JP4918695B2 - メモリデバイス用分離トレンチ - Google Patents
メモリデバイス用分離トレンチ Download PDFInfo
- Publication number
- JP4918695B2 JP4918695B2 JP2007519287A JP2007519287A JP4918695B2 JP 4918695 B2 JP4918695 B2 JP 4918695B2 JP 2007519287 A JP2007519287 A JP 2007519287A JP 2007519287 A JP2007519287 A JP 2007519287A JP 4918695 B2 JP4918695 B2 JP 4918695B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- layer
- dielectric layer
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002955 isolation Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 42
- 238000007667 floating Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 78
- 238000000137 annealing Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 230000005641 tunneling Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Description
104…メモリアレイ 106…アドレスデコーダ
108…行アクセス回路 110…列アクセス回路
112…制御回路 114…I/O回路
116…アドレスバッファ回路 120…マイクロプロセッサ
122…制御リンク 124…データリンク
126…アドレスリンク 200…基板
202…第1誘電体層 204、260…導電層
206…マスク層 210…トレンチ
212…第3誘電体層 220…第4誘電体層
230…第5誘電体層 232…第1の誘電体充填層
240…第6誘電体層 242…第2の誘電体充填層
250…ゲート間誘電体層
Claims (19)
- 基板内を延在するトレンチの一部に、第1誘電体の層と前記第1誘電体の層上に形成された第2誘電体の層とを備える第1の誘電体充填層を、その上側表面が、前記基板の上側表面よりも下方に位置するように形成するステップと、
第3誘電体からなる第2の誘電体充填層を、前記第1の誘電体充填層の上側表面に、前記第1の誘電体充填層の上側表面から、その上方に向かって、前記基板の上側表面上に形成された第4誘電体の層と、その上に形成された第1導電層とを貫通する前記トレンチの残余の部分にわたって延在し、且つ前記第4誘電体の層の一部と前記第1導電層の一部とに接するように形成するステップと、
前記第2の誘電体充填層を形成するステップの後、
前記第1導電層上に第5誘電体の層を形成するステップと、
前記第5誘電体の層上に第2導電層を形成するステップと、を備え、
前記第5誘電体の層の上側表面は、前記第2の誘電体充填層の上側表面よりも下方に配置されることを特徴するメモリデバイスの一部を形成する方法。 - 請求項1記載の方法において、第1の誘電体充填層を形成する前記ステップは、前記トレンチの一部を覆い、且つ前記基板上に配置された第6誘電体の層上に、前記第1誘電体の層を形成するステップをさらに備えることを特徴とする方法。
- 請求項2記載の方法において、第2の誘電体充填層を形成する前記ステップは、前記第6誘電体の層上に前記第2の誘電体充填層の一部を形成するステップを備えることを特徴とする方法。
- 請求項1〜3のいずれか1項に記載の方法において、前記第1誘電体は窒化物であり、前記第2誘電体はスピンオン誘電体であり、前記第3誘電体は高密度プラズマによる酸化物であることを特徴とする方法。
- 請求項1〜4のいずれか1項に記載の方法において、第1の誘電体充填層を形成する前記ステップは、前記第2誘電体の層をキュアするステップをさらに備えることを特徴とする方法。
- 請求項5記載の方法において、前記第2誘電体の層をキュアする前記ステップは酸化工程を備えることを特徴とする方法。
- 請求項1〜6のいずれか1項に記載の方法において、前記第4誘電体の層は、トンネル誘電体層であることを特徴とする方法。
- 請求項1〜7のいずれか1項に記載の方法において、前記トレンチは、前記第1導電層上に配置されたハードマスク層をパターニングして、エッチングすることによって形成されることを特徴とする方法。
- 請求項1〜8のいずれか1項に記載の方法において、前記第1の誘電体充填層を形成する前記ステップは、
前記第1誘電体の層上に前記第2誘電体の層を形成して、前記第2誘電体の層で前記トレンチを前記基板の上側表面より上のレベルまで充填するステップと、
前記第2誘電体の層の一部を除去して、前記第2誘電体の層の上側表面を前記基板の上側表面よりも下方に位置させるステップと、
を備えることを特徴とする方法。 - 請求項9記載の方法において、前記第1の誘電体充填層を形成する前記ステップは、前記第1誘電体の層の一部を前記第2誘電体の層の上側表面のレベルまで選択的に除去するステップをさらに備えることを特徴とする方法。
- 請求項9又は10のいずれか1項に記載の方法において、前記第2誘電体の層の一部を除去する前記ステップの前に、前記第2誘電体の層をアニールするステップをさらに備えることを特徴とする方法。
- 請求項1〜7、9〜11のいずれか1項に記載の方法において、前記第5誘電体の層は、ゲート間誘電体層であることを特徴とする方法。
- 請求項12記載の方法において、前記第1導電層は浮遊ゲート層であり、前記第2導電層は制御ゲート層であることを特徴とする方法。
- 第1誘電体の層とその層上に形成された第2誘電体の層とを有し、基板内に延在するトレンチ内に配置され、上側表面が、前記基板の上側表面よりも下方に位置している第1の誘電体充填層と、
前記トレンチ内の前記第1の誘電体充填層の上側表面上に配置され、前記基板の上側表面上に形成された第4誘電体の層と、その層上に形成された第1導電層とを貫通し、前記第4誘電体の層の一部と前記第1導電層の一部とに接する、第3誘電体からなる第2の誘電体充填層と、
前記第1導電層上に形成された第5誘電体の層と、
前記第5誘電体の層上に形成された第2導電層と、
を備える集積回路デバイスであって、
前記第5誘電体の層の上側表面は、前記第2の誘電体充填層の上側表面よりも下方に位置していることを特徴とする集積回路デバイス。 - 請求項14記載の集積回路デバイスにおいて、前記基板と前記第1の誘電体充填層の前記第1誘電体との間に介在し、且つ前記第2の誘電体充填層の一部と前記基板との間に介在する第6誘電体の層をさらに備えることを特徴とする集積回路デバイス。
- 請求項14又は15のいずれか1項に記載の集積回路デバイスにおいて、前記第1誘電体は窒化物であり、前記第2誘電体はアニールされたスピンオン誘電体であることを特徴とする集積回路デバイス。
- 請求項14〜16のいずれか1項に記載の集積回路デバイスにおいて、前記第3誘電体は高密度プラズマによる酸化物であることを特徴とする集積回路デバイス。
- 請求項14〜17のいずれか1項に記載の集積回路デバイスにおいて、前記第4誘電体の層は、トンネル誘電体層であり、前記第1導電層は浮遊ゲート層であり、前記第5誘電体の層は、層間誘電体層であり、且つ前記第2導電層は、制御ゲート層であることを特徴とする集積回路デバイス。
- 請求項14〜18のいずれか1項に記載の集積回路デバイスにおいて、前記集積回路デバイスはメモリデバイスであることを特徴とする集積回路デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/878,805 | 2004-06-28 | ||
US10/878,805 US7332408B2 (en) | 2004-06-28 | 2004-06-28 | Isolation trenches for memory devices |
PCT/US2005/022143 WO2006012163A1 (en) | 2004-06-28 | 2005-06-22 | Isolation trenches for memory devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008504713A JP2008504713A (ja) | 2008-02-14 |
JP4918695B2 true JP4918695B2 (ja) | 2012-04-18 |
Family
ID=35169961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007519287A Active JP4918695B2 (ja) | 2004-06-28 | 2005-06-22 | メモリデバイス用分離トレンチ |
Country Status (6)
Country | Link |
---|---|
US (5) | US7332408B2 (ja) |
EP (1) | EP1774586B1 (ja) |
JP (1) | JP4918695B2 (ja) |
SG (1) | SG141446A1 (ja) |
TW (1) | TWI316745B (ja) |
WO (1) | WO2006012163A1 (ja) |
Families Citing this family (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4594648B2 (ja) * | 2004-05-26 | 2010-12-08 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7332408B2 (en) | 2004-06-28 | 2008-02-19 | Micron Technology, Inc. | Isolation trenches for memory devices |
KR100546161B1 (ko) * | 2004-07-13 | 2006-01-24 | 주식회사 하이닉스반도체 | 반도체 소자의 소자 분리막 제조 방법 |
US7358586B2 (en) * | 2004-09-28 | 2008-04-15 | International Business Machines Corporation | Silicon-on-insulator wafer having reentrant shape dielectric trenches |
US7402487B2 (en) * | 2004-10-18 | 2008-07-22 | Infineon Technologies Richmond, Lp | Process for fabricating a semiconductor device having deep trench structures |
US7259055B2 (en) * | 2005-02-24 | 2007-08-21 | Sharp Laboratories Of America, Inc. | Method of forming high-luminescence silicon electroluminescence device |
KR100685730B1 (ko) * | 2005-05-02 | 2007-02-26 | 삼성전자주식회사 | 절연막 구조물의 형성 방법 및 이를 이용한 반도체 장치의제조 방법 |
JP2006351881A (ja) * | 2005-06-16 | 2006-12-28 | Toshiba Corp | 半導体記憶装置及び半導体記憶装置の製造方法 |
US20070010070A1 (en) * | 2005-07-05 | 2007-01-11 | International Business Machines Corporation | Fabrication of strained semiconductor-on-insulator (ssoi) structures by using strained insulating layers |
US20070235783A9 (en) * | 2005-07-19 | 2007-10-11 | Micron Technology, Inc. | Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions |
US7842618B2 (en) * | 2005-08-01 | 2010-11-30 | Spansion Llc | System and method for improving mesa width in a semiconductor device |
US7772672B2 (en) | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Semiconductor constructions |
EP1770772B1 (en) * | 2005-09-30 | 2012-07-18 | STMicroelectronics Srl | Process for manufacturing a non-volatile memory device |
US7514742B2 (en) * | 2005-10-13 | 2009-04-07 | Macronix International Co., Ltd. | Recessed shallow trench isolation |
JP5010244B2 (ja) * | 2005-12-15 | 2012-08-29 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
JP2007165696A (ja) * | 2005-12-15 | 2007-06-28 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US8501632B2 (en) * | 2005-12-20 | 2013-08-06 | Infineon Technologies Ag | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
US8936995B2 (en) | 2006-03-01 | 2015-01-20 | Infineon Technologies Ag | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
US7811935B2 (en) * | 2006-03-07 | 2010-10-12 | Micron Technology, Inc. | Isolation regions and their formation |
US20070212874A1 (en) * | 2006-03-08 | 2007-09-13 | Micron Technology, Inc. | Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device |
US7691722B2 (en) | 2006-03-14 | 2010-04-06 | Micron Technology, Inc. | Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability |
JP5132068B2 (ja) * | 2006-03-27 | 2013-01-30 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20070232019A1 (en) * | 2006-03-30 | 2007-10-04 | Hynix Semiconductor Inc. | Method for forming isolation structure in nonvolatile memory device |
US7799694B2 (en) | 2006-04-11 | 2010-09-21 | Micron Technology, Inc. | Methods of forming semiconductor constructions |
US7977190B2 (en) * | 2006-06-21 | 2011-07-12 | Micron Technology, Inc. | Memory devices having reduced interference between floating gates and methods of fabricating such devices |
JP2008010724A (ja) * | 2006-06-30 | 2008-01-17 | Sharp Corp | 半導体装置及びその製造方法 |
US7968425B2 (en) * | 2006-07-14 | 2011-06-28 | Micron Technology, Inc. | Isolation regions |
JP2008041901A (ja) * | 2006-08-04 | 2008-02-21 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100790252B1 (ko) * | 2006-08-11 | 2008-01-02 | 동부일렉트로닉스 주식회사 | Cmos 이미지 센서 제조방법 |
KR100871642B1 (ko) * | 2006-09-29 | 2008-12-02 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자의 제조방법 |
US7645670B2 (en) | 2006-09-29 | 2010-01-12 | Hynix Semiconductor Inc. | Method for fabricating nonvolatile memory device |
JP2008098420A (ja) * | 2006-10-12 | 2008-04-24 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
KR100830579B1 (ko) * | 2006-10-19 | 2008-05-21 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 형성 방법 |
KR100790296B1 (ko) * | 2006-12-04 | 2008-01-02 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
KR100893595B1 (ko) | 2006-12-27 | 2009-04-17 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
KR101026479B1 (ko) * | 2006-12-28 | 2011-04-01 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
DE102007008530B4 (de) * | 2007-02-21 | 2015-11-12 | Infineon Technologies Ag | Verfahren zum Herstellen einer nichtflüchtigen Speichervorrichtung, nichtflüchtige Speichervorrichtung, Speicherkarte mit einer nichtflüchtigen Speichervorrichtung und elektrisches Gerät mit einer Speicherkarte |
US7704832B2 (en) * | 2007-04-02 | 2010-04-27 | Sandisk Corporation | Integrated non-volatile memory and peripheral circuitry fabrication |
JP5301108B2 (ja) * | 2007-04-20 | 2013-09-25 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置 |
TW200847328A (en) * | 2007-05-23 | 2008-12-01 | Promos Technologies Inc | Method for preparing a shallow trench isolation |
GB0710335D0 (en) * | 2007-05-31 | 2007-07-11 | Aviza Technologies Ltd | A method of filling trenches on a substrate |
KR100946116B1 (ko) * | 2007-06-27 | 2010-03-10 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 소자 분리막 형성 방법 |
KR100972881B1 (ko) * | 2007-06-28 | 2010-07-28 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 형성 방법 |
US7892942B2 (en) * | 2007-07-09 | 2011-02-22 | Micron Technology Inc. | Methods of forming semiconductor constructions, and methods of forming isolation regions |
JP2009032929A (ja) * | 2007-07-27 | 2009-02-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
KR101034950B1 (ko) * | 2007-09-10 | 2011-05-17 | 주식회사 하이닉스반도체 | 반도체 소자의 소자 분리막 형성 방법 |
JP2009076637A (ja) * | 2007-09-20 | 2009-04-09 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
KR101002548B1 (ko) * | 2007-10-10 | 2010-12-17 | 주식회사 하이닉스반도체 | 반도체 소자의 소자 분리막 형성 방법 |
KR101002493B1 (ko) * | 2007-12-28 | 2010-12-17 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 소자 분리막 형성 방법 |
KR100941865B1 (ko) * | 2008-03-10 | 2010-02-11 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
KR100980058B1 (ko) * | 2008-03-27 | 2010-09-03 | 주식회사 하이닉스반도체 | 메모리 소자의 소자분리 구조 및 형성 방법 |
US7915124B2 (en) * | 2008-07-09 | 2011-03-29 | Sandisk Corporation | Method of forming dielectric layer above floating gate for reducing leakage current |
US7919809B2 (en) * | 2008-07-09 | 2011-04-05 | Sandisk Corporation | Dielectric layer above floating gate for reducing leakage current |
US8138036B2 (en) * | 2008-08-08 | 2012-03-20 | International Business Machines Corporation | Through silicon via and method of fabricating same |
JP2010098293A (ja) * | 2008-09-22 | 2010-04-30 | Elpida Memory Inc | 半導体装置 |
KR101003496B1 (ko) * | 2008-09-29 | 2010-12-30 | 주식회사 하이닉스반도체 | 소자분리 구조 및 리세스 게이트를 포함하는 반도체 소자 및 제조 방법 |
US8207036B2 (en) * | 2008-09-30 | 2012-06-26 | Sandisk Technologies Inc. | Method for forming self-aligned dielectric cap above floating gate |
US8367515B2 (en) * | 2008-10-06 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid shallow trench isolation for high-k metal gate device improvement |
US7910491B2 (en) * | 2008-10-16 | 2011-03-22 | Applied Materials, Inc. | Gapfill improvement with low etch rate dielectric liners |
US7972933B2 (en) * | 2009-03-31 | 2011-07-05 | Applied Materials, Inc. | Method of selective nitridation |
US8320181B2 (en) * | 2009-08-25 | 2012-11-27 | Micron Technology, Inc. | 3D memory devices decoding and routing systems and methods |
US8048755B2 (en) | 2010-02-08 | 2011-11-01 | Micron Technology, Inc. | Resistive memory and methods of processing resistive memory |
US8461016B2 (en) | 2011-10-07 | 2013-06-11 | Micron Technology, Inc. | Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation |
US8907396B2 (en) | 2012-01-04 | 2014-12-09 | Micron Technology, Inc | Source/drain zones with a delectric plug over an isolation region between active regions and methods |
KR102001597B1 (ko) * | 2012-12-11 | 2019-07-19 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
US9515172B2 (en) | 2014-01-28 | 2016-12-06 | Samsung Electronics Co., Ltd. | Semiconductor devices having isolation insulating layers and methods of manufacturing the same |
JP2015204443A (ja) * | 2014-04-16 | 2015-11-16 | マイクロン テクノロジー, インク. | 半導体装置およびその製造方法 |
WO2016054079A1 (en) | 2014-09-29 | 2016-04-07 | Zyomed Corp. | Systems and methods for blood glucose and other analyte detection and measurement using collision computing |
KR102181686B1 (ko) * | 2014-12-04 | 2020-11-23 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
CN106340455B (zh) * | 2015-07-06 | 2021-08-03 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
US9673207B2 (en) | 2015-08-20 | 2017-06-06 | Sandisk Technologies Llc | Shallow trench isolation trenches and methods for NAND memory |
US9991280B2 (en) | 2016-02-17 | 2018-06-05 | Sandisk Technologies Llc | Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same |
US9935000B2 (en) | 2016-02-29 | 2018-04-03 | Intel Corporation | Slit stress modulation in semiconductor substrates |
US9554738B1 (en) | 2016-03-30 | 2017-01-31 | Zyomed Corp. | Spectroscopic tomography systems and methods for noninvasive detection and measurement of analytes using collision computing |
CN108538839B (zh) * | 2017-03-01 | 2019-08-23 | 联华电子股份有限公司 | 半导体结构、用于存储器元件的半导体结构及其制作方法 |
US11171206B2 (en) * | 2019-07-11 | 2021-11-09 | Micron Technology, Inc. | Channel conduction in semiconductor devices |
US11114443B2 (en) * | 2019-08-29 | 2021-09-07 | Micron Technology, Inc. | Semiconductor structure formation |
CN112635470B (zh) * | 2019-10-09 | 2024-03-05 | 华邦电子股份有限公司 | 半导体结构及其形成方法 |
US11664438B2 (en) * | 2019-11-05 | 2023-05-30 | Winbond Electronics Corp. | Semiconductor structure and method for forming the same |
US20210143275A1 (en) * | 2019-11-11 | 2021-05-13 | Integrated Silicon Solution Inc. | Finfet stack gate memory and mehod of forming thereof |
TWI730677B (zh) | 2020-03-18 | 2021-06-11 | 力晶積成電子製造股份有限公司 | 記憶體元件及其製造方法 |
US11502165B2 (en) | 2020-07-08 | 2022-11-15 | Nanya Technology Corporation | Semiconductor device with flowable layer and method for fabricating the same |
KR20230059028A (ko) * | 2021-10-25 | 2023-05-03 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000286254A (ja) * | 1999-03-31 | 2000-10-13 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2002203895A (ja) * | 2000-12-08 | 2002-07-19 | Samsung Electronics Co Ltd | トレンチ素子分離膜の形成方法 |
JP2002208629A (ja) * | 2000-11-09 | 2002-07-26 | Toshiba Corp | 半導体装置、及び、半導体装置の製造方法 |
JP2004134759A (ja) * | 2002-10-10 | 2004-04-30 | Samsung Electronics Co Ltd | トレンチ隔離された半導体素子の形成方法及びそれによって形成されたトレンチ隔離された半導体素子 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6322634B1 (en) * | 1997-01-27 | 2001-11-27 | Micron Technology, Inc. | Shallow trench isolation structure without corner exposure |
US5976947A (en) * | 1997-08-18 | 1999-11-02 | Micron Technology, Inc. | Method for forming dielectric within a recess |
JP3470182B2 (ja) * | 1999-08-27 | 2003-11-25 | リアル化学株式会社 | 新規な染毛剤およびそれを用いた染毛方法 |
US6413827B2 (en) * | 2000-02-14 | 2002-07-02 | Paul A. Farrar | Low dielectric constant shallow trench isolation |
US6437417B1 (en) * | 2000-08-16 | 2002-08-20 | Micron Technology, Inc. | Method for making shallow trenches for isolation |
KR100351506B1 (en) * | 2000-11-30 | 2002-09-05 | Samsung Electronics Co Ltd | Method for forming insulation layer of semiconductor device |
US6897120B2 (en) * | 2001-01-03 | 2005-05-24 | Micron Technology, Inc. | Method of forming integrated circuitry and method of forming shallow trench isolation in a semiconductor substrate |
KR100568100B1 (ko) | 2001-03-05 | 2006-04-05 | 삼성전자주식회사 | 트렌치형 소자 분리막 형성 방법 |
KR100512167B1 (ko) | 2001-03-12 | 2005-09-02 | 삼성전자주식회사 | 트렌치 소자 분리형 반도체 장치 및 트렌치형 소자 분리막형성방법 |
US6737333B2 (en) | 2001-07-03 | 2004-05-18 | Texas Instruments Incorporated | Semiconductor device isolation structure and method of forming |
US6531377B2 (en) | 2001-07-13 | 2003-03-11 | Infineon Technologies Ag | Method for high aspect ratio gap fill using sequential HDP-CVD |
KR100395759B1 (ko) * | 2001-07-21 | 2003-08-21 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 제조방법 |
KR100428805B1 (ko) * | 2001-08-09 | 2004-04-28 | 삼성전자주식회사 | 트렌치 소자분리 구조체 및 그 형성 방법 |
US6798038B2 (en) | 2001-09-20 | 2004-09-28 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device with filling insulating film into trench |
TWI248159B (en) | 2002-01-25 | 2006-01-21 | Nanya Technology Corp | Manufacturing method for shallow trench isolation with high aspect ratio |
US6627529B2 (en) * | 2002-02-07 | 2003-09-30 | Micron Technology, Inc. | Capacitance reduction by tunnel formation for use with semiconductor device |
KR100454135B1 (ko) * | 2002-10-10 | 2004-10-26 | 삼성전자주식회사 | 비휘발성 기억소자의 형성방법 |
JP2004207564A (ja) | 2002-12-26 | 2004-07-22 | Fujitsu Ltd | 半導体装置の製造方法と半導体装置 |
US6890833B2 (en) * | 2003-03-26 | 2005-05-10 | Infineon Technologies Ag | Trench isolation employing a doped oxide trench fill |
US6693050B1 (en) | 2003-05-06 | 2004-02-17 | Applied Materials Inc. | Gapfill process using a combination of spin-on-glass deposition and chemical vapor deposition techniques |
KR100512939B1 (ko) * | 2003-07-10 | 2005-09-07 | 삼성전자주식회사 | 트렌치 소자분리 방법 |
JP2005166700A (ja) * | 2003-11-28 | 2005-06-23 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005251973A (ja) | 2004-03-04 | 2005-09-15 | Fujitsu Ltd | 半導体装置の製造方法と半導体装置 |
US7332408B2 (en) * | 2004-06-28 | 2008-02-19 | Micron Technology, Inc. | Isolation trenches for memory devices |
-
2004
- 2004-06-28 US US10/878,805 patent/US7332408B2/en active Active
-
2005
- 2005-05-16 US US11/129,884 patent/US7439157B2/en active Active
- 2005-06-22 SG SG200802159-4A patent/SG141446A1/en unknown
- 2005-06-22 EP EP05766678.6A patent/EP1774586B1/en active Active
- 2005-06-22 WO PCT/US2005/022143 patent/WO2006012163A1/en active Application Filing
- 2005-06-22 JP JP2007519287A patent/JP4918695B2/ja active Active
- 2005-06-24 TW TW094121143A patent/TWI316745B/zh active
-
2006
- 2006-11-16 US US11/600,350 patent/US7332789B2/en not_active Expired - Lifetime
-
2007
- 2007-12-21 US US11/962,967 patent/US7892943B2/en active Active
-
2010
- 2010-09-27 US US12/891,248 patent/US8049298B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000286254A (ja) * | 1999-03-31 | 2000-10-13 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2002208629A (ja) * | 2000-11-09 | 2002-07-26 | Toshiba Corp | 半導体装置、及び、半導体装置の製造方法 |
JP2002203895A (ja) * | 2000-12-08 | 2002-07-19 | Samsung Electronics Co Ltd | トレンチ素子分離膜の形成方法 |
JP2004134759A (ja) * | 2002-10-10 | 2004-04-30 | Samsung Electronics Co Ltd | トレンチ隔離された半導体素子の形成方法及びそれによって形成されたトレンチ隔離された半導体素子 |
Also Published As
Publication number | Publication date |
---|---|
US7332408B2 (en) | 2008-02-19 |
US20050287731A1 (en) | 2005-12-29 |
US20110012186A1 (en) | 2011-01-20 |
US20080128781A1 (en) | 2008-06-05 |
EP1774586A1 (en) | 2007-04-18 |
TW200608514A (en) | 2006-03-01 |
JP2008504713A (ja) | 2008-02-14 |
EP1774586B1 (en) | 2019-08-07 |
TWI316745B (en) | 2009-11-01 |
WO2006012163A1 (en) | 2006-02-02 |
US20050285179A1 (en) | 2005-12-29 |
US20070063258A1 (en) | 2007-03-22 |
US7892943B2 (en) | 2011-02-22 |
SG141446A1 (en) | 2008-04-28 |
US8049298B2 (en) | 2011-11-01 |
US7332789B2 (en) | 2008-02-19 |
US7439157B2 (en) | 2008-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4918695B2 (ja) | メモリデバイス用分離トレンチ | |
US11398493B2 (en) | Arrays of memory cells including pairs of memory cells having respective charge storage nodes between respective access lines | |
US7344942B2 (en) | Isolation regions for semiconductor devices and their formation | |
US7453134B2 (en) | Integrated circuit device with a circuit element formed on an active region having rounded corners | |
US8546888B2 (en) | Isolation regions | |
US8716084B2 (en) | Memory array with an air gap between memory cells and the formation thereof | |
US8284616B2 (en) | Trench memory structure operation | |
TW200939405A (en) | Semiconductor constructions, NAND unit cells, methods of forming semiconductor constructions, and methods of forming NAND unit cells | |
US7348236B2 (en) | Formation of memory cells and select gates of NAND memory arrays | |
KR100865012B1 (ko) | 메모리 디바이스를 위한 분리 트렌치 | |
JP2010212506A (ja) | 半導体記憶装置及びその製造方法 | |
KR20100074525A (ko) | 플래시 메모리 소자의 제조방법 | |
KR100773688B1 (ko) | 반도체 소자의 제조방법 | |
KR100880227B1 (ko) | 플래시 메모리 소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100217 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110118 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110418 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110425 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110518 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111220 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20111227 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20111227 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120111 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4918695 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150210 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |