JP4913717B2 - 2つの電極間にドリフト経路を有する電荷補償部材 - Google Patents
2つの電極間にドリフト経路を有する電荷補償部材 Download PDFInfo
- Publication number
- JP4913717B2 JP4913717B2 JP2007328288A JP2007328288A JP4913717B2 JP 4913717 B2 JP4913717 B2 JP 4913717B2 JP 2007328288 A JP2007328288 A JP 2007328288A JP 2007328288 A JP2007328288 A JP 2007328288A JP 4913717 B2 JP4913717 B2 JP 4913717B2
- Authority
- JP
- Japan
- Prior art keywords
- drift path
- drift
- zone
- charge compensation
- doping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000007423 decrease Effects 0.000 claims description 24
- 230000000295 complement effect Effects 0.000 claims description 21
- 239000002019 doping agent Substances 0.000 description 47
- 238000004519 manufacturing process Methods 0.000 description 42
- 239000004065 semiconductor Substances 0.000 description 31
- 230000005684 electric field Effects 0.000 description 27
- 239000000758 substrate Substances 0.000 description 27
- 239000002800 charge carrier Substances 0.000 description 20
- 230000008859 change Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 230000035515 penetration Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本発明は、電極と対向電極とから成る2つの電極間に、ドリフト経路を有する電荷補償部材とその製造方法に関する。上記ドリフト経路は、第1の伝導型のドリフトゾーンと、該第1の伝導型に対して相補的な伝導型の電荷補償ゾーンとを有する。
本発明の一実施形態は、ロバスト設計の電荷補償部材を提供するものである。該電荷補償部材は、簡素化された製造プロセスに従って製造され、このために、プロセス変動に対する影響を受けにくい。
図1は、本発明に係る第1の形態のドリフト経路のb〜eまでのドーパントプロファイルと、従来技術のUS 5,216,275に係るドーパントプロファイルとの比較を該略的に示す図である。上記ドリフトゾーン内の第1の伝導型n、および、上記電荷補償ゾーン内の相補的な伝導型pの、立方センチメートル当りのドーパント濃度またはその結果として生じる電荷キャリア濃度が、均等目盛で縦座標上に示されている。上記ドリフト経路の侵入深度xが、マイクロメートル(μm)の単位で、横座標上に示されている。
だけ降下させている。上記電極に対する端部領域で行われる変調ドーピングΔpの結果として生じる逆電圧の低下によって、オン抵抗が改善され、これによって該オン抵抗は低減される。しかしながら、本発明のように、上記電極に近接して、上記ドリフト経路層ドーピングを上昇させる場合には、上記逆電圧の低下が少なく、許容されることが可能である。
本発明のさらなる実施形態では、上記ドリフト経路ドーピングは、互いに向かい合って配置されている2つの電極に近接した両領域から、上記ドリフト経路の中心領域に向かって、減少するドーピングを有する。これは、上記中心領域において、p型オーバードーピングからn型オーバードーピングまで、または、n型アンダードーピングからp型アンダードーピングまで急変させることによって、実現することが可能である。上記ドリフト経路層ドーピングを急激に変化させることは、このドリフト経路にエピタキシャル層を一層毎に成長させることによって、比較的容易に行うことが可能である。
Claims (6)
- 第1の電極と、
対向電極と、
これら電極間に設けられるドリフト経路とを有し、
上記ドリフト経路は、
第1の伝導型のドリフトゾーンと、
上記第1の伝導型に対して相補的な伝導型の電荷補償ゾーンとを含み、
垂直に伸びるドリフト経路に、水平なドリフト経路層のドーピング位置が重ね合わせられたドリフト経路層ドーピングがなされており、
上記ドリフトゾーンと上記電荷補償ゾーンとは、上記ドリフト経路に沿って平行に位置付けられ、
上記垂直に伸びるドリフト経路は、上記ドリフト経路層内に配置された、上記ドリフトゾーンの領域と上記電荷補償ゾーンの領域とを含み、
上記ドリフト経路層ドーピングは、このドリフト経路の中心領域(xm)に向かう方向においてよりも、2つの上記電極の近傍においてのほうがより大きく、
上記ドリフトゾーンにおけるドーピング位置の濃度プロファイルと、上記電荷補償ゾーンにおけるドーピング位置の濃度プロファイルとは、増減の傾向が同一であることを特徴とする電荷補償部材。 - 上記ドリフト経路層ドーピングは、互いに向かい合っている2つの電極に近接した両領域から上記ドリフト経路の中心領域にかけて、上記ドリフトゾーンと上記電荷補償ゾーンとの両方において、段階的な減少を含むことを特徴とする請求項1に記載の電荷補償部材。
- 上記ドリフト経路層ドーピングは、互いに向かい合っている2つの電極に近接した両領域から上記ドリフト経路の中心領域にかけて、上記ドリフトゾーンと上記電荷補償ゾーンとの両方において、1つの急減を含むことを特徴とする請求項1に記載の電荷補償部材。
- 上記ドリフト経路層ドーピングは、互いに向かい合っている2つの電極に近接した両領域から上記ドリフト経路の中心領域にかけて、上記ドリフトゾーンと上記電荷補償ゾーンとの両方において、直線的な減少を含むことを特徴とする請求項1に記載の電荷補償部材。
- 上記ドリフト経路層ドーピングは、互いに向かい合っている2つの電極に近接した両領域から上記ドリフト経路の中心領域にかけて、上記ドリフトゾーンと上記電荷補償ゾーンとの両方において、連続的な非直線状の減少を含むことを特徴とする請求項1に記載の電荷補償部材。
- 上記ドリフト経路は、パワーダイオードまたは高電圧ダイオードのアノード領域とカソード領域との間に配置されることを特徴とする請求項1に記載の電荷補償部材。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006061994A DE102006061994B4 (de) | 2006-12-21 | 2006-12-21 | Ladungskompensationsbauelement mit einer Driftstrecke zwischen zwei Elektroden und Verfahren zur Herstellung desselben |
DE102006061994.3 | 2006-12-21 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011266218A Division JP5519623B2 (ja) | 2006-12-21 | 2011-12-05 | 2つの電極間にドリフト経路を有する電荷補償部材 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008205431A JP2008205431A (ja) | 2008-09-04 |
JP4913717B2 true JP4913717B2 (ja) | 2012-04-11 |
Family
ID=39509685
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007328288A Expired - Fee Related JP4913717B2 (ja) | 2006-12-21 | 2007-12-20 | 2つの電極間にドリフト経路を有する電荷補償部材 |
JP2011266218A Active JP5519623B2 (ja) | 2006-12-21 | 2011-12-05 | 2つの電極間にドリフト経路を有する電荷補償部材 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011266218A Active JP5519623B2 (ja) | 2006-12-21 | 2011-12-05 | 2つの電極間にドリフト経路を有する電荷補償部材 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7968919B2 (ja) |
JP (2) | JP4913717B2 (ja) |
DE (1) | DE102006061994B4 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554137B2 (en) * | 2005-10-25 | 2009-06-30 | Infineon Technologies Austria Ag | Power semiconductor component with charge compensation structure and method for the fabrication thereof |
US8525254B2 (en) | 2010-08-12 | 2013-09-03 | Infineon Technologies Austria Ag | Silicone carbide trench semiconductor device |
KR101876573B1 (ko) * | 2011-12-23 | 2018-07-10 | 매그나칩 반도체 유한회사 | 반도체 소자 및 그 제조 방법 |
KR101795828B1 (ko) | 2013-09-17 | 2017-11-10 | 매그나칩 반도체 유한회사 | 초접합 반도체 소자 및 제조 방법 |
CN204067367U (zh) * | 2014-06-09 | 2014-12-31 | 英飞凌科技股份有限公司 | 功率半导体器件 |
CN105914233B (zh) * | 2016-05-26 | 2018-09-18 | 东南大学 | 一种高鲁棒性快恢复超结功率半导体晶体管及其制备方法 |
DE102016111844A1 (de) | 2016-06-28 | 2017-12-28 | Infineon Technologies Ag | Leistungshalbleitervorrichtung |
DE102016115559B4 (de) * | 2016-08-22 | 2020-06-04 | Infineon Technologies Austria Ag | Transistorbauelement mit verbesserter leckstromcharakteristik |
DE102016115805B4 (de) | 2016-08-25 | 2020-07-09 | Infineon Technologies Austria Ag | Transistorbauelement mit hoher lawinen-festigkeit |
JP6809071B2 (ja) * | 2016-09-14 | 2021-01-06 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN109729743B (zh) | 2016-11-11 | 2021-12-28 | 新电元工业株式会社 | Mosfet以及电力转换电路 |
CN106684120B (zh) * | 2017-03-09 | 2020-07-10 | 山东大学 | 一种可提高耐压的局部非平衡超结结构 |
US10872952B1 (en) * | 2017-05-26 | 2020-12-22 | Shindengen Electric Manufacturing Co., Ltd. | MOSFET and power conversion circuit |
US10644102B2 (en) * | 2017-12-28 | 2020-05-05 | Alpha And Omega Semiconductor (Cayman) Ltd. | SGT superjunction MOSFET structure |
JP6833778B2 (ja) | 2018-09-11 | 2021-02-24 | 株式会社東芝 | 半導体装置 |
IT201900013416A1 (it) | 2019-07-31 | 2021-01-31 | St Microelectronics Srl | Dispositivo di potenza a bilanciamento di carica e procedimento di fabbricazione del dispositivo di potenza a bilanciamento di carica |
KR102306123B1 (ko) | 2020-03-19 | 2021-09-28 | 파워마스터반도체 주식회사 | 반도체 장치 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
JPS59107569A (ja) * | 1982-12-13 | 1984-06-21 | Fuji Photo Film Co Ltd | 一次元半導体撮像装置 |
US5216278A (en) | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
CN1019720B (zh) * | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
JP3988262B2 (ja) * | 1998-07-24 | 2007-10-10 | 富士電機デバイステクノロジー株式会社 | 縦型超接合半導体素子およびその製造方法 |
DE19840032C1 (de) * | 1998-09-02 | 1999-11-18 | Siemens Ag | Halbleiterbauelement und Herstellungsverfahren dazu |
JP4447065B2 (ja) * | 1999-01-11 | 2010-04-07 | 富士電機システムズ株式会社 | 超接合半導体素子の製造方法 |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
US6475864B1 (en) * | 1999-10-21 | 2002-11-05 | Fuji Electric Co., Ltd. | Method of manufacturing a super-junction semiconductor device with an conductivity type layer |
DE10024480B4 (de) * | 2000-05-18 | 2006-02-16 | Infineon Technologies Ag | Kompensationsbauelement mit verbesserter Robustheit |
DE10120656C2 (de) * | 2001-04-27 | 2003-07-10 | Infineon Technologies Ag | Halbleiterbauelement mit erhöhter Avalanche-Festigkeit |
DE10132136C1 (de) * | 2001-07-03 | 2003-02-13 | Infineon Technologies Ag | Halbleiterbauelement mit Ladungskompensationsstruktur sowie zugehöriges Herstellungsverfahren |
CN1663049A (zh) | 2002-06-26 | 2005-08-31 | 剑桥半导体有限公司 | 横向半导体器件 |
JP3634830B2 (ja) * | 2002-09-25 | 2005-03-30 | 株式会社東芝 | 電力用半導体素子 |
DE10245049B4 (de) * | 2002-09-26 | 2007-07-05 | Infineon Technologies Ag | Kompensationshalbleiterbauelement |
US6825513B2 (en) * | 2002-09-27 | 2004-11-30 | Xerox Corporation | High power mosfet semiconductor device |
JP4851694B2 (ja) * | 2004-08-24 | 2012-01-11 | 株式会社東芝 | 半導体装置の製造方法 |
EP1696490A1 (en) * | 2005-02-25 | 2006-08-30 | STMicroelectronics S.r.l. | Charge compensation semiconductor device and relative manufacturing process |
JP4939760B2 (ja) * | 2005-03-01 | 2012-05-30 | 株式会社東芝 | 半導体装置 |
JP2007012858A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 半導体素子及びその製造方法 |
DE102005048447B4 (de) * | 2005-10-07 | 2007-07-19 | Infineon Technologies Ag | Halbleiterleistungsbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben |
JP2008091450A (ja) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | 半導体素子 |
-
2006
- 2006-12-21 DE DE102006061994A patent/DE102006061994B4/de active Active
-
2007
- 2007-12-20 US US11/961,235 patent/US7968919B2/en active Active
- 2007-12-20 JP JP2007328288A patent/JP4913717B2/ja not_active Expired - Fee Related
-
2011
- 2011-12-05 JP JP2011266218A patent/JP5519623B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
DE102006061994B4 (de) | 2011-05-05 |
JP2012094881A (ja) | 2012-05-17 |
DE102006061994A1 (de) | 2008-07-17 |
JP2008205431A (ja) | 2008-09-04 |
JP5519623B2 (ja) | 2014-06-11 |
US20080150073A1 (en) | 2008-06-26 |
US7968919B2 (en) | 2011-06-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4913717B2 (ja) | 2つの電極間にドリフト経路を有する電荷補償部材 | |
AU2011375931B2 (en) | Semiconductor device | |
US9190469B2 (en) | Super junction semiconductor device and method for manufacturing the same | |
US20170271442A1 (en) | Semiconductor device | |
US20160300905A1 (en) | Semiconductor Device Including a Superjunction Structure with Drift Regions and Compensation Structures | |
US8866221B2 (en) | Super junction semiconductor device comprising a cell area and an edge area | |
JP5697665B2 (ja) | 半導体装置 | |
US20130248924A1 (en) | Semiconductor device | |
KR102502093B1 (ko) | 버퍼 영역을 갖는 반도체 디바이스 | |
US8273622B2 (en) | Semiconductor with a dynamic gate-drain capacitance | |
US20110101501A1 (en) | Semiconductor device including semiconductor zones and manufacturing method | |
CN106165101B (zh) | 半导体装置 | |
US9646836B2 (en) | Semiconductor device manufacturing method | |
JP2007335844A (ja) | 半導体装置 | |
US20140284715A1 (en) | Method of manufacturing semiconductor device | |
US20190259871A1 (en) | Semiconductor device | |
US8030706B2 (en) | Power semiconductor device | |
US20110169080A1 (en) | Charge balance power device and manufacturing method thereof | |
KR101403061B1 (ko) | 전력 반도체 디바이스 | |
WO2018154963A1 (ja) | 半導体装置 | |
CN110176497B (zh) | 碳化硅半导体器件和用于制造碳化硅半导体器件的方法 | |
KR102094769B1 (ko) | 다중 에피 성장법으로 구현된 p 쉴드 구조의 전력 반도체 및 그 제조 방법 | |
CN113424327A (zh) | 用于单极电荷平衡半导体功率器件的***和方法 | |
WO2022118976A1 (ja) | 超接合半導体装置 | |
US8975661B2 (en) | Asymmetrical bidirectional protection component |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110826 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110906 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111205 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111220 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120119 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4913717 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150127 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |