JP4904529B2 - 半導体素子のオーバーレイバーニアとその製造方法 - Google Patents
半導体素子のオーバーレイバーニアとその製造方法 Download PDFInfo
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- JP4904529B2 JP4904529B2 JP2007134907A JP2007134907A JP4904529B2 JP 4904529 B2 JP4904529 B2 JP 4904529B2 JP 2007134907 A JP2007134907 A JP 2007134907A JP 2007134907 A JP2007134907 A JP 2007134907A JP 4904529 B2 JP4904529 B2 JP 4904529B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24628—Nonplanar uniform thickness material
- Y10T428/24669—Aligned or parallel nonplanarities
- Y10T428/24694—Parallel corrugations
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
101 親バーニア
102 絶縁膜
103 子バーニアパッド
104 子バーニア
Claims (8)
- 半導体基板のスクライブ領域に内部空間を有し、枠部分が突出した四角枠状の親バーニアと、
前記親バーニアの前記内部空間に形成された前記親バーニアの上端部と同じ高さの子バーニアパッドと、
前記子バーニアパッド上に形成された子バーニアと、
を含むことを特徴とする半導体素子のオーバーレイバーニア。 - 前記子バーニアパッドは、前記親バーニアよりも小さく、前記子バーニアよりも大きいかまたは同一であることを特徴とする請求項1に記載の半導体素子のオーバーレイバーニア。
- 前記子バーニアパッドは、絶縁膜で形成されることを特徴とする請求項1に記載の半導体素子のオーバーレイバーニア。
- エッチング工程を進行し、半導体基板のスクライブ領域にトレンチを形成して内部空間を有し、枠部分が突出した四角枠状の親バーニアを形成する工程と、
前記親バーニアを含む全体構造上に絶縁膜を形成した後、平坦化工程を進行して前記親バーニアの上端部を露出させる工程と、
キーオープンマスクを用いたエッチング工程を実施して前記親バーニアの内部空間の一領域にのみ前記絶縁膜を残留させて子バーニアパッドを形成する工程と、
フォトレジストを塗布した後、露光及び現像工程を進行して前記子バーニアパッド上に子バーニアを形成する工程と、
を含むことを特徴とする半導体素子のオーバーレイバーニア製造方法。 - 前記絶縁膜は、酸化膜で形成することを特徴とする請求項4に記載の半導体素子のオーバーレイバーニア製造方法。
- 前記平坦化工程は、前記絶縁膜の上部の高さと前記親バーニアの上部の高さを同一にすることを特徴とする請求項4に記載の半導体素子のオーバーレイバーニア製造方法。
- 前記子バーニアパッドは、上記親バーニアより小さく、上記子バーニアよりも大きいかまたは同一であることを特徴とする請求項4に記載の半導体素子のオーバーレイバーニア製造方法。
- 前記露光工程は、I線(365nm)、KrF(248nm)、ArF(193nm)、及びEUV(157nm)のいずれか一つを用いて実施することを特徴とする請求項4に記載の半導体素子のオーバーレイバーニア製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060136154A KR100870316B1 (ko) | 2006-12-28 | 2006-12-28 | 반도체 소자의 오버레이 버니어 및 그 제조 방법 |
KR10-2006-0136154 | 2006-12-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008166681A JP2008166681A (ja) | 2008-07-17 |
JP4904529B2 true JP4904529B2 (ja) | 2012-03-28 |
Family
ID=39584381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007134907A Expired - Fee Related JP4904529B2 (ja) | 2006-12-28 | 2007-05-22 | 半導体素子のオーバーレイバーニアとその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7595258B2 (ja) |
JP (1) | JP4904529B2 (ja) |
KR (1) | KR100870316B1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100870316B1 (ko) * | 2006-12-28 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 오버레이 버니어 및 그 제조 방법 |
KR100985307B1 (ko) * | 2007-07-16 | 2010-10-04 | 주식회사 하이닉스반도체 | 포토 마스크 및 이를 이용한 반도체 소자의 오버레이버니어 형성 방법 |
US8338218B2 (en) | 2008-06-26 | 2012-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device module and manufacturing method of the photoelectric conversion device module |
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JP2687418B2 (ja) * | 1988-04-25 | 1997-12-08 | ソニー株式会社 | 半導体装置 |
JP2630484B2 (ja) * | 1990-05-15 | 1997-07-16 | 富士通株式会社 | 自動位置ずれ管理装置 |
JP2865089B2 (ja) * | 1996-12-26 | 1999-03-08 | 日本電気株式会社 | 重合せ精度測定用マーク及びその製造方法 |
KR19980065652A (ko) * | 1997-01-14 | 1998-10-15 | 김광호 | 반도체소자의 얼라인 키 형성방법 |
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JP3362717B2 (ja) * | 1999-11-24 | 2003-01-07 | 日本電気株式会社 | 半導体装置およびその製造方法 |
KR100318270B1 (ko) * | 1999-12-16 | 2001-12-24 | 박종섭 | 반도체 소자의 오버레이 버어니어 형성방법 |
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KR100870316B1 (ko) * | 2006-12-28 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 오버레이 버니어 및 그 제조 방법 |
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2006
- 2006-12-28 KR KR1020060136154A patent/KR100870316B1/ko not_active IP Right Cessation
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2007
- 2007-05-22 JP JP2007134907A patent/JP4904529B2/ja not_active Expired - Fee Related
- 2007-05-24 US US11/753,544 patent/US7595258B2/en active Active
Also Published As
Publication number | Publication date |
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US7595258B2 (en) | 2009-09-29 |
US20080160261A1 (en) | 2008-07-03 |
KR20080061163A (ko) | 2008-07-02 |
KR100870316B1 (ko) | 2008-11-25 |
JP2008166681A (ja) | 2008-07-17 |
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