JP4877626B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 101
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 claims description 79
- 230000001681 protective effect Effects 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 26
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 238000007789 sealing Methods 0.000 claims description 16
- 238000005520 cutting process Methods 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 27
- 229910052710 silicon Inorganic materials 0.000 description 27
- 239000010703 silicon Substances 0.000 description 27
- 239000010953 base metal Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 235000019353 potassium silicate Nutrition 0.000 description 2
- NTHWMYGWWRZVTN-UHFFFAOYSA-N sodium silicate Chemical compound [Na+].[Na+].[O-][Si]([O-])=O NTHWMYGWWRZVTN-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
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Description
次に、この半導体装置の製造方法の第1の例について説明する。まず、図2に示すように、ウエハ状態のシリコン基板1上に、接続パッド2、絶縁膜3、保護膜5、下地金属層7、配線8、柱状電極9および封止膜10が形成され、半田ボール11が形成されていないものを用意する。なお、図2において、符号21で示す領域はダイシングストリートに対応する領域である。
次に、図1に示す半導体装置の製造方法の第2の例について説明する。この場合、図5に示す工程後に、図11に示すように、スプレー(噴霧)式コーティング法により、溝23内におけるシリコン基板1、絶縁膜3、保護膜5、封止膜10の周側面および第1のダイシングフィルム22の上面とシリコン基板1の上面にエポキシ系樹脂等からなる保護膜12を比較的薄く形成し、溝23内に形成された保護膜12の幅方向中央部に溝25を形成する。
2 接続パッド
3 絶縁膜
5 保護膜
7 下地金属層
8 配線
9 柱状電極
10 封止膜
11 半田ボール
12 保護膜
21 ダイシングストリート
22 第1のダイシングフィルム
23 溝
24 第2のダイシングフィルム
25 溝
26 サポートフィルム
Claims (17)
- 表面側に外部接続用電極が設けられたウエハ状態の半導体基板の表面側をフィルムの上面に貼り付ける第一貼付工程と、
前記フィルムの上面に貼り付けられた前記ウエハ状態の半導体基板を切断して、各々、隣接のものと相互に間隔を有して分離された複数のチップサイズの半導体基板を得る第一切断工程と、
前記各半導体基板間に間隔を有する状態において前記各半導体基板の裏面および周側面に保護膜を形成する保護膜形成工程と、
前記保護膜によって前記各半導体基板が互いにつながった状態のまま、前記各半導体基板を前記フィルムの上面から剥離する剥離工程と、
を有し、
前記剥離工程の後に、前記保護膜によって前記各半導体基板が互いにつながった状態のまま、前記フィルムを剥離した前記各半導体基板の面に対してさらに加工を施し、その後、前記複数の半導体装置を個々に分離することを特徴とする半導体装置の製造方法。 - 請求項1に記載の発明において、前記保護膜形成工程の後に、前記保護膜によって前記各半導体基板同士が互いにつながった状態のまま、前記各半導体基板の裏面側に設けられた前記保護膜の裏面が覆われるように、前記各半導体基板を第二のフィルムの上面に貼り付ける第二貼付工程を、さらに有することを特徴とする半導体装置の製造方法。
- 請求項2に記載の発明において、前記第二貼付工程の後に、前記各半導体基板の前記外部接続用電極に接続するように半田ボールを形成する半田ボール形成工程を、さらに有することを特徴とする半導体装置の製造方法。
- 請求項2又は3に記載の発明において、前記剥離工程の後に、前記第二貼付工程を行うことを特徴とする半導体装置の製造方法。
- 請求項4に記載の発明において、
前記第一切断工程は、前記フィルムに第一の溝を形成することを含み、
前記保護膜形成工程は、前記保護膜を前記フィルムの前記第一の溝内に形成することを含むことを特徴とする半導体装置の製造方法。 - 請求項4又は5に記載の発明において、前記剥離工程の後に、前記半導体基板間において前記保護膜が前記外部接続用電極よりも突出して形成された部分を除去する除去工程を、さらに有することを特徴とする半導体装置の製造方法。
- 請求項4乃至6の何れか一項に記載の発明において、前記半田ボール形成工程は、前記保護膜によって前記各半導体基板が互いにつながった状態のまま、前記各半導体基板の前記外部接続用電極に接続するように前記半田ボールを形成することを含むことを特徴とする半導体装置の製造方法。
- 請求項4乃至7の何れか一項に記載の発明において、前記半田ボール形成工程の後に、前記保護膜を前記半導体基板間において切断する第二切断工程を、さらに有し、
当該第二切断工程の前には、半導体基板と該半導体基板の裏面及び周側面を覆う前記保護膜とをそれぞれが含む複数の半導体装置が前記保護膜によって互いにつながった状態であり、当該第二切断工程は、前記複数の半導体装置を個々に分離することを含むことを特徴とする半導体装置の製造方法。 - 請求項2又は3に記載の発明において、前記保護膜形成工程の後であって前記剥離工程の前に、前記第二貼付工程を行うことを特徴とする半導体装置の製造方法。
- 請求項9に記載の発明において、
前記第一切断工程は、前記フィルムに第一の溝を形成することを含み、
前記保護膜形成工程は、前記保護膜を前記フィルムの前記第一の溝内に形成することを含むことを特徴とする半導体装置の製造方法。 - 請求項9又は10に記載の発明において、前記半田ボール形成工程は、前記各半導体基板が前記第二のフィルムの上面に貼り付けられた状態のまま、前記各半導体基板の前記外部接続用電極に接続するように前記半田ボールを形成することを含むことを特徴とする半導体装置の製造方法。
- 請求項9乃至11の何れか一項に記載の発明において、前記剥離工程の後に、前記半導体基板間において前記保護膜が前記外部接続用電極よりも突出して形成された部分を除去する除去工程を、さらに有し、
当該除去工程の前には、半導体基板と該半導体基板の裏面及び周側面を覆う前記保護膜とをそれぞれが含む複数の半導体装置が前記保護膜によって互いにつながった状態であり、当該除去工程は、前記複数の半導体装置を個々に分離することを含むことを特徴とする半導体装置の製造方法。 - 請求項1乃至12の何れか一項に記載の発明において、前記保護膜は前記各半導体基板間全体に形成することを特徴とする半導体装置の製造方法。
- 請求項13に記載の発明において、前記保護膜を形成した後に、前記各半導体基板間に形成された前記保護膜をその幅方向中央部において切断する工程を有することを特徴とする半導体装置の製造方法。
- 請求項1乃至12の何れか一項に記載の発明において、前記保護膜は前記各半導体基板の周側面に形成される当該保護膜間に第二の溝が形成されるように形成することを特徴とする半導体装置の製造方法。
- 請求項1乃至14の何れか一項に記載の発明において、前記複数のチップサイズの半導体基板を得る工程は、前記ウエハ状態の半導体基板を切断した後、前記フィルムを拡張して前記各半導体基板間の間隔を広げる工程を有することを特徴とする半導体装置の製造方法。
- 請求項1乃至15の何れか一項に記載の発明において、前記外部接続用電極は柱状電極であり、該柱状電極の周囲に封止膜が設けられ、
前記第一切断工程は、前記封止膜を前記ウエハ状態の半導体基板と共に切断して分離することを含み、
前記保護膜形成工程は、前記保護膜を分離後の前記各封止膜を含む前記各半導体基板の周側面に形成することを含むことを特徴とする半導体装置の製造方法。
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