JP2007220869A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 230000001681 protective effect Effects 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 30
- 230000002093 peripheral effect Effects 0.000 claims abstract description 19
- 238000007789 sealing Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 64
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052710 silicon Inorganic materials 0.000 abstract description 30
- 239000010703 silicon Substances 0.000 abstract description 30
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000009719 polyimide resin Substances 0.000 abstract description 3
- 239000010953 base metal Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 235000019353 potassium silicate Nutrition 0.000 description 2
- NTHWMYGWWRZVTN-UHFFFAOYSA-N sodium silicate Chemical compound [Na+].[Na+].[O-][Si]([O-])=O NTHWMYGWWRZVTN-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
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Abstract
【解決手段】 まず、ウエハ状態のシリコン基板1の下側に設けられた封止膜10等をダイシングフィルム22の上面に貼り付けた状態において、ウエハ状態のシリコン基板1等を切断して各チップに分離する。この状態では、各チップ間に溝23が形成されている。そして、ダイシングフィルム22をその周囲方向に引っ張って拡張して溝23の間隔つまり各チップ間の間隔を広げた状態において、各シリコン基板1の上面(裏面)および周側面等にポリイミド系樹脂等からなる保護膜を同時に形成すると、別々に形成する場合と比較して、当該保護膜の形成工程数を少なくすることができる。
【選択図】 図4
Description
次に、この半導体装置の製造方法の第1の例について説明する。まず、図2に示すように、ウエハ状態のシリコン基板1上に、接続パッド2、絶縁膜3、保護膜5、下地金属層7、配線8、柱状電極9および封止膜10が形成され、半田ボール11が形成されていないものを用意する。なお、図2において、符号21で示す領域はダイシングストリートに対応する領域である。
次に、図1に示す半導体装置の製造方法の第2の例について説明する。この場合、図5に示す工程後に、図11に示すように、スプレー(噴霧)式コーティング法により、溝23内におけるシリコン基板1、絶縁膜3、保護膜5、封止膜10の周側面および第1のダイシングフィルム22の上面とシリコン基板1の上面にエポキシ系樹脂等からなる保護膜12を比較的薄く形成し、溝23内に形成された保護膜12の幅方向中央部に溝25を形成する。
2 接続パッド
3 絶縁膜
5 保護膜
7 下地金属層
8 配線
9 柱状電極
10 封止膜
11 半田ボール
12 保護膜
21 ダイシングストリート
22 第1のダイシングフィルム
23 溝
24 第2のダイシングフィルム
25 溝
26 サポートフィルム
Claims (7)
- 表面側に外部接続用電極が設けられたウエハ状態の半導体基板の表面側をフィルムの上面に貼り付ける工程と、
前記フィルムの上面に貼り付けられた前記ウエハ状態の半導体基板を切断して、各々、隣接のものと相互に間隔を有して分離された複数のチップサイズの半導体基板を得る工程と、
前記各半導体基板間に間隔を有する状態において前記各半導体基板の裏面および周側面に保護膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 請求項1に記載の発明において、前記複数のチップサイズの半導体基板を得る工程は、前記ウエハ状態の半導体基板を切断した後、前記フィルムを拡張して前記各半導体基板間の間隔を広げる工程を有することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記保護膜は前記各半導体基板間全体に形成することを特徴とする半導体装置の製造方法。
- 請求項3に記載の発明において、前記保護膜を形成した後に、前記各半導体基板間に形成された前記保護膜をその幅方向中央部において切断する工程を有することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記保護膜は前記各半導体基板の周側面に形成される当該保護膜間に溝が形成されるように形成することを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記外部接続用電極は柱状電極であり、該柱状電極の周囲に封止膜が設けられ、該封止膜は前記ウエハ状態の半導体基板と共に切断されて分離され、前記保護膜は分離後の前記各封止膜を含む前記各半導体基板の周側面に形成することを特徴とする半導体装置の製造方法。
- 請求項6に記載の発明において、前記保護膜を形成した後に、前記各半導体基板の柱状電極上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。
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JP2006039134A JP4877626B2 (ja) | 2006-02-16 | 2006-02-16 | 半導体装置の製造方法 |
US11/706,772 US7838394B2 (en) | 2006-02-16 | 2007-02-15 | Method of manufacturing semiconductor device |
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JP2006039134A JP4877626B2 (ja) | 2006-02-16 | 2006-02-16 | 半導体装置の製造方法 |
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JP4877626B2 JP4877626B2 (ja) | 2012-02-15 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009122911A1 (ja) * | 2008-03-31 | 2009-10-08 | 三洋電機株式会社 | 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2010062170A (ja) * | 2008-09-01 | 2010-03-18 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
US8642381B2 (en) | 2010-07-16 | 2014-02-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die |
US8895440B2 (en) | 2010-08-06 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV |
KR102389946B1 (ko) * | 2014-05-28 | 2022-05-10 | 주식회사 에이엔케이 | 입자 정렬을 이용한 코팅 방법 |
US10790160B2 (en) * | 2015-05-12 | 2020-09-29 | Smartrac Technology Gmbh | Barrier configurations and processes in layer structures |
US10121765B2 (en) * | 2017-03-01 | 2018-11-06 | Semiconductor Components Industries, Llc | Semiconductor device and method of forming WLCSP |
US20210407903A1 (en) * | 2020-06-26 | 2021-12-30 | Intel Corporation | High-throughput additively manufactured power delivery vias and traces |
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JP2000243774A (ja) * | 1999-02-24 | 2000-09-08 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2004165312A (ja) * | 2002-11-12 | 2004-06-10 | Sanyo Electric Co Ltd | 半導体集積装置及びその製造方法 |
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JP3455948B2 (ja) | 2000-05-19 | 2003-10-14 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP4115326B2 (ja) * | 2003-04-15 | 2008-07-09 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
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JPH02125633A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 集積回路 |
JP2000243774A (ja) * | 1999-02-24 | 2000-09-08 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2004165312A (ja) * | 2002-11-12 | 2004-06-10 | Sanyo Electric Co Ltd | 半導体集積装置及びその製造方法 |
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WO2009122911A1 (ja) * | 2008-03-31 | 2009-10-08 | 三洋電機株式会社 | 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器 |
JP2009246174A (ja) * | 2008-03-31 | 2009-10-22 | Sanyo Electric Co Ltd | 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器 |
US8476776B2 (en) | 2008-03-31 | 2013-07-02 | Sanyo Electric Co., Ltd. | Semiconductor module, method for fabricating the semiconductor module, and mobile apparatus |
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US7838394B2 (en) | 2010-11-23 |
US20070190689A1 (en) | 2007-08-16 |
JP4877626B2 (ja) | 2012-02-15 |
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