JP4817342B2 - Soiタイプのウェハの製造方法 - Google Patents
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- JP4817342B2 JP4817342B2 JP2009546830A JP2009546830A JP4817342B2 JP 4817342 B2 JP4817342 B2 JP 4817342B2 JP 2009546830 A JP2009546830 A JP 2009546830A JP 2009546830 A JP2009546830 A JP 2009546830A JP 4817342 B2 JP4817342 B2 JP 4817342B2
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 235000012431 wafers Nutrition 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000012212 insulator Substances 0.000 claims abstract description 10
- 230000007547 defect Effects 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000002131 composite material Substances 0.000 description 19
- 239000013078 crystal Substances 0.000 description 18
- 238000010438 heat treatment Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 206010040844 Skin exfoliation Diseases 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 239000002244 precipitate Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- 229910052734 helium Inorganic materials 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004064 recycling Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- -1 hydrogen or helium Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/8305—Miscellaneous [e.g., treated surfaces, etc.]
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Description
Claims (6)
- シリコン・オン・インシュレータ(SOI)タイプのウェハの製造方法であって、
a)シリコンの初期ドナー基板(1)を用意するステップと、
b)前記初期ドナー基板(1)上に二酸化シリコンの絶縁層(3)を形成するステップと、
c)前記初期ドナー基板(1)に所定の分割エリアを形成するステップと、
d)前記初期ドナー基板をハンドル基板(9)に貼り付けるステップと、
e)前記所定の分割エリア(7)で前記ドナー基板(1)を剥離することで、前記初期ドナー基板(1)の層(13)を被転写層として前記ハンドル基板(9)上に転写して、SOIウェハを形成するステップと、
を備え、
当該製造方法が、少なくとも3回繰り返され、
前記初期ドナー基板(1)の残部(15)が、後続する製造ランにおいて初期ドナー基板(1)として再利用される、方法において、
前記絶縁層(3)が、900℃未満の温度で実行される熱酸化処理によって形成され、
前記絶縁層(3)の厚さが、少なくとも1000Åであることを特徴とするSOIタイプのウェハの製造方法。 - 前記被転写層(13)の厚さが、1000Å以下である、請求項1に記載のSOIタイプのウェハの製造方法。
- 前記被転写層を研磨およびアニールするステップをさらに備え、このステップの後に、前記被転写層が、エピタキシャル堆積により、6000Åの層の厚さを達成するように、さらに厚層化される、請求項1または2に記載のSOIタイプのウェハの製造方法。
- 第1の製造ランの前の新しい初期ドナー基板(1)の格子間酸素濃度が、25ppma(old ASTM)未満である、請求項1〜3のいずれか一項に記載のSOIタイプのウェハの製造方法。
- 前記初期ドナー基板(1)、および、後続する残部(15)を用いた各製造ランにおいて、前記被転写層のHF欠陥密度が、0.1欠陥/cm2未満であるように前記熱酸化処理が実行される、請求項1〜4のいずれか一項に記載のSOIタイプのウェハの製造方法。
- 製造ランごとに、前記絶縁層(3)がより高い温度で形成される、請求項1〜5のいずれか一項に記載のSOIタイプのウェハの製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07290094.7 | 2007-01-24 | ||
EP20070290094 EP1950803B1 (en) | 2007-01-24 | 2007-01-24 | Method for manufacturing silicon on Insulator wafers and corresponding wafer |
PCT/IB2008/000131 WO2008090439A1 (en) | 2007-01-24 | 2008-01-16 | Method for manufacturing compound material wafers and corresponding compound material wafer |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010517286A JP2010517286A (ja) | 2010-05-20 |
JP2010517286A5 JP2010517286A5 (ja) | 2011-02-03 |
JP4817342B2 true JP4817342B2 (ja) | 2011-11-16 |
Family
ID=38157805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009546830A Active JP4817342B2 (ja) | 2007-01-24 | 2008-01-16 | Soiタイプのウェハの製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7736994B2 (ja) |
EP (2) | EP1950803B1 (ja) |
JP (1) | JP4817342B2 (ja) |
KR (1) | KR101302426B1 (ja) |
CN (1) | CN101558487B (ja) |
AT (1) | ATE518241T1 (ja) |
WO (1) | WO2008090439A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5438986B2 (ja) | 2008-02-19 | 2014-03-12 | 株式会社半導体エネルギー研究所 | 光電変換装置の製造方法 |
WO2011072153A2 (en) | 2009-12-09 | 2011-06-16 | Solexel, Inc. | High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods using three-dimensional semiconductor absorbers |
WO2013055307A2 (en) | 2010-08-05 | 2013-04-18 | Solexel, Inc. | Backplane reinforcement and interconnects for solar cells |
FR2987166B1 (fr) | 2012-02-16 | 2017-05-12 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
JP2015516672A (ja) | 2012-02-26 | 2015-06-11 | ソレクセル、インコーポレイテッド | レーザ分割及び装置層移設のためのシステム及び方法 |
FR2999801B1 (fr) | 2012-12-14 | 2014-12-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure |
US8946054B2 (en) | 2013-04-19 | 2015-02-03 | International Business Machines Corporation | Crack control for substrate separation |
FR3076069B1 (fr) * | 2017-12-22 | 2021-11-26 | Commissariat Energie Atomique | Procede de transfert d'une couche utile |
FR3076070B1 (fr) * | 2017-12-22 | 2019-12-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile |
DE102018221582A1 (de) | 2018-12-13 | 2020-06-18 | Siltronic Ag | Verfahren zur Herstellung einer Halbleiterscheibe und Halbleiterscheibe |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US5953622A (en) * | 1996-11-23 | 1999-09-14 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating semiconductor wafers |
JP2000030995A (ja) * | 1998-07-07 | 2000-01-28 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
WO2000055397A1 (fr) * | 1999-03-16 | 2000-09-21 | Shin-Etsu Handotai Co., Ltd. | Procede de production d'une tranche de silicium et tranche de silicium ainsi obtenue |
JP2003068744A (ja) * | 2001-08-30 | 2003-03-07 | Shin Etsu Handotai Co Ltd | シリコンウエーハの製造方法及びシリコンウエーハ並びにsoiウエーハ |
US20040185638A1 (en) * | 2003-02-14 | 2004-09-23 | Canon Kabushiki Kaisha | Substrate manufacturing method |
US20050026394A1 (en) * | 2000-11-27 | 2005-02-03 | S.O.I.Tec Silicon On Insulator Technologies S.A., | Methods for fabricating a substrate |
EP1513193A1 (en) * | 2003-02-14 | 2005-03-09 | Sumitomo Mitsubishi Silicon Corporation | Method for manufacturing silicon wafer |
WO2005022610A1 (ja) * | 2003-09-01 | 2005-03-10 | Sumco Corporation | 貼り合わせウェーハの製造方法 |
EP1659623A1 (en) * | 2004-11-19 | 2006-05-24 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Method for fabricating a germanium on insulator (GeOI) type wafer |
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JPH11307747A (ja) | 1998-04-17 | 1999-11-05 | Nec Corp | Soi基板およびその製造方法 |
JP3500063B2 (ja) * | 1998-04-23 | 2004-02-23 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
JP4476390B2 (ja) * | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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FR2855909B1 (fr) | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
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FR2881573B1 (fr) * | 2005-01-31 | 2008-07-11 | Soitec Silicon On Insulator | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
US20070117350A1 (en) * | 2005-08-03 | 2007-05-24 | Memc Electronic Materials, Inc. | Strained silicon on insulator (ssoi) with layer transfer from oxidized donor |
-
2007
- 2007-01-24 EP EP20070290094 patent/EP1950803B1/en active Active
- 2007-01-24 EP EP20100290492 patent/EP2264755A3/en not_active Withdrawn
- 2007-01-24 AT AT07290094T patent/ATE518241T1/de not_active IP Right Cessation
- 2007-09-05 US US11/850,481 patent/US7736994B2/en active Active
-
2008
- 2008-01-16 JP JP2009546830A patent/JP4817342B2/ja active Active
- 2008-01-16 WO PCT/IB2008/000131 patent/WO2008090439A1/en active Application Filing
- 2008-01-16 KR KR1020097011182A patent/KR101302426B1/ko active IP Right Grant
- 2008-01-16 CN CN2008800011140A patent/CN101558487B/zh active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5953622A (en) * | 1996-11-23 | 1999-09-14 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating semiconductor wafers |
JP2000030995A (ja) * | 1998-07-07 | 2000-01-28 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
WO2000055397A1 (fr) * | 1999-03-16 | 2000-09-21 | Shin-Etsu Handotai Co., Ltd. | Procede de production d'une tranche de silicium et tranche de silicium ainsi obtenue |
US20050026394A1 (en) * | 2000-11-27 | 2005-02-03 | S.O.I.Tec Silicon On Insulator Technologies S.A., | Methods for fabricating a substrate |
JP2003068744A (ja) * | 2001-08-30 | 2003-03-07 | Shin Etsu Handotai Co Ltd | シリコンウエーハの製造方法及びシリコンウエーハ並びにsoiウエーハ |
US20040185638A1 (en) * | 2003-02-14 | 2004-09-23 | Canon Kabushiki Kaisha | Substrate manufacturing method |
EP1513193A1 (en) * | 2003-02-14 | 2005-03-09 | Sumitomo Mitsubishi Silicon Corporation | Method for manufacturing silicon wafer |
WO2005022610A1 (ja) * | 2003-09-01 | 2005-03-10 | Sumco Corporation | 貼り合わせウェーハの製造方法 |
EP1659623A1 (en) * | 2004-11-19 | 2006-05-24 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Method for fabricating a germanium on insulator (GeOI) type wafer |
Also Published As
Publication number | Publication date |
---|---|
EP2264755A3 (en) | 2011-11-23 |
ATE518241T1 (de) | 2011-08-15 |
US20080176380A1 (en) | 2008-07-24 |
EP1950803B1 (en) | 2011-07-27 |
EP1950803A1 (en) | 2008-07-30 |
KR101302426B1 (ko) | 2013-09-10 |
CN101558487A (zh) | 2009-10-14 |
US7736994B2 (en) | 2010-06-15 |
JP2010517286A (ja) | 2010-05-20 |
WO2008090439A1 (en) | 2008-07-31 |
CN101558487B (zh) | 2012-05-30 |
KR20090108689A (ko) | 2009-10-16 |
EP2264755A2 (en) | 2010-12-22 |
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