JP4758787B2 - 半導体集積回路 - Google Patents
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- 230000015556 catabolic process Effects 0.000 description 36
- 230000001172 regenerating effect Effects 0.000 description 29
- 230000010354 integration Effects 0.000 description 17
- 230000008929 regeneration Effects 0.000 description 13
- 238000011069 regeneration method Methods 0.000 description 13
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Description
図5は、本発明の第1の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図1に示したMOSドライバ45を含む出力回路25aを備えた多チャンネル半導体集積回路を例にして説明する。
図8は、本発明の第2の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図2に示したIGBTドライバ46を含む出力回路25bを備えた多チャンネル半導体集積回路を例にして説明する。
図11は、本発明の第3の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図3に示したハイサイドレスMOSドライバ47を含む出力回路25cを備えた多チャンネル半導体集積回路を例にして説明する。
図14は、本発明の第4の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図4に示したハイサイドレスIGBTドライバ48を含む出力回路25dを備えた多チャンネル半導体集積回路を例にして説明する。
図17は、本発明の第5の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図1に示したMOSドライバ45を含む出力回路25aを備えた多チャンネル半導体集積回路を例にして説明する。
図19は、本発明の第5の実施形態に係る半導体集積回路の変形例のレイアウトを示す平面図である。
図20は、本発明の第6の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図2に示したIGBTドライバ46を含む出力回路25bを備えた多チャンネル半導体集積回路を例にして説明する。
図22は、本発明の第6の実施形態に係る半導体集積回路の変形例のレイアウトを示す平面図である。
図23は、本発明の第7の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図3に示したハイサイドレスMOSドライバ47を含む出力回路25cを備えた多チャンネル半導体集積回路を例にして説明する。
図25は、本発明の第7の実施形態に係る半導体集積回路の変形例のレイアウトを示す平面図である。
図26は、本発明の第8の実施形態における多チャンネル半導体集積回路のレイアウトを示す平面図であって、具体的には、上述した図4に示したハイサイドレスIGBTドライバ48を含む出力回路25dを備えた多チャンネル半導体集積回路を例にして説明する。
図28は、本発明の第8の実施形態に係る半導体集積回路の変形例のレイアウトを示す平面図である。
2、2b 高圧電位の配線
3a、3aA、3aB、3aC、3aD、3b 基準電位の配線
4 高圧電源のパッド
5 基準電位のパッド
6 低耐圧制御部
7 バス配線
8 パッド
9 入力制御パッド
10 ハイサイドトランジスタ
11 ローサイドトランジスタ
12 レベルシフト回路
13 プリドライバ
14 2層配線
15 1層配線
16A〜16D 出力回路セル
17 インナーリード
18 ボンディングワイヤ
19 ハイサイドトランジスタのドレイン領域
20 ハイサイドトランジスタのソース領域
21 スルーホール
22 ローサイドトランジスタのドレイン領域
23 ローサイドトランジスタのソース領域
24 入力端子
25a〜25d 出力回路
26 バックゲート−ドレイン間寄生ダイオード
27 バックゲート−ドレイン間寄生ダイオード
28 ハイサイドトランジスタ
29 ローサイドトランジスタ
30 ハイサイド回生ダイオード
31 ローサイド回生ダイオード
32 ゲート保護用ダイオード
33 ゲートオフ用抵抗
34 ゲート保護回路
35 ハイサイドトランジスタのエミッタ領域
36 ハイサイドトランジスタのコレクタ領域
37 ローサイドトランジスタのエミッタ領域
38 ローサイドトランジスタのコレクタ領域
39 ダイオードのカソード領域
40 ダイオードのアノード領域
41 コンタクト
43 ESD保護素子
44 プリドライバ
45 MOSドライバ
46 IGBTドライバ
47 ハイサイドレスMOSドライバ
48 ハイサイドレスIGBTドライバ
Claims (15)
- 半導体チップ上に、前記半導体チップにおける第1のチップ辺に沿うように形成され、各々がパッドを有する複数の回路セルを備えた半導体集積回路であって、
前記複数の回路セルのうち、前記第1のチップ辺における少なくとも端部近傍に位置する一以上の回路セルは、前記第1のチップ辺における中央部から端部へ近付くにつれて前記第1のチップ辺から離れる方向へ階段状にずれるように配置され、前記パッドが階段状にずれることを特徴とする半導体集積回路。 - 前記複数の回路セルの各々が、前記第1のチップ辺における中央部から端部へ近付くにつれて前記第1のチップ辺から離れる方向へ階段状にずれるように配置されていることを特徴とする請求項1に記載の半導体集積回路。
- 前記回路セルは、
高耐圧ドライバと、
前記高耐圧ドライバを駆動するプリドライバと、
前記パッドとを備えていることを特徴とする請求項1に記載の半導体集積回路。 - 前記高耐圧ドライバは、
ハイサイドトランジスタとローサイドトランジスタと前記ハイサイドトランジスタを駆動するレベルシフト回路とを備えていることを特徴とする請求項3に記載の半導体集積回路。 - 前記プリドライバ、前記パッド、前記ハイサイドトランジスタ、前記レベルシフト回路、及び、前記ローサイドトランジスタは、一直線上に配置されていることを特徴とする請求項4に記載の半導体集積回路。
- 少なくとも前記ハイサイドトランジスタと前記ローサイドトランジスタとは、前記パッドを介して対向するように配置されていることを特徴とする請求項5に記載の半導体集積回路。
- 前記半導体チップの中央部に配置された制御部と、
前記半導体チップにおける前記第1のチップ辺に対向する第2のチップ辺に沿うように配置され、前記複数の回路セルよりなる第1の回路セル列に前記制御部を介して対向する複数の前記の回路セルよりなる第2の回路セル列とをさらに備えていることを特徴とする請求項6に記載の半導体集積回路。 - 前記第1の回路セル列及び前記第2の回路セル列の各々の両端に配置され、高圧電位用の第1の電源パッド及び基準電位用の第2の電源パッドと、
前記第1の回路セル列及び前記第2の回路セル列における各々の前記ハイサイドトランジスタの上に配置され、前記第1の電源パッドと電気的に接続する高圧電位の第1の配線と、
前記第1の回路セル列及び前記第2の回路セル列における各々の前記ローサイドトランジスタの上に配置され、前記第2の電源パッドと電気的に接続する基準電位の第2の配線とをさらに備えていることを特徴とする請求項7に記載の半導体集積回路。 - 前記レベルシフト回路及び前記プリドライバは、前記ローサイドトランジスタのセル幅内に収まるように設計されていることを特徴とする請求項4に記載の半導体集積回路。
- 前記高耐圧ドライバは、
ESD保護素子と、
ローサイドトランジスタとを備えていることを特徴とする請求項3に記載の半導体集積回路。 - 前記プリドライバ、前記パッド、前記ESD保護素子、及び、前記ローサイドトランジスタは、一直線上に配置されていることを特徴とする請求項10に記載の半導体集積回路。
- 少なくとも前記ESD保護素子と前記ローサイドトランジスタとは、前記パッドを介して対向するように配置されていることを特徴とする請求項11に記載の半導体集積回路。
- 前記半導体チップの中央部に配置された制御部と、
前記半導体チップにおける前記第1のチップ辺に対向する第2のチップ辺に沿うように配置され、前記複数の回路セルよりなる第1の回路セル列に前記制御部を介して対向する複数の前記の回路セルよりなる第2の回路セル列とをさらに備えていることを特徴とする請求項12に記載の半導体集積回路。 - 前記第1の回路セル列及び前記第2の回路セル列の各々の両端に配置され、高圧電位用の第1の電源パッド及び基準電位用の第2の電源パッドと、
前記第1の回路セル列及び前記第2の回路セル列における各々の前記ESD保護素子の上に配置され、前記第1の電源パッドと電気的に接続する高圧電位の第1の配線と、
前記第1の回路セル列及び前記第2の回路セル列における各々の前記ローサイドトランジスタの上に配置され、前記第2の電源パッドと電気的に接続する基準電位の第2の配線とをさらに備えていることを特徴とする請求項13に記載の半導体集積回路。 - 前記プリドライバは、前記ローサイドトランジスタのセル幅内に収まるように設計されていることを特徴とする請求項10に記載の半導体集積回路。
Priority Applications (5)
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JP2006056575A JP4758787B2 (ja) | 2006-03-02 | 2006-03-02 | 半導体集積回路 |
KR1020087011921A KR20080107350A (ko) | 2006-03-02 | 2006-09-29 | 반도체 집적회로 |
US12/094,494 US7989964B2 (en) | 2006-03-02 | 2006-09-29 | Semiconductor integrated circuit |
CN2006800360566A CN101278389B (zh) | 2006-03-02 | 2006-09-29 | 半导体集成电路 |
PCT/JP2006/319535 WO2007099664A1 (ja) | 2006-03-02 | 2006-09-29 | 半導体集積回路 |
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JP2006056575A JP4758787B2 (ja) | 2006-03-02 | 2006-03-02 | 半導体集積回路 |
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JP4758787B2 true JP4758787B2 (ja) | 2011-08-31 |
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US (1) | US7989964B2 (ja) |
JP (1) | JP4758787B2 (ja) |
KR (1) | KR20080107350A (ja) |
CN (1) | CN101278389B (ja) |
WO (1) | WO2007099664A1 (ja) |
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US8169088B2 (en) * | 2009-07-02 | 2012-05-01 | Monolithic Power Systems, Inc. | Power converter integrated circuit floor plan and package |
JP6584977B2 (ja) * | 2016-02-24 | 2019-10-02 | 日立オートモティブシステムズ株式会社 | 半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6046041A (ja) | 1983-08-24 | 1985-03-12 | Nec Corp | 半導体装置 |
JPS6265449A (ja) | 1985-09-18 | 1987-03-24 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPS62185331A (ja) | 1986-02-10 | 1987-08-13 | Sumitomo Electric Ind Ltd | 半導体装置 |
JPH03163817A (ja) * | 1989-11-21 | 1991-07-15 | Mitsubishi Electric Corp | 大規模半導体集積回路チップ |
JPH0645511A (ja) * | 1992-07-23 | 1994-02-18 | Matsushita Electric Ind Co Ltd | Igbtモジュール |
JP2001308141A (ja) * | 2000-02-18 | 2001-11-02 | Sony Corp | 電子回路装置の製造方法 |
US7276802B2 (en) * | 2002-04-15 | 2007-10-02 | Micron Technology, Inc. | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
KR100476925B1 (ko) * | 2002-06-26 | 2005-03-17 | 삼성전자주식회사 | 본딩 불량과 신호 스큐를 방지하는 패드 배치를 갖는 반도체 칩 |
KR100492801B1 (ko) * | 2002-11-14 | 2005-06-07 | 주식회사 하이닉스반도체 | 리셋신호 발생회로 및 이를 이용한 불휘발성 강유전체메모리 장치 |
US6919603B2 (en) * | 2003-04-30 | 2005-07-19 | Texas Instruments Incorporated | Efficient protection structure for reverse pin-to-pin electrostatic discharge |
JP4091038B2 (ja) * | 2003-11-19 | 2008-05-28 | 松下電器産業株式会社 | プラズマディスプレイのサステインドライバ、及びその制御回路 |
US7321242B2 (en) * | 2004-04-15 | 2008-01-22 | California Institute Of Technology | Integrated circuit with breakdown voltage multiplier |
JP4778811B2 (ja) * | 2006-03-02 | 2011-09-21 | パナソニック株式会社 | 半導体集積回路 |
-
2006
- 2006-03-02 JP JP2006056575A patent/JP4758787B2/ja not_active Expired - Fee Related
- 2006-09-29 KR KR1020087011921A patent/KR20080107350A/ko not_active Application Discontinuation
- 2006-09-29 US US12/094,494 patent/US7989964B2/en not_active Expired - Fee Related
- 2006-09-29 WO PCT/JP2006/319535 patent/WO2007099664A1/ja active Application Filing
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CN101278389A (zh) | 2008-10-01 |
JP2007234973A (ja) | 2007-09-13 |
KR20080107350A (ko) | 2008-12-10 |
US7989964B2 (en) | 2011-08-02 |
WO2007099664A1 (ja) | 2007-09-07 |
CN101278389B (zh) | 2013-01-09 |
US20090273099A1 (en) | 2009-11-05 |
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