JP4703680B2 - Method for manufacturing embedded printed circuit board - Google Patents

Method for manufacturing embedded printed circuit board Download PDF

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JP4703680B2
JP4703680B2 JP2008103101A JP2008103101A JP4703680B2 JP 4703680 B2 JP4703680 B2 JP 4703680B2 JP 2008103101 A JP2008103101 A JP 2008103101A JP 2008103101 A JP2008103101 A JP 2008103101A JP 4703680 B2 JP4703680 B2 JP 4703680B2
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layer
copper
plating
pattern
forming
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JP2009158905A (en
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ホン ヒュン キム
ジョン チョル キム
ジョン サン クウォン
ジ サン キム
ジュン ギ パク
チョル ホン リム
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コリア サーキット カンパニー リミテッド
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

本発明は、導電性パターンの密着力を向上させ、外部環境から導電性パターンを保護することができ、印刷回路基板の信頼性を向上させることができる埋込型印刷回路基板の製造方法に関する。   The present invention relates to a method for manufacturing an embedded printed circuit board that can improve the adhesion of a conductive pattern, protect the conductive pattern from the external environment, and improve the reliability of the printed circuit board.

電子産業の発達に伴い、電子部品の高機能化、小型化の要求が急増している。このような趨勢に対応するために、印刷回路基板も回路の高密度化が要求されている実情があり、これにより、多様な微細回路の具現工法が使われている。   With the development of the electronic industry, demands for higher functionality and miniaturization of electronic components are increasing rapidly. In order to cope with such a trend, there is a situation where printed circuit boards are required to have higher circuit density, and accordingly, various fine circuit implementation methods are used.

最も顕著な増加傾向を持った電子産業は、携帯電話であり、面積や厚さを低減する趨勢に変化しており、使用される電子部品もこのような趨勢を踏まえるために、面積を減らす方向に変化した。特に、集積回路(Integrated circuit;IC)のインターポーザー(Interposer)として使用される基板であるＣＳＰ(Chip sale package)が携帯電話に採用される数が多くなり始め、現在は、殆どのパッケージがＣＳＰ基板を使用しており、次第に基板の密度増加が要求されている。   The electronics industry, which has the most notable increase, is the mobile phone, and the trend is to reduce the area and thickness, and the electronic components used are also in the direction of reducing the area to take this trend into account. Changed. In particular, CSP (Chip sale package), which is a substrate used as an interposer of an integrated circuit (IC), has begun to be used in mobile phones, and most packages are now CSP. A substrate is used, and an increase in the density of the substrate is gradually required.

図１１は、従来技術に係る印刷回路基板を示した斜視図である。図１１に示すように、層間電気的信号を連結するために加工されるビアーホールの周囲に露光や現状工程で発生する加工誤差のために、上部ランドが存在することになる。図１１を参照すると、ビアーホールの大きさに露光及び現状の誤差を加えた大きさだけランドが存在する。ランドの大きさを減らすためには、高精細の露光設備が使用できるが、設備を使用するとしても、ランドを無くすことはできない状態である。   FIG. 11 is a perspective view illustrating a printed circuit board according to the related art. As shown in FIG. 11, an upper land is present around a via hole that is processed to connect interlayer electrical signals due to exposure and processing errors that occur in the current process. Referring to FIG. 11, there is a land having a size equal to the size of the via hole plus the exposure and current errors. In order to reduce the size of the land, a high-definition exposure facility can be used, but even if the facility is used, the land cannot be eliminated.

一方、従来の回路パターンは、サブトラクティブ(subtractive)方法で具現できるが、サブトラクティブ方法は、基板全体にメッキを施した後、イメージング(Imaging)過程などを通して選択的にパターンを形成する方法である。このようなサブトラクティブ方法は、パターンの形成に制約が多く、パターンを外部環境から保護してくれるＰＳＲ層部分にクラックなどが頻繁に発生して、不良率が増加し、印刷回路基板の信頼性に問題が多い。   Meanwhile, the conventional circuit pattern can be implemented by a subtractive method, and the subtractive method is a method of selectively forming a pattern through an imaging process after plating the entire substrate. . Such a subtractive method has many restrictions on pattern formation, and cracks frequently occur in the PSR layer portion that protects the pattern from the external environment, increasing the defect rate and improving the reliability of the printed circuit board. There are many problems.

本発明の目的は、微細回路パターンの形成が可能であり、導電性パターンの密着力を向上させ、外部環境から導電性パターンを保護することができ、印刷回路基板の信頼性を向上させることができる埋込型印刷回路基板の製造方法を提供することにある。   It is an object of the present invention to form a fine circuit pattern, improve the adhesion of the conductive pattern, protect the conductive pattern from the external environment, and improve the reliability of the printed circuit board. An object of the present invention is to provide a method for manufacturing an embedded printed circuit board.

本発明は、上記した問題点を解決するために案出されたものであって、(a)絶縁基板に銅層と絶縁層とを順次蒸着して銅積層板を形成する銅積層板の形成段階と;(b)前記絶縁層にパターンとビアーホールとを形成するパターニング段階と;(c)前記銅積層板の表面を無電解メッキして前記銅積層板の表面に第１のメッキ層を形成する第１のメッキ層の形成段階と;(d)前記パターン及び前記ビアーホールを除いた前記第１のメッキ層の表面にメッキレジスト層を形成するメッキレジスト層の形成段階と;(e)前記銅積層板を電解メッキして、前記パターンと前記ビアーホールとに第２のメッキ層を形成する第２のメッキ層の形成段階と;(f)前記メッキレジスト層を剥離するメッキレジスト層の剥離段階と;(g)前記銅積層板をエッチングして前記第１のメッキ層を除去するエッチング段階と;(h)前記銅積層板の表面にＰＳＲ(Photo solder resist)層を形成するＰＳＲ層の形成段階と、を含む埋込型印刷回路基板の製造方法を提供する。   The present invention has been devised to solve the above-described problems, and (a) formation of a copper laminate by forming a copper laminate by sequentially depositing a copper layer and an insulating layer on an insulating substrate. And (b) a patterning step of forming a pattern and a via hole in the insulating layer; and (c) electrolessly plating the surface of the copper laminate and providing a first plating layer on the surface of the copper laminate. Forming a first plating layer to be formed; (d) forming a plating resist layer on the surface of the first plating layer excluding the pattern and the via hole; and (e) Forming a second plating layer by electroplating the copper laminate and forming a second plating layer on the pattern and the via hole; and (f) a plating resist layer for peeling the plating resist layer; A peeling step; and (g) etching the copper laminate to form the first plating layer And etching removing; (h) to provide a method for manufacturing a buried printed circuit board comprising, a step of forming PSR layer forming a PSR (Photo solder resist) layer on the surface of the copper laminate.

上記において、前記(b)段階において、前記パターンと前記ビアーホールとは、レーザーにより形成することが望ましい。   In the above, in the step (b), the pattern and the via hole are preferably formed by a laser.

上記において、前記(c)段階において、前記銅積層板の表面を無電解銅メッキして、前記銅積層板の表面に第１の銅メッキ層を形成することが望ましい。   In the above, preferably, in the step (c), the surface of the copper laminate is electrolessly copper plated to form a first copper plating layer on the surface of the copper laminate.

上記において、前記(e)段階において、前記パターンと前記ビアーホールとの内部に前記第２のメッキ層が充填されるようにすることが望ましい。   In the above, it is preferable that the second plating layer is filled in the pattern and the via hole in the step (e).

上記において、前記(e)段階において、前記銅積層板を電解銅メッキして、前記パターンと前記ビアーホールとに第２の銅メッキ層を形成することが望ましい。   In the above, in the step (e), it is preferable that the copper laminated plate is subjected to electrolytic copper plating to form a second copper plating layer on the pattern and the via hole.

上記において、前記(g)段階と前記(h)段階との間に、前記銅積層板の表面が平坦化するように、前記銅積層板の表面を研磨する研磨段階を更に含むことが望ましい。   In the above, it is preferable that a polishing step of polishing the surface of the copper laminate is further included between the step (g) and the step (h) so that the surface of the copper laminate is flattened.

本発明の埋込型印刷回路基板の製造方法によれば、次のような効果がある。   The method for manufacturing an embedded printed circuit board according to the present invention has the following effects.

導電性パターンを絶縁層の内部で形成することで、導電性パターンの密着力を向上させ、外部環境から導電性パターンを保護することができ、印刷回路基板の信頼性を向上させることができる。   By forming the conductive pattern inside the insulating layer, it is possible to improve the adhesion of the conductive pattern, protect the conductive pattern from the external environment, and improve the reliability of the printed circuit board.

また、銅積層板の表面が均一な状態でＰＳＲ層を形成することで、クラック(Crack)が予防できる。   In addition, cracks can be prevented by forming the PSR layer with the surface of the copper laminate being uniform.

更に、微細パターンの形成が可能である。   Furthermore, a fine pattern can be formed.

以下、添付の図面を参照しながら、本発明に係る望ましい実施形態を詳細に説明することにする。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図１を参照して説明すると、本実施形態の埋込型印刷回路基板の製造方法は、次のような段階からなる。   Referring to FIG. 1, the method for manufacturing an embedded printed circuit board according to this embodiment includes the following steps.

まず、図２に示すように、絶縁基板１０の所定の箇所に複数個設けられた単層の銅層２０を蒸着し、次に絶縁基板１０及び銅層２０の上に絶縁層３０を蒸着して銅積層板１００を形成する(銅積層板の形成段階、a段階)。
First, as shown in FIG. 2, by depositing a copper layer 20 of the plurality provided monolayer at a predetermined point insulation substrate 10, then depositing an insulating layer 30 on the insulating substrate 10 and the copper layer 20 Thus, the copper laminate 100 is formed (formation step of copper laminate, step a).

次に、図３に示すように、絶縁層３０にパターン３１とビアーホール３５とを各々形成する(パターニング段階、b段階)。   Next, as shown in FIG. 3, a pattern 31 and a via hole 35 are respectively formed in the insulating layer 30 (patterning step, b step).

この段階において、パターン３１とビアーホール３５とは、レーザー(Laser)により形成することが望ましい。   At this stage, the pattern 31 and the via hole 35 are preferably formed by a laser.

次に、図４に示すように、銅積層板１００の表面を無電解メッキして、銅積層板１００の表面に第１のメッキ層４０を形成する(第１のメッキ層の形成段階、c段階)。   Next, as shown in FIG. 4, the surface of the copper laminate 100 is electrolessly plated to form a first plating layer 40 on the surface of the copper laminate 100 (the first plating layer forming step, c Stage).

この段階において、銅積層板１００の表面を無電解銅メッキして、銅積層板１００の表面に第１の銅メッキ層４０を形成することが望ましい。   At this stage, it is desirable to form the first copper plating layer 40 on the surface of the copper laminate 100 by electroless copper plating the surface of the copper laminate 100.

次に、図５に示すように、選択的にパターン３１及びビアーホール３５を除いた第１のメッキ層４０の表面のみにメッキレジスト層５０を形成する(メッキレジスト層の形成段階、d段階)。   Next, as shown in FIG. 5, a plating resist layer 50 is selectively formed only on the surface of the first plating layer 40 excluding the pattern 31 and the via hole 35 (plating resist layer formation stage, d stage). .

次に、図６aに示すように、銅積層板１００を電解メッキして、パターン３１とビアーホール３５とに第２のメッキ層６０を形成する(第２のメッキ層の形成段階、e段階)。   Next, as shown in FIG. 6a, the copper laminate 100 is electrolytically plated to form a second plating layer 60 on the pattern 31 and the via hole 35 (second plating layer formation stage, e stage). .

この段階において、銅積層板１００を電解銅メッキして、パターン３１とビアーホール３５とに第２の銅メッキ層６０を形成することが望ましい。   At this stage, it is desirable to form the second copper plating layer 60 on the pattern 31 and the via hole 35 by electrolytic copper plating of the copper laminate 100.

また、この段階では、２つの方法によりパターン３１とビアーホール３５とに第２のメッキ層６０を形成することができる。   At this stage, the second plating layer 60 can be formed on the pattern 31 and the via hole 35 by two methods.

第１の方法により、図６aに示すように、パターン３１とビアーホール３５との内部に第２のメッキ層６０が充填されるように、パターン３１とビアーホール３５とをフィールド(Filled)メッキすることができる。   As shown in FIG. 6a, the pattern 31 and the via hole 35 are field-plated by the first method so that the second plating layer 60 is filled in the pattern 31 and the via hole 35. be able to.

この場合、本明細書の図６aでは、第２のメッキ層６０の高さが第１のメッキ層４０の高さとほぼ同じであるようにフィールドメッキしたが、以下で説明する(g)段階でエッチングして、第１のメッキ層４０の除去時に、第２のメッキ層６０の高さが絶縁層３０の高さと同じであるように、第２のメッキ層６０の高さを調節してメッキすることができる。   In this case, in FIG. 6a of the present specification, the field plating is performed so that the height of the second plating layer 60 is substantially the same as the height of the first plating layer 40, but in the step (g) described below. Etching is performed to adjust the height of the second plating layer 60 so that the height of the second plating layer 60 is the same as the height of the insulating layer 30 when the first plating layer 40 is removed. can do.

第２の方法により、図６ｂに示すように、パターン３１の内部には、第２のメッキ層６０が充填されるようにパターン３１をフィールド(Filled)メッキし、ビアーホール３５は、表面のみに第２のメッキ層６０が形成されるように一般メッキすることができる。   According to the second method, as shown in FIG. 6B, the pattern 31 is field-filled so that the second plating layer 60 is filled in the pattern 31, and the via hole 35 is formed only on the surface. General plating can be performed so that the second plating layer 60 is formed.

実施形態によって、上記の２つの方法のうちで適切な方法を選択して、メッキを実施することができる。   Depending on the embodiment, plating can be performed by selecting an appropriate method from the above two methods.

次に、図７に示すように、メッキレジスト層５０を剥離する(メッキレジスト層の剥離段階、f段階)。   Next, as shown in FIG. 7, the plating resist layer 50 is stripped (plating resist layer stripping stage, stage f).

次に、図８に示すように、銅積層板１００をエッチングして第１のメッキ層４０を除去する(エッチング段階、g段階)。エッチングは、フラッシュエッチング(Flash etching)やソフトエッチング(Soft etching)とすることができる。   Next, as shown in FIG. 8, the copper laminate 100 is etched to remove the first plating layer 40 (etching stage, g stage). The etching can be flash etching or soft etching.

(g)段階の以後、エッチング時に、銅積層板１００の表面が平坦でない場合、言い換えれば、図８に示すように、パターン３１とビアーホール３５との内部に充填された第２のメッキ層６０の高さが、絶縁層３０の高さと同じでない場合は、銅積層板１００の表面が平坦化するように、絶縁層３０の高さになるまで第２のメッキ層６０を研磨することが望ましい。
After the step (g), when the surface of the copper laminate 100 is not flat during etching, in other words, as shown in FIG. 8, the second plating layer 60 filled in the pattern 31 and the via hole 35 is filled. Is not the same as the height of the insulating layer 30, it is desirable to polish the second plating layer 60 until the height of the insulating layer 30 is reached so that the surface of the copper laminate 100 is flattened. .

次に、図１０に示すように、ビアーホール３５を除いた銅積層板１００の表面にＰＳＲ(Photo solder resist)層７０を形成する(ＰＳＲ層の形成段階、h段階)。   Next, as shown in FIG. 10, a PSR (Photo solder resist) layer 70 is formed on the surface of the copper laminate 100 excluding the via hole 35 (PSR layer forming stage, h stage).

上記で説明した銅積層板１００の表面研磨により、銅積層板１００の表面が平坦な状態でＰＳＲ層７０を形成することで、クラック(Crack)を予防できる。 By polishing the surface of the copper laminate 100 described above, the PSR layer 70 is formed in a state where the surface of the copper laminate 100 is flat, thereby preventing cracks.

ＰＳＲ層７０を形成した後、後工程などを進めることができる。   After the PSR layer 70 is formed, a post process or the like can be performed.

以上のように、本発明は、たとえ限定された実施形態と図面により説明されたが、本発明は、これにより限定されることなく、本発明が属する技術分野において通常の知識を有する者が、本発明の技術思想と本願の特許請求範囲の均等範囲内で様々な修正及び変形が可能であることは言うまでもない。   As described above, the present invention has been described with reference to limited embodiments and drawings. However, the present invention is not limited thereto, and a person having ordinary knowledge in the technical field to which the present invention belongs Needless to say, various modifications and variations are possible within the scope of the technical idea of the present invention and the scope of claims of the present application.

本発明の望ましい実施形態に係る埋込型印刷回路基板の製造方法の順序図である。3 is a flowchart illustrating a method for manufacturing an embedded printed circuit board according to an exemplary embodiment of the present invention. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 図１の方法によって製造される印刷回路基板の断面図である。It is sectional drawing of the printed circuit board manufactured by the method of FIG. 従来技術に係る印刷回路基板を示した斜視図である。It is the perspective view which showed the printed circuit board based on a prior art.

符号の説明Explanation of symbols

１０ 絶縁基板
２０ 銅層
３０ 絶縁層
３１ パターン
３５ ビアーホール
４０ 第１のメッキ層
５０ メッキレジスト層
６０ 第２のメッキ層
７０ ＰＳＲ層
１００ 銅積層板。 10 Insulating substrate 20 Copper layer 30 Insulating layer 31 Pattern 35 Via hole 40 First plating layer 50 Plating resist layer 60 Second plating layer 70 PSR layer 100 Copper laminate.

Claims (4)

(a)絶縁基板（１０）の所定の箇所に複数個設けられた単層の銅層（２０）を蒸着し、次に絶縁基板（１０）及び銅層（２０）の上に絶縁層（３０）を蒸着して銅積層板（１００）を形成する銅積層板（１００）の形成段階と;
(b)前記絶縁層（３０）にパターン（３１）とビアーホール（３５）とを形成するパターニング段階と;
(c)前記銅積層板（１００）の表面を無電解メッキして前記銅積層板（１００）の表面に第１のメッキ層（４０）を形成する第１のメッキ層（４０）の形成段階と;
(d)前記パターン（３１）及び前記ビアーホール（３５）を除いた前記第１のメッキ層（４０）の表面にメッキレジスト層（５０）を形成するメッキレジスト層（５０）の形成段階と;
(e)前記銅積層板（１００）を電解銅メッキして、前記パターン（３１）と前記ビアーホール（３５）とに銅メッキ層である第２のメッキ層（６０）を形成する第２の銅メッキ層の形成段階と;
(f)前記メッキレジスト層（５０）を剥離するメッキレジスト層（５０）剥離段階と;
(g)前記銅積層板（１００）をエッチングして前記第１のメッキ層（４０）を除去するエッチング段階と;
(h)前記銅積層板（１００）の表面にＰＳＲ(Photo solder resist)層を形成するＰＳＲ層（７０）の形成段階と、を含み、
前記(g)段階と前記(h)段階との間に、
前記銅積層板（１００）の表面が平坦化するように、絶縁層（３０）の高さと同じになるまで第２の銅メッキ層を研磨する研磨段階を更に含む埋込型印刷回路基板の製造方法。 (a) depositing a copper layer of a plurality provided monolayer at a predetermined point insulation substrate (10) (20), then the insulating layer on the insulating substrate (10) and copper layer (20) ( Forming a copper laminate (100) by depositing 30) to form a copper laminate (100);
(b) a patterning step of forming a pattern (31) and a via hole (35) in the insulating layer (30);
(c) Forming the first plating layer (40) for forming the first plating layer (40) on the surface of the copper laminate (100) by electroless plating the surface of the copper laminate (100) When;
(d) forming a plating resist layer (50) for forming a plating resist layer (50) on the surface of the first plating layer (40) excluding the pattern (31) and the via hole (35);
(e) A second plating layer (60), which is a copper plating layer, is formed on the pattern (31) and the via hole (35) by electrolytic copper plating on the copper laminate (100). Forming a copper plating layer; and
(f) a plating resist layer (50) peeling step for peeling the plating resist layer (50);
(g) etching the copper laminate (100) to remove the first plating layer (40);
(h) forming a PSR layer (70) for forming a PSR (Photo solder resist) layer on the surface of the copper laminate (100),
Between the step (g) and the step (h),
Manufacturing an embedded printed circuit board further comprising a polishing step of polishing the second copper plating layer until the height of the insulating layer (30) is the same so that the surface of the copper laminate (100) is flattened. Method. 前記(b)段階において、
前記パターン（３１）と前記ビアーホール（３５）とは、レーザーにより形成することを特徴とする請求項１に記載の埋込型印刷回路基板の製造方法。 In the step (b),
The method of manufacturing an embedded printed circuit board according to claim 1, wherein the pattern (31) and the via hole (35) are formed by a laser. 前記(c)段階において、
前記銅積層板（１００）の表面を無電解銅メッキして、前記銅積層板（１００）の表面に第１の銅メッキ層を形成することを特徴とする請求項１に記載の埋込型印刷回路基板の製造方法。 In step (c),
The embedded mold according to claim 1 , wherein the surface of the copper laminate (100) is electroless copper plated to form a first copper plating layer on the surface of the copper laminate (100). A method of manufacturing a printed circuit board. 前記(e)段階において、In step (e),
パターン（３１）の内部には、第２のメッキ層（６０）が充填されるようにパターン（３１）をメッキし、ビアーホール（３５）は表面のみに第２のメッキ層（６０）が形成されることを特徴とする請求項１に記載の埋込型印刷回路基板の製造方法。The pattern (31) is plated so that the second plating layer (60) is filled inside the pattern (31), and the second plating layer (60) is formed only on the surface of the via hole (35). The method of manufacturing an embedded printed circuit board according to claim 1, wherein:
JP2008103101A 2007-12-27 2008-04-11 Method for manufacturing embedded printed circuit board Expired - Fee Related JP4703680B2 (en)

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