WO2013089439A1

WO2013089439A1 - The printed circuit board and the method for manufacturing the same

Info

Publication number: WO2013089439A1
Application number: PCT/KR2012/010808
Authority: WO
Inventors: Byeong Ho Kim; Yeong Uk Seo; Hyun Seok Seo; Chang Woo Yoo; Sang Myung Lee; Ki Do Chun
Original assignee: Lg Innotek Co., Ltd.
Priority date: 2011-12-15
Filing date: 2012-12-12
Publication date: 2013-06-20
Also published as: TW201334646A

Abstract

Disclosed are a printed circuit board and a method of fabricating the same. The method includes preparing an insulating substrate, forming a circuit pattern groove on a surface of the insulating substrate, plating a first metal layer on the substrate of the insulating substrate, forming a plating layer burying the circuit pattern groove by performing a plating process using the first metal layer of the circuit pattern groove as a seed layer, forming a buried pattern by removing the plating layer through chemical mechanical polishing until an insulating layer is exposed, and forming a concave pattern on a top surface of the buried pattern through a flash etching. Both of the half-etching process and the flash etching process in order to improve the efficiency of the chemical mechanical polishing are performed, thereby preventing the short between the patterns.

Description

THE PRINTED CIRCUIT BOARD AND THE METHOD FOR MANUFACTURING THE SAME

The disclosure relates to a printed circuit board and a method of fabricating the same.

A printed circuit board (PCB) is formed by printing a circuit line pattern on an electrical insulating substrate by using a conductive material such as copper (Cu), and refers to a board right before electronic parts are mounted thereon. In other words, the PCB refers to a circuit board in which the mounting positions of the electronic parts are determined, and a circuit pattern connecting the electronic parts is fixedly printed on a flat plate in order to densely mount electronic devices on the flat plate.

Meanwhile, in recent years, a buried pattern substrate having the reduced thickness and planarized surface has been used for the purpose of high performance and miniaturization of electronic parts.

FIG. 1 is a view showing a typical buried pattern PCB 10.

As shown in FIG. 1, the buried pattern PCB 10 includes a buried pattern groove 2 in the surface of an insulating substrate 1 and a circuit pattern 3 formed by filling the buried pattern groove 2 through a plating process.

The PCB 10 having the buried circuit pattern 3 can represent very strong adhesive strength with respect to an insulating member due to the formation structure of a base circuit pattern and a contact part, and the pitches of base circuit patterns and contact parts can be uniformly and finely formed.

However, when the buried circuit pattern 3 is formed through the plating scheme, plating variation occurs between a region having the pattern groove 2 and a region without the pattern groove 2, so that the etching process may not be uniformly performed after the plating process. Therefore, one region of the circuit pattern 3 may be not etched as shown in FIG. 1, so that the circuit pattern 3 may be shorted with respect to an adjacent circuit pattern. In addition, another region of the circuit pattern 3 may be over-etched, so that errors may occur in signal transmission.

The embodiment provides a printed circuit board having a novel structure and a method of fabricating the same.

The embodiment provides a novel method of fabricating a buried circuit pattern.

According to the embodiment, there is provided a method of fabricating a printed circuit board. The method includes preparing an insulating substrate, forming a circuit pattern groove on a surface of the insulating substrate, plating a first metal layer on the substrate of the insulating substrate, forming a plating layer burying the circuit pattern groove by performing a plating process using the first metal layer of the circuit pattern groove as a seed layer, forming a buried pattern by removing the plating layer through chemical mechanical polishing until an insulating layer is exposed, and forming a concave pattern on a top surface of the buried pattern through a flash etching.

According to the embodiment, there is provided a printed circuit board including an insulating substrate provided on a surface thereof with a plurality of circuit pattern grooves, and a plurality of circuit patterns formed by filling the circuit pattern grooves. Each circuit pattern is provided on a top surface thereof with a concave shape.

As described above, the circuit pattern is formed by filling the groove of the substrate through the plating scheme, and the plating layer on the insulating layer is removed through the chemical mechanical polishing, thereby simply forming the micro-buried pattern.

In addition, both of the half-etching process and the flash etching process in order to improve the efficiency of the chemical mechanical polishing are performed, thereby preventing the short between the patterns.

In addition, the circuit pattern is formed in the curved shape without edges, thereby reducing the noise and the heat caused from the edge, and thereby realizing the high-speed and the high-integrated package.

FIG. 1 is a sectional view showing a printed circuit board according to the related art;

FIG. 2 is a sectional view showing a printed circuit board according to the embodiment;

FIGS. 3 to 10 are sectional views showing the method of fabricating the printed circuit board according to the embodiment;

FIGS. 11 and 12 are photographs showing the printed circuit board according to the embodiment; and

FIG. 13 is a sectional view showing a printed circuit board according to another embodiment.

Hereinafter, embodiments will be described in detail with reference to accompanying drawings so that those skilled in the art can easily work with the embodiments. However, the embodiments may have various modifications.

In the following description, when a predetermined part “includes” a predetermined component, the predetermined part does not exclude other components, but may further include other components if there is a specific opposite description.

The thickness and size of each layer shown in the drawings may be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity. In addition, the size of elements does not utterly reflect an actual size. The same reference numbers will be assigned the same elements throughout the drawings.

In the description of the embodiments, it will be understood that, when a layer, a film, or a plate is referred to as being “on” or “under” another layer, another film, another region, or another plate, it can be “directly” or “indirectly” on the other layer, film, region, plate, or one or more intervening layers may also be present. Such a position of the layer has been described with reference to the drawings.

The disclosure provides a method of forming a circuit pattern through chemical mechanical polishing in a printed circuit board (PCB) having a buried pattern circuit pattern.

Hereinafter, the PCB according to the embodiment will be described with reference to FIGS. 2 to 12.

FIG. 2 is a sectional view showing the PCB according to the embodiment.

Referring to FIG. 2, a PCB 100 according to the embodiment includes an insulating plate 110, a first circuit pattern 120 formed on the insulating plate 110, an insulating layer 130, and a plurality of second circuit patterns 150.

The insulating plate 110 may include thermosetting substrate, thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber impregnation substrate. If the insulating plate 110 includes a polymer resin, the insulating plate 110 may include an epoxy-based insulating resin, or may include polyimide-based resin.

The insulating plate 110 is formed thereon with a plurality of first circuit patterns 120 serving as a base circuit pattern.

In addition, the first circuit pattern 120 may include a material representing high electrical conductivity and low resistance. In particular, the first circuit pattern 120 may be formed by patterning a thin copper film as a conductive layer. If the first circuit pattern 120 is a copper film, and the insulating plate 110 includes resin, the first circuit pattern 120 and the insulating plate 110 may have a typical copper clad laminate (CCL) structure.

Meanwhile, the insulating layer 130 is formed by burying the first circuit pattern 120 on the insulating plate 110.

The insulating layer 130 may include a plurality of insulating layers 130, and each insulating layer 130 may include polymer resin.

The insulating layer 130 includes a via hole 135 to expose the first circuit pattern 120 and circuit pattern grooves 131 to form the second circuit patterns 150.

In this case, the circuit pattern groove 131 has an inclined sectional shape. Preferably, the section of the circuit pattern groove 131 has a width gradually narrowed downward.

Each circuit pattern groove 131 has a width in the range of 3㎛ to 25㎛, and a depth in the range of 3㎛ to 25㎛. In addition, the via hole 135 has a diameter of about 80㎛ or less and a depth of about 100㎛ or less.

A metal layer 140 is formed in via holes 135 of the insulating layer 130 and the circuit pattern groove 131 along the shape of the circuit pattern groove 131.

The metal layer 140 may serve as a seed layer, and may include copper (Cu), nickel (Ni), or the alloy thereof.

The metal layer 140 is formed thereon with the second circuit pattern 150 and a via 151 to fill the circuit pattern groove 131 and the via hole 135.

The second circuit pattern 150 and the via 151 are simultaneously formed, and may include the alloy including at least one of aluminum (Al), copper (Cu), silver (Ag), platinum (Pt), nickel (Ni), and palladium (Pd). The second circuit pattern 150 and the via 151 may be formed by performing a plating process using the metal layer 140 as a seed layer.

The second circuit pattern 150 and the via 151 have a concave shape with a depth lowered from the edge region to the central region thereof.

Hereinafter, a method of fabricating the PCB 100 of FIG. 2 will be described with reference to FIGS. 3 to 10.

As shown in FIG. 3, the first circuit pattern 120 is formed on the insulating plate 110.

The structure of the insulating plate 110 and the first circuit pattern 120 may be formed by etching the thin copper layer of the CCL according to the design of the first circuit pattern 120. Alternatively, the structure of the insulating plate 110 and the first circuit pattern 120 may be formed by stacking a copper film on a ceramic substrate and etching the resultant structure.

In this case, the first circuit pattern 120 may include a pattern connected to the second circuit pattern 150 through the via hole 135 as shown in FIG. 2.

Next, the insulating substrate is prepared by forming the insulating layer 130 to cover the first circuit pattern 120 on the insulating plate 110.

The insulating layer 130 may include a thermosetting resin. The insulating layer 130 can be formed by coating a B-stage resin on the insulating plate 110 at a predetermined thickness and curing the B-stage resin by applying heat and pressure to the B-stage resin. It is also possible to provide a plurality of insulating layers 130.

Next, as shown in FIG. 4, the via hole 135 is formed in the insulating layer 130 to expose the first circuit pattern 120. As shown in FIG. 4, the via hole 135 may have sidewalls inclined at a predetermined angle with respect to a flat surface of the substrate. Alternatively, the via hole 135 may have sidewalls perpendicular to the flat surface of the substrate.

The via hole 135 can be formed by using a laser, such as a UV laser or a CO2 laser.

In addition, the via hole 135 may be formed through a physical scheme. For instance, the via hole 135 may be formed through a drilling process. Further, the via hole 135 may be formed through a selective chemical etching process.

Subsequently, as shown in FIG. 5, the circuit pattern groove 131 is formed in the insulating layer 130 to form the second circuit pattern 150. As shown in FIG. 5, the circuit pattern groove 131 may be formed by using an excimer laser irradiating a laser beam having ultraviolet wavelengths. The excimer laser may include a KrF excimer laser (krypton fluoride, central wavelength of 248 nm) or an ArF excimer laser (argon fluoride, central wavelength of 193 nm).

When the circuit pattern grooves 131 are formed by using the excimer laser, the circuit pattern grooves 131 may be formed by forming a pattern mask 200 for simultaneously forming the circuit pattern grooves 131 and selectively irradiating the excimer laser through the pattern mask 200.

As shown in FIG. 5, when the circuit pattern grooves 131 are formed through the pattern mask 200 by using the excimer laser, the section of the each circuit pattern groove 131 has a trapezoidal edge or a rectangular edge as shown in FIG. 5.

At this time, a recess having an area larger than exposed top portions of the via holes 135 can be formed in a region having the via holes 135 in such a manner that the via holes 135 may have the layered structure.

If the via holes 135 have the layered structure, the expanded top portions of the via holes 135 can be used as pads for mounting devices, so the mounting area for the device can be ensured.

Next, the smear on the surface of the insulating layer 130 is removed by performing a desmear process.

In detail, after bulging the surface of the insulating layer 130, the bulged insulating layer 130 is removed by using permanganate, and a wet etching process is performed to neutralize the insulating layer 130, thereby removing the insulating layer.

The roughness may be provided on the surface of the insulating layer 130 through the desmear process.

Next, as shown in FIG. 6, the metal layer 140 is formed on the insulating layer 130.

The metal layer 140 may be formed through an electroless plating scheme.

The electroless plating scheme may be performed in the sequence of a degreasing process, a soft etching process, a pre-catalyst process, a catalyst treatment process, an accelerator process, an electroless plating process, and an anti-oxidation treatment process. In addition, the metal layer 140 may be formed by sputtering metallic particles using plasma.

The metal layer 140 includes the alloy including Cu, Ni, Pd, or Cr.

Then, as shown in FIG. 7, an electroplating process is performed with respect to a conductive material using the metal layer 140 as a seed layer, thereby forming a plating layer 155.

The plating layer 155 may be formed by performing the electroplating process using the metal layer 140 as a seed layer, and the electroplating process may be performed while controlling current according to a plating area.

The plating layer 155 may include Cu representing high electrical conductivity.

In this case, the plating layer 155 is formed at a first thickness h2 from the top surface of the insulating layer 130.

Subsequently, as shown in FIG. 8, the plating layer 155 is etched through a half-etching process, so that the plating layer 155 has the second thickness h3.

The second thickness h3 obtained through the half-etching process satisfies 1/3 or less of the first thickness h2.

Subsequently, as shown in FIG. 9, chemical mechanical etching is performed to remove the plating layer 155 on the insulating layer 130.

In other words, referring to FIG. 9, after placing the PCB 100 on a plate 310, the over-plated plating layer 155 is polished at the basic atmosphere of pH 9 or above. Preferably, the over-plated plating layer 155 is polished by using slurry in which ammonia is added as a main component and peroxide is added in the small quantity.

A polisher 320 rotates on the plate 310 to induce the physical etching for the over-plated plating layer and the slurry.

Accordingly, as shown in FIG. 9, the plating layer 155 is etched until the insulating layer 130 is exposed through the chemical mechanical etching, so that the plating layer 155 remaining on the insulating layer 130 is removed.

The plate 310 may have a diameter of 1300 mm or less. In addition, the plate 310 may be provided with a heat wire so that heat is transferred to the PCB 100. Accordingly, the PCB 100 having the size of 510 ㎜ × 410 ㎜ or larger can be simultaneously etched, so that the plating layer having a large area may be removed.

If the chemical mechanical etching is performed, the top surface of the second circuit pattern 150 is in line with the top surface of the insulating layer 130.

Subsequently, as shown in FIG. 10, the central regions of the second circuit pattern 150 and the via 151 are etched by performing a flash etching process so that the central regions of the second circuit pattern 150 and the via 151 are recessed in the concave shape.

The metallic particles remaining on the surface of the insulating layer 130 are removed through the flash etching process, thereby preventing the electrical short between patterns.

In other words, referring to FIGS. 11 and 12, if the components of the surface of the insulating layer 130 are detected after the chemical mechanical etching has been performed, Cu is detected in addition t_o carbon (C) and oxygen (O). In this case, if the components of the surface of the insulating layer 130 are detected after the chemical mechanical etching is performed and the flash etching process is performed, Cu is not detected at all.

Hereinafter, the PCB according to another embodiment will be described with reference to FIG. 13.

Referring to FIG. 13, a PCB includes the insulating plate 110, the first circuit pattern 120 formed on the insulating plate 110, the insulating layer 130, and the second circuit patterns 150.

The insulating plate 110 is formed thereon with the first circuit patterns 120 serving as a base circuit pattern.

The insulating layer 130 includes the via holes 135 to expose the first circuit pattern 120 and the circuit pattern grooves 131 used to form the second circuit patterns 150.

In this case, each circuit pattern groove 131 has a curved section, and, preferably, has a U-shape section.

A metal layer 140 is formed in the via holes 135 of the insulating layer 130 and the circuit pattern groove 131 along the U shape of the circuit pattern groove 131.

The metal layer 140 may serve as a seed layer, and may include Cu, Ni, or the alloy thereof.

The second circuit pattern 150 and the via 151 are simultaneously formed, and may include the alloy including at least one of Al, Cu, Ag, Pt, Ni, and Pd. The second circuit pattern 150 and the via 151 may be formed by performing a plating process using the metal layer 140 as a seed layer.

In the case of the PCB 400 of FIG. 13, the circuit pattern groove 131 of the insulating layer 130 has a curved shape, and metal is filled in the curved-shape circuit pattern groove 131, thereby forming the second circuit pattern 150.

In addition, even in the PCB 400 of FIG. 13, since the flash etching is performed after the chemical mechanical polishing has been performed, the top surfaces of the second circuit pattern and the via have a concave shape similarly to the PCB 100 of FIG. 2.

As described above, the second circuit pattern 150 is formed in the curved shape without an edge, thereby preventing resistance from being concentrated on the edge so that the signal noise is not caused, and thereby preventing the increase of the heating at the edge.

Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.

Claims

A method of fabricating a printed circuit board, the method comprising:

preparing an insulating substrate;

forming a circuit pattern groove on a surface of the insulating substrate;

plating a first metal layer on the substrate of the insulating substrate;

forming a plating layer burying the circuit pattern groove by performing a plating process using the first metal layer of the circuit pattern groove as a seed layer;

forming a buried pattern by removing the plating layer through chemical mechanical polishing until an insulating layer is exposed; and

forming a concave pattern on a top surface of the buried pattern through a flash etching.
The method of claim 1, wherein, in the forming of the circuit pattern groove on the surface of the insulating substrate, the circuit pattern groove is formed by using a laser.
The method of claim 1, wherein, in the forming of the buried pattern by removing the plating layer through the chemical mechanical polishing until the insulating layer is exposed, the plating layer is removed by using slurry at an basic atmosphere of pH 9 or above.
The method of claim 3, wherein the basic atmosphere is formed by mixing ammonia and peroxide with the slurry.
The method of claim 4, wherein the chemical mechanical polishing etches the printed circuit board on a plate while applying heat to the printed circuit board at the basic atmosphere.
The method of claim 1, wherein the preparing of the insulating substrate comprises:

preparing an insulating plate;

forming a base circuit pattern on the insulating plate by patterning a thin copper film; and

forming an insulating layer on the insulating plate while covering the base circuit pattern, and

wherein the circuit pattern groove is formed on a surface of the insulating layer.
The method of claim 1, further comprising forming a via hole, which exposes the base circuit pattern, in the insulating layer after the insulating layer has been formed.
The method of claim 1, further comprising reducing a thickness of the plating layer by performing a half-etching process before the chemical mechanical polishing has been performed.
The method of claim 8, wherein the half-etching is performed such that the thickness of the plating layer is reduced to 1/3.
The method of claim 1, wherein the first metal layer includes one selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), chrome (Cr), and an alloy thereof.
A printed circuit board comprising:

an insulating substrate provided on a surface thereof with a plurality of circuit pattern grooves; and

a plurality of circuit patterns formed by filling the circuit pattern grooves,

wherein each circuit pattern is provided on a top surface thereof with a concave pattern.
The printed circuit board of claim 11, wherein each circuit pattern groove and each buried circuit pattern have a curved section.
The printed circuit board of claim 11, wherein the circuit pattern groove and the buried circuit pattern have a U shape-section.
The printed circuit board of claim 11, wherein the insulating substrate comprises:

an insulating plate;

a base circuit pattern patterned on the insulating plate; and

an insulating layer formed on the insulating plate while covering the base circuit pattern,

wherein the circuit pattern groove is formed on a surface of the insulating layer.
The printed circuit board of claim 14, wherein the insulating layer includes a via hole to expose the base circuit pattern.
The printed circuit board of claim 15, further comprising a via to fill the via hole, wherein the via is provided on a top surface thereof with a concave pattern.
The printed circuit board of claim 11, further comprising a metal layer formed along the circuit pattern groove.
The printed circuit board of claim 17, wherein the metal layer includes one selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), chrome (Cr), and an alloy thereof.