JP4632114B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
- Publication number
- JP4632114B2 JP4632114B2 JP2003393386A JP2003393386A JP4632114B2 JP 4632114 B2 JP4632114 B2 JP 4632114B2 JP 2003393386 A JP2003393386 A JP 2003393386A JP 2003393386 A JP2003393386 A JP 2003393386A JP 4632114 B2 JP4632114 B2 JP 4632114B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- internal clock
- address
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Description
2、12、63 内部クロック発生回路
3 読取りコマンドラッチ回路
3−A PREコマンドラッチ回路
3−B A0アドレスラッチ回路
4、13 反転信号入力回路
5 Y系回路
6 X系回路
21A、21B パルス発生回路
22 カウンタ
31 (コマンド)デコーダ
32 コマンドラッチ回路
32A、32B、34A、34B ラッチ回路
33 (コマンド)出力回路
34 アドレスラッチ回路
35 (アドレス)選択回路
41 Y系制御回路
42 Y系救済回路
43 X系制御回路
44 リフレッシュカウンタ
45 X系救済回路
51 読取り系制御回路
52 信号出力回路
53 主増幅器
54、66 FIFO
55 データ出力回路
61 書込み系制御回路
62 信号入力回路
64 データ入力回路
65 データラッチ回路
67 書込み増幅器
70 メモリブロック
71 メモリアレイ
72 Yデコーダ
73 Xデコーダ
74 メインアンプ
79 メモリセル
80 内部電圧発生回路
Claims (1)
- 外部クロック信号に同期してアドレス、コマンド及びデータのラッチ用内部クロック信号を発生する内部クロック発生回路を有し、前記内部クロック信号に従ってアドレス及びコマンドの入力並びにデータの入出力をする同期式の記憶装置に用いられる半導体集積回路装置において、
前記外部クロック信号に同期する相補の分周クロックを発生し、該相補の分周クロックに各々対応するワンショットパルスの内部クロック信号を二系統発生し送出する前記内部クロック発生回路と、前記二系統の内部クロック信号のそれぞれを受け、前記内部クロック信号に基づいて外部からの入力信号をラッチし送出する一対のラッチ回路とを備え、
前記外部クロック信号に基づく動作が停止モードとなった後に、前記二系統の内部クロック信号を制御信号による制御を行うことなく共にリセット状態とすることを特徴とする半導体集積回路装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003393386A JP4632114B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体集積回路装置 |
TW093135960A TWI251237B (en) | 2003-11-25 | 2004-11-23 | Latch circuit and synchronous memory including the same |
US10/995,528 US7113446B2 (en) | 2003-11-25 | 2004-11-24 | Latch circuit and synchronous memory including the same |
CNB2004100962493A CN100479058C (zh) | 2003-11-25 | 2004-11-25 | 锁存电路和包括该电路的同步存储器 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003393386A JP4632114B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005158127A JP2005158127A (ja) | 2005-06-16 |
JP4632114B2 true JP4632114B2 (ja) | 2011-02-16 |
Family
ID=34696768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003393386A Expired - Fee Related JP4632114B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体集積回路装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7113446B2 (ja) |
JP (1) | JP4632114B2 (ja) |
CN (1) | CN100479058C (ja) |
TW (1) | TWI251237B (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100632611B1 (ko) | 2004-11-15 | 2006-10-09 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 명령 디코더 |
US20060117201A1 (en) * | 2004-11-30 | 2006-06-01 | Infineon Technologies North America Corp. | Variable pipeline circuit |
KR100588593B1 (ko) * | 2005-06-09 | 2006-06-14 | 삼성전자주식회사 | 레지스터형 메모리 모듈 및 그 제어방법 |
KR100674981B1 (ko) * | 2005-07-02 | 2007-01-29 | 삼성전자주식회사 | 칼럼선택 라인을 개선한 반도체 메모리 장치 및 그구동방법 |
US7738307B2 (en) * | 2005-09-29 | 2010-06-15 | Hynix Semiconductor, Inc. | Data transmission device in semiconductor memory device |
KR100753036B1 (ko) | 2005-09-29 | 2007-08-30 | 주식회사 하이닉스반도체 | 펄스 제어 장치 |
KR100656432B1 (ko) * | 2005-11-09 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 컬럼 선택신호 제어장치 및 방법 |
KR100659159B1 (ko) * | 2005-12-07 | 2006-12-19 | 삼성전자주식회사 | 메모리 모듈 |
KR100753412B1 (ko) | 2006-01-13 | 2007-08-30 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 커맨드 디코더 회로 |
US7355920B2 (en) * | 2006-02-16 | 2008-04-08 | Micron Technology, Inc. | Write latency tracking using a delay lock loop in a synchronous DRAM |
US7362651B2 (en) * | 2006-05-12 | 2008-04-22 | International Business Machines Corporation | Using common mode differential data signals of DDR2 SDRAM for control signal transmission |
US20110026385A1 (en) * | 2008-06-12 | 2011-02-03 | Nobuyuki Nakai | Semiconductor storage device, semiconductor device and optical disc reproducing device |
JP5146284B2 (ja) | 2008-11-27 | 2013-02-20 | 株式会社リコー | データ転送装置及びデータ転送方法 |
KR101009336B1 (ko) * | 2008-12-31 | 2011-01-19 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 구동 방법 |
TWI401695B (zh) * | 2009-01-23 | 2013-07-11 | Nanya Technology Corp | 訊號調整系統與訊號調整方法 |
US8432195B2 (en) | 2010-11-05 | 2013-04-30 | Qualcomm Incorporated | Latch circuits with synchronous data loading and self-timed asynchronous data capture |
JP2012226800A (ja) * | 2011-04-19 | 2012-11-15 | Elpida Memory Inc | 半導体装置及びその制御方法並びに情報処理システム |
CN102881318B (zh) * | 2011-07-13 | 2015-02-18 | 苏州雄立科技有限公司 | 一种应用于静态随机存储器中的灵敏放大器 |
CN103632708B (zh) * | 2012-08-28 | 2016-08-10 | 珠海全志科技股份有限公司 | 同步动态随机存储器的自刷新控制装置及方法 |
US9159391B1 (en) | 2012-12-13 | 2015-10-13 | Gsi Technology, Inc. | Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features |
US9431079B1 (en) * | 2012-12-13 | 2016-08-30 | Gsi Technology, Inc. | Systems and methods of memory and memory operation involving input latching, self-timing and/or other features |
KR102311512B1 (ko) * | 2015-08-21 | 2021-10-13 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US9959918B2 (en) | 2015-10-20 | 2018-05-01 | Samsung Electronics Co., Ltd. | Memory device and system supporting command bus training, and operating method thereof |
US9754650B2 (en) * | 2015-10-20 | 2017-09-05 | Samsung Electronics Co., Ltd. | Memory device and system supporting command bus training, and operating method thereof |
CN106569921B (zh) * | 2016-10-17 | 2019-01-08 | 国家电网公司 | 一种双芯智能电能表的计量芯时钟处理方法及装置 |
KR20190046491A (ko) * | 2017-10-26 | 2019-05-07 | 삼성전자주식회사 | 반도체 메모리, 반도체 메모리를 포함하는 메모리 시스템, 그리고 반도체 메모리의 동작 방법 |
KR20200082918A (ko) * | 2018-12-31 | 2020-07-08 | 에스케이하이닉스 주식회사 | 클럭 생성 회로 및 이를 포함하는 메모리 장치 |
KR20230117999A (ko) | 2022-02-03 | 2023-08-10 | 에스케이하이닉스 주식회사 | 프리차지동작을 수행하기 위한 전자장치 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000040364A (ja) * | 1998-07-13 | 2000-02-08 | Samsung Electronics Co Ltd | 同期式半導体メモリ装置及びその基準信号発生回路 |
JP2000100170A (ja) * | 1998-09-24 | 2000-04-07 | Fujitsu Ltd | 高速クロックに対応可能な入力バッファを持つ集積回路装置 |
JP2000311486A (ja) * | 1999-02-24 | 2000-11-07 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP2000357390A (ja) * | 1999-06-11 | 2000-12-26 | Hitachi Ltd | パルス発生回路 |
JP2001155483A (ja) * | 1999-11-30 | 2001-06-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2001177384A (ja) * | 1999-11-22 | 2001-06-29 | Hyundai Electronics Ind Co Ltd | パルス発生器 |
JP2002025254A (ja) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体メモリ |
JP2002245778A (ja) * | 2001-02-16 | 2002-08-30 | Fujitsu Ltd | 半導体装置 |
JP2002374164A (ja) * | 2001-06-13 | 2002-12-26 | Mitsubishi Electric Corp | 半導体装置 |
JP2003132680A (ja) * | 2001-06-30 | 2003-05-09 | Hynix Semiconductor Inc | レジスタ制御ディレイロックループ及びそれを備えた半導体デバイス |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3315501B2 (ja) * | 1993-11-19 | 2002-08-19 | 株式会社日立製作所 | 半導体記憶装置 |
JP2742220B2 (ja) * | 1994-09-09 | 1998-04-22 | 松下電器産業株式会社 | 半導体記憶装置 |
JPH1074386A (ja) * | 1996-08-30 | 1998-03-17 | Hitachi Ltd | 半導体記憶装置及びデータ処理装置 |
JP3903588B2 (ja) * | 1997-07-31 | 2007-04-11 | ソニー株式会社 | 信号変化検出回路 |
JP3982934B2 (ja) * | 1998-01-21 | 2007-09-26 | 富士通株式会社 | 入力回路および該入力回路を有する半導体集積回路 |
JP4017248B2 (ja) * | 1998-04-10 | 2007-12-05 | 株式会社日立製作所 | 半導体装置 |
JP3773863B2 (ja) * | 2001-07-19 | 2006-05-10 | 三菱電機株式会社 | 半導体装置 |
JP4308461B2 (ja) * | 2001-10-05 | 2009-08-05 | ラムバス・インコーポレーテッド | 半導体記憶装置 |
-
2003
- 2003-11-25 JP JP2003393386A patent/JP4632114B2/ja not_active Expired - Fee Related
-
2004
- 2004-11-23 TW TW093135960A patent/TWI251237B/zh not_active IP Right Cessation
- 2004-11-24 US US10/995,528 patent/US7113446B2/en not_active Expired - Fee Related
- 2004-11-25 CN CNB2004100962493A patent/CN100479058C/zh not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000040364A (ja) * | 1998-07-13 | 2000-02-08 | Samsung Electronics Co Ltd | 同期式半導体メモリ装置及びその基準信号発生回路 |
JP2000100170A (ja) * | 1998-09-24 | 2000-04-07 | Fujitsu Ltd | 高速クロックに対応可能な入力バッファを持つ集積回路装置 |
JP2000311486A (ja) * | 1999-02-24 | 2000-11-07 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP2000357390A (ja) * | 1999-06-11 | 2000-12-26 | Hitachi Ltd | パルス発生回路 |
JP2001177384A (ja) * | 1999-11-22 | 2001-06-29 | Hyundai Electronics Ind Co Ltd | パルス発生器 |
JP2001155483A (ja) * | 1999-11-30 | 2001-06-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002025254A (ja) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体メモリ |
JP2002245778A (ja) * | 2001-02-16 | 2002-08-30 | Fujitsu Ltd | 半導体装置 |
JP2002374164A (ja) * | 2001-06-13 | 2002-12-26 | Mitsubishi Electric Corp | 半導体装置 |
JP2003132680A (ja) * | 2001-06-30 | 2003-05-09 | Hynix Semiconductor Inc | レジスタ制御ディレイロックループ及びそれを備えた半導体デバイス |
Also Published As
Publication number | Publication date |
---|---|
TWI251237B (en) | 2006-03-11 |
CN1627441A (zh) | 2005-06-15 |
TW200529231A (en) | 2005-09-01 |
US7113446B2 (en) | 2006-09-26 |
JP2005158127A (ja) | 2005-06-16 |
US20050141333A1 (en) | 2005-06-30 |
CN100479058C (zh) | 2009-04-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4632114B2 (ja) | 半導体集積回路装置 | |
US6801460B2 (en) | Semiconductor memory device suppressing peak current | |
KR100261640B1 (ko) | 동기형 다이나믹형 반도체 기억 장치 | |
JP4684394B2 (ja) | 半導体集積回路装置 | |
US7466623B2 (en) | Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof | |
JP4370507B2 (ja) | 半導体集積回路装置 | |
KR100572840B1 (ko) | 로우 디코더를 갖는 메모리 장치 | |
US20040100856A1 (en) | Semiconductor memory device adaptive for use circumstance | |
US6496403B2 (en) | Semiconductor memory device | |
US6789137B2 (en) | Semiconductor memory device allowing reduction of I/O terminals | |
US6166993A (en) | Synchronous semiconductor memory device | |
US6456563B1 (en) | Semiconductor memory device that operates in sychronization with a clock signal | |
JP2003059267A (ja) | 半導体記憶装置 | |
US6339560B1 (en) | Semiconductor memory based on address transitions | |
US9076503B2 (en) | Semiconductor device | |
US6636455B2 (en) | Semiconductor memory device that operates in synchronization with a clock signal | |
US20100110747A1 (en) | Semiconductor memory device | |
KR100728927B1 (ko) | 반도체집적회로장치 | |
KR20010102846A (ko) | 동기형 반도체 기억 장치 | |
US11043255B2 (en) | Memory device with improved writing features | |
US7668032B2 (en) | Refresh operation of memory device | |
CN110998732B (zh) | 输入缓冲器电路 | |
CN116417039A (zh) | 存储器装置布局 | |
JP2001014894A (ja) | 半導体記憶装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20050322 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071113 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071121 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080121 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20080702 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080828 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20080912 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20081003 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100921 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101104 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131126 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131126 Year of fee payment: 3 |
|
SG99 | Written request for registration of restore |
Free format text: JAPANESE INTERMEDIATE CODE: R316G99 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131126 Year of fee payment: 3 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131126 Year of fee payment: 3 |
|
SG99 | Written request for registration of restore |
Free format text: JAPANESE INTERMEDIATE CODE: R316G99 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131126 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S803 | Written request for registration of cancellation of provisional registration |
Free format text: JAPANESE INTERMEDIATE CODE: R316803 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |