JP4600837B2 - 半導体装置の製造方法 - Google Patents
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- JP4600837B2 JP4600837B2 JP2006341634A JP2006341634A JP4600837B2 JP 4600837 B2 JP4600837 B2 JP 4600837B2 JP 2006341634 A JP2006341634 A JP 2006341634A JP 2006341634 A JP2006341634 A JP 2006341634A JP 4600837 B2 JP4600837 B2 JP 4600837B2
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- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000002955 isolation Methods 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 239000007772 electrode material Substances 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
半導体基板上の前記Fin型チャネルの形成領域を覆う所定厚みの絶縁膜パターンを形成する工程と、
前記絶縁膜パターンをマスクとして、前記半導体基板を選択的にエッチングして素子間分離トレンチを形成し、該素子間分離トレンチ内に素子分離絶縁膜を埋め込む工程と、
前記絶縁膜パターンの一部を選択的にエッチングして、前記トレンチ型ゲートの形成領域上にのみ前記絶縁膜パターンを残存させる工程と、
前記残存した絶縁膜パターンで覆われずに露出している、前記Fin型チャネルの形成領域の半導体基板の表面に、選択成長半導体層を前記絶縁膜パターンの所定厚み以下の膜厚で形成する工程と、
前記残存した絶縁膜パターンを除去して前記トレンチ型ゲートの形成領域の前記半導体基板表面を露出し、且つ、前記素子分離絶縁膜を、前記絶縁膜パターンの所定厚み以上である所定深さまでエッチング除去する工程と、
露出した前記半導体基板の表面部分及び露出した前記選択成長半導体層の表面部分を覆うゲート絶縁膜を形成する工程と、
前記トレンチ型ゲートの形成領域を覆い、平面視で前記Fin型チャネルの形成領域と交差するように延在するゲート電極を前記ゲート絶縁膜上に形成する工程と、
を有することを特徴とする。
12:絶縁膜パターン
13:素子分離絶縁膜
14:ゲート酸化膜(絶縁膜)
15:ゲート電極
16:サイドウオール絶縁膜
17:コンタクトプラグ
20:Fin型チャネル
21:レジストパターン
22:選択成長シリコン層
Claims (3)
- 半導体基板上に、Fin型チャネル及びトレンチ型ゲートを有するMISFETを形成する半導体装置の製造方法において、
半導体基板上の前記Fin型チャネルの形成領域を覆う所定厚みの絶縁膜パターンを形成する工程と、
前記絶縁膜パターンをマスクとして、前記半導体基板を選択的にエッチングして素子間分離トレンチを形成し、該素子間分離トレンチ内に素子分離絶縁膜を埋め込む工程と、
前記絶縁膜パターンの一部を選択的にエッチングして、前記トレンチ型ゲートの形成領域上にのみ前記絶縁膜パターンを残存させる工程と、
前記残存した絶縁膜パターンで覆われずに露出している、前記Fin型チャネルの形成領域の半導体基板の表面に、選択成長半導体層を前記絶縁膜パターンの所定厚み以下の膜厚で形成する工程と、
前記残存した絶縁膜パターンを除去して前記トレンチ型ゲートの形成領域の前記半導体基板表面を露出し、且つ、前記素子分離絶縁膜を、前記絶縁膜パターンの所定厚み以上である所定深さまでエッチング除去する工程と、
露出した前記半導体基板の表面部分及び露出した前記選択成長半導体層の表面部分を覆うゲート絶縁膜を形成する工程と、
前記トレンチ型ゲートの形成領域を覆い、平面視で前記Fin型チャネルの形成領域と交差するように延在するゲート電極を前記ゲート絶縁膜上に形成する工程と、
を有し、
前記ゲート電極の幅は、前記トレンチ型ゲートの形成領域の幅よりも大きくすることにより、前記ゲート電極の両端が、それぞれ、前記選択成長半導体層上を覆うように形成されていることを特徴とする半導体装置の製造方法。 - 前記素子間分離トレンチ内に前記素子分離絶縁膜を埋め込む工程は、前記素子間分離トレンチ内を充填するように前記半導体基板上に前記素子分離絶縁膜を堆積した後に、CMPプロセスによって前記素子分離絶縁膜の表面の研磨を行い、前記絶縁膜パターンの上面の位置と概略同じ高さとなるように、前記素子間分離トレンチ内に前記素子分離絶縁膜を残存させることを特徴とする、請求項1に記載の半導体装置の製造方法。
- 前記半導体基板及び選択成長半導体層がそれぞれシリコン基板及びシリコン層であり、前記絶縁膜パターンがシリコン窒化膜である、請求項1又は2に記載の半導体装置の製造方法。
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JP2006341634A JP4600837B2 (ja) | 2006-12-19 | 2006-12-19 | 半導体装置の製造方法 |
US11/955,968 US7705401B2 (en) | 2006-12-19 | 2007-12-13 | Semiconductor device including a fin-channel recess-gate MISFET |
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JP2006341634A JP4600837B2 (ja) | 2006-12-19 | 2006-12-19 | 半導体装置の製造方法 |
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JP2008153530A JP2008153530A (ja) | 2008-07-03 |
JP4600837B2 true JP4600837B2 (ja) | 2010-12-22 |
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Families Citing this family (11)
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KR100618893B1 (ko) * | 2005-04-14 | 2006-09-01 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
JP2008098553A (ja) * | 2006-10-16 | 2008-04-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2010021328A (ja) * | 2008-07-10 | 2010-01-28 | Elpida Memory Inc | 半導体装置及びその製造方法、並びに、データ処理システム |
US8053322B2 (en) * | 2008-12-29 | 2011-11-08 | Texas Instruments Incorporated | Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom |
JP2011077185A (ja) * | 2009-09-29 | 2011-04-14 | Elpida Memory Inc | 半導体装置の製造方法、半導体装置及びデータ処理システム |
US9057463B2 (en) | 2012-03-26 | 2015-06-16 | Vetco Gray U.K. Limited | Quick disconnect connector for subsea tubular members |
US8927373B2 (en) | 2013-03-13 | 2015-01-06 | Samsung Electronics Co, Ltd. | Methods of fabricating non-planar transistors including current enhancing structures |
US9520494B2 (en) | 2013-09-26 | 2016-12-13 | Intel Corporation | Vertical non-planar semiconductor device for system-on-chip (SoC) applications |
US9653542B2 (en) * | 2013-10-23 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET having isolation structure and method of forming the same |
US10109739B2 (en) * | 2016-04-15 | 2018-10-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor |
JP7274148B2 (ja) | 2017-07-19 | 2023-05-16 | グローバルウェーハズ・ジャパン株式会社 | 三次元構造体の製造方法、縦型トランジスタの製造方法、および縦型トランジスタ用基板 |
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JPS63287064A (ja) * | 1987-05-19 | 1988-11-24 | Fujitsu Ltd | Mis形半導体装置およびその製造方法 |
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- 2006-12-19 JP JP2006341634A patent/JP4600837B2/ja active Active
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- 2007-12-13 US US11/955,968 patent/US7705401B2/en active Active
Patent Citations (7)
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JPS63287064A (ja) * | 1987-05-19 | 1988-11-24 | Fujitsu Ltd | Mis形半導体装置およびその製造方法 |
JPH0629531A (ja) * | 1992-07-09 | 1994-02-04 | Sharp Corp | 半導体装置の製造方法 |
JPH07131007A (ja) * | 1993-11-02 | 1995-05-19 | Tadahiro Omi | 半導体装置 |
JPH10200106A (ja) * | 1997-01-13 | 1998-07-31 | Sony Corp | 半導体装置及びその製造方法 |
JP2008515188A (ja) * | 2004-09-29 | 2008-05-08 | フリースケール セミコンダクター インコーポレイテッド | 歪みチャネル、及びヘテロ接合ソース/ドレインを有する半導体素子を形成する方法 |
JP2006269760A (ja) * | 2005-03-24 | 2006-10-05 | Sony Corp | 半導体装置およびその製造方法 |
JP2006310718A (ja) * | 2005-04-29 | 2006-11-09 | Hynix Semiconductor Inc | メモリ素子のトランジスタ構造及びその製造方法 |
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US20080142881A1 (en) | 2008-06-19 |
JP2008153530A (ja) | 2008-07-03 |
US7705401B2 (en) | 2010-04-27 |
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