JP4587788B2 - 論理回路 - Google Patents
論理回路 Download PDFInfo
- Publication number
- JP4587788B2 JP4587788B2 JP2004339340A JP2004339340A JP4587788B2 JP 4587788 B2 JP4587788 B2 JP 4587788B2 JP 2004339340 A JP2004339340 A JP 2004339340A JP 2004339340 A JP2004339340 A JP 2004339340A JP 4587788 B2 JP4587788 B2 JP 4587788B2
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- JP
- Japan
- Prior art keywords
- input
- terminal
- circuit
- reset
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Description
・2入力排他的論理和回路の一方の入力である信号φ1の変化、
・2入力排他的論理和回路の他方の入力RDの変化、
・2入力排他的論理和回路の両方の入力φ1とRDがともに変化、
のそれぞれの場合で、伝播遅延時間が異なり、このため、スキューが発生する。
NM1〜NM7、NM11、NM12 nMOSトランジスタ
INV インバータ
Claims (4)
- 論理信号をそれぞれ入力とする第1及び第2の入力端子と、
ソースがそれぞれに対応する前記第1及び第2の入力端子に接続され、ゲートが、前記第2及び第1の入力端子に交差接続され、ドレインが一のノード(「共通ノード」という)に共通接続された第1及び第2のMOSトランジスタと、
第1の電源と前記共通ノードとの間に直列形態に接続され、ゲートが前記第1及び第2の入力端子にそれぞれ接続された第3及び第4のMOSトランジスタと、
前記共通ノードに入力端が接続されたインバータと、
前記インバータの電源と前記第1の電源間に並列に接続され、ゲートが前記第1及び第2の入力端子にそれぞれ接続された第5及び第6のMOSトランジスタと、
前記インバータの出力端と第2の電源間に直列に接続され、ゲートが前記第1及び第2の入力端子にそれぞれ接続された第7及び第8のMOSトランジスタと、
を備えている、ことを特徴とする論理回路。 - 前記第3及び第4のMOSトランジスタと前記第5及び第6のMOSトランジスタは、前記第1及び第2のMOSトランジスタ及び前記第7及び第8のMOSトランジスタと逆導電型である、ことを特徴とする請求項1記載の論理回路。
- 前記第1及び第2の入力端子の信号がともに予め定められた論理値のとき、前記第7及び第8のMOSトランジスタがオンし前記出力端子を前記第2の電源に対応する論理レベルとする、ことを特徴とする請求項1記載の論理回路。
- 請求項1乃至3のいずれか一に記載の論理回路を、排他的論理和回路として備えている、ことを特徴とするECC回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004339340A JP4587788B2 (ja) | 2004-11-24 | 2004-11-24 | 論理回路 |
US11/285,285 US7560955B2 (en) | 2004-11-24 | 2005-11-23 | Logic circuit |
CN200510125200.0A CN1783718A (zh) | 2004-11-24 | 2005-11-24 | 逻辑电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004339340A JP4587788B2 (ja) | 2004-11-24 | 2004-11-24 | 論理回路 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010184242A Division JP2010259121A (ja) | 2010-08-19 | 2010-08-19 | 論理回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006148805A JP2006148805A (ja) | 2006-06-08 |
JP4587788B2 true JP4587788B2 (ja) | 2010-11-24 |
Family
ID=36460376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004339340A Expired - Fee Related JP4587788B2 (ja) | 2004-11-24 | 2004-11-24 | 論理回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7560955B2 (ja) |
JP (1) | JP4587788B2 (ja) |
CN (1) | CN1783718A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010259121A (ja) * | 2010-08-19 | 2010-11-11 | Renesas Electronics Corp | 論理回路 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9104214B2 (en) | 2012-08-06 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Voltage providing circuit |
CN112910458B (zh) * | 2019-12-03 | 2024-05-17 | 华润微集成电路(无锡)有限公司 | 一种计数电路及其迟滞电压产生方法 |
CN112269332B (zh) * | 2020-09-29 | 2021-10-22 | 宇龙计算机通信科技(深圳)有限公司 | 微控制器***电路和电子设备 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5746536A (en) * | 1980-09-04 | 1982-03-17 | Matsushita Electric Ind Co Ltd | Gate circuit |
JPS5838033A (ja) * | 1981-08-28 | 1983-03-05 | Toshiba Corp | 排他的論理和回路 |
JPS58215827A (ja) * | 1982-06-09 | 1983-12-15 | Toshiba Corp | 論理回路 |
JPH06224745A (ja) * | 1993-01-22 | 1994-08-12 | Oki Electric Ind Co Ltd | 排他的論理和回路及び排他的否定論理和回路 |
JPH09135163A (ja) * | 1995-11-08 | 1997-05-20 | Nippon Telegr & Teleph Corp <Ntt> | 論理回路 |
JPH10303737A (ja) * | 1997-04-23 | 1998-11-13 | Mitsubishi Electric Corp | 3入力排他的否定論理和回路 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60206222A (ja) | 1984-03-29 | 1985-10-17 | Toshiba Corp | 排他的論理和回路 |
JPH023144A (ja) | 1988-06-15 | 1990-01-08 | Nec Ic Microcomput Syst Ltd | 半導体メモリ |
KR950006352B1 (ko) | 1992-12-31 | 1995-06-14 | 삼성전자주식회사 | 정류성 전송 게이트와 그 응용회로 |
US5523707A (en) | 1995-06-30 | 1996-06-04 | International Business Machines Corporation | Fast, low power exclusive or circuit |
JP2001168707A (ja) | 1999-12-03 | 2001-06-22 | Sony Corp | 論理回路およびそれを用いた全加算器 |
US6724225B2 (en) * | 2001-06-07 | 2004-04-20 | Ibm Corporation | Logic circuit for true and complement signal generator |
US7176746B1 (en) * | 2001-09-27 | 2007-02-13 | Piconetics, Inc. | Low power charge pump method and apparatus |
JP3928937B2 (ja) * | 2002-05-24 | 2007-06-13 | シャープ株式会社 | 半導体集積回路 |
-
2004
- 2004-11-24 JP JP2004339340A patent/JP4587788B2/ja not_active Expired - Fee Related
-
2005
- 2005-11-23 US US11/285,285 patent/US7560955B2/en not_active Expired - Fee Related
- 2005-11-24 CN CN200510125200.0A patent/CN1783718A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5746536A (en) * | 1980-09-04 | 1982-03-17 | Matsushita Electric Ind Co Ltd | Gate circuit |
JPS5838033A (ja) * | 1981-08-28 | 1983-03-05 | Toshiba Corp | 排他的論理和回路 |
JPS58215827A (ja) * | 1982-06-09 | 1983-12-15 | Toshiba Corp | 論理回路 |
JPH06224745A (ja) * | 1993-01-22 | 1994-08-12 | Oki Electric Ind Co Ltd | 排他的論理和回路及び排他的否定論理和回路 |
JPH09135163A (ja) * | 1995-11-08 | 1997-05-20 | Nippon Telegr & Teleph Corp <Ntt> | 論理回路 |
JPH10303737A (ja) * | 1997-04-23 | 1998-11-13 | Mitsubishi Electric Corp | 3入力排他的否定論理和回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010259121A (ja) * | 2010-08-19 | 2010-11-11 | Renesas Electronics Corp | 論理回路 |
Also Published As
Publication number | Publication date |
---|---|
US7560955B2 (en) | 2009-07-14 |
JP2006148805A (ja) | 2006-06-08 |
CN1783718A (zh) | 2006-06-07 |
US20060109029A1 (en) | 2006-05-25 |
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