JP4579027B2 - 負荷駆動回路 - Google Patents
負荷駆動回路 Download PDFInfo
- Publication number
- JP4579027B2 JP4579027B2 JP2005095362A JP2005095362A JP4579027B2 JP 4579027 B2 JP4579027 B2 JP 4579027B2 JP 2005095362 A JP2005095362 A JP 2005095362A JP 2005095362 A JP2005095362 A JP 2005095362A JP 4579027 B2 JP4579027 B2 JP 4579027B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- transistor
- potential
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000007423 decrease Effects 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 4
- 230000005669 field effect Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 15
- 239000003990 capacitor Substances 0.000 description 14
- 101710170230 Antimicrobial peptide 1 Proteins 0.000 description 12
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 description 12
- 230000000630 rising effect Effects 0.000 description 12
- 238000004088 simulation Methods 0.000 description 6
- 101000799554 Homo sapiens Protein AATF Proteins 0.000 description 5
- 102100034180 Protein AATF Human genes 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 101150075317 bfr1 gene Proteins 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- HODRFAVLXIFVTR-RKDXNWHRSA-N tevenel Chemical compound NS(=O)(=O)C1=CC=C([C@@H](O)[C@@H](CO)NC(=O)C(Cl)Cl)C=C1 HODRFAVLXIFVTR-RKDXNWHRSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
- H03F3/3022—CMOS common source output SEPP amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
- H03K17/166—Soft switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0204—Compensation of DC component across the pixels in flat panels
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
- H03F2203/30015—An input signal dependent control signal controls the bias of an output stage in the SEPP
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Amplifiers (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electronic Switches (AREA)
Description
すなわち、高電位側の位相補償回路5についてみると、 トランジスタP1のゲート端子GP1と電源端子VDDとの間には、プルアップ抵抗として機能するpチャンネル型MOS電界効果トランジスタP6(以下、単に、「トランジスタP6」と称する)が接続されている。また、低電位側の位相補償回路6についてみると、トランジスタN1のゲート端子GN1とグランド端子GNDとの間には、プルダウン抵抗として機能するnチャンネル型MOS電界効果トランジスタN6(以下、単に、「トランジスタN6」と称する)が接続されている。一方、前段増幅回路としては、非反転型のバッファ増幅回路BFR1が採用されている。
P1 pチャンネル型MOS電界効果トランジスタ(出力素子)
N1 pチャンネル型MOS電界効果トランジスタ(出力素子)
1,3,5,7,9,11,13 立ち上がり時の位相補償回路
2,4,6,8,10,1214 立ち下がり時の位相補償回路
OUT 出力端子
IN 入力端子
GP1 ゲート端子(出力素子の制御入力端子)
GN1 ゲート端子(出力素子の制御入力端子)
AMP1 第1の反転型増幅回路
AMP2 第2の反転型増幅回路
AMP3 カレントミラー形式の反転型作動増幅回路
AMP4 カレントミラー形式の反転型作動増幅回路
CNT 制御入力端子
BFR1 非反転型のバッファ増幅回路
BFR2 非反転型のバッファ増幅回路(イネーブル端子付)
Claims (13)
- 負荷が接続されるべき出力端子と、
入力信号が与えられるべき入力端子と、
負荷を駆動するための出力素子含む終段増幅回路と、
入力信号に応じて終段増幅回路に含まれる出力素子を駆動するための前段増幅回路と、
入出力信号波形間の位相特性を改善するための位相補償回路とを含み、
入力端子に与えられる入力信号に応じて、非反転形式の出力信号が出力端子に現れるようにした負荷駆動回路であって、
前記位相補償回路が、
終段増幅回路の出力素子の制御入力端子と当該負荷駆動回路の出力端子との間に非直線抵抗素子とスイッチ素子との直列回路を挿入することにより構成されており、
前記非直線抵抗素子は、印加電圧値が増加するに連れて抵抗値が減少し、かつ印加電圧値が減少するに連れて抵抗値が増加する非直線特性を有するものであり、
前記スイッチ素子は、その出力素子が終段増幅回路内において、高電位側又は低電位側のいずれに配置されているかに対応して、入力信号の高電位期間又は低電位期間に限り選択的にオン状態となるようにスイッチング制御される、
ことを特徴とする負荷駆動回路。 - 前記非直線抵抗素子が、制御入力端子と一対の主端子とを有すると共に、この制御入力端子の電位が当該負荷駆動回路の出力端子の電位に追従するように回路接続されたトランジスタ素子である、ことを特徴とする請求項1に記載の負荷駆動回路。
- 前記終段増幅回路が、相補接続された一対の出力素子により構成され、前記直列回路が高電位側出力素子の制御入力端子と出力端子との間、及び、低電位側出力素子の制御入力端子と出力端子との間、のそれぞれに挿入されている、ことを特徴とする請求項1又は2に記載の負荷駆動回路。
- 前記終段増幅回路が、高電位側出力素子と負荷素子、又は低電位側出力素子と負荷素子とを、一対の電源端子間に直列に接続し、それらの接続点から出力信号を取り出すように構成され、前記直列回路が高電位側出力素子の制御入力端子と出力端子との間、又は、低電位側出力素子の制御入力端子と出力端子との間、のいずれかに挿入されている、ことを特徴とする請求項1又は2に記載の負荷駆動回路。
- 前記負荷素子が、1若しくは2以上のトランジスタ素子で構成された定電流源である、ことを特徴とする請求項4に記載の負荷駆動回路。
- 前記前段増幅回路が、入力端子と出力端子との電位差を増幅して終段増幅回路の出力素子に与える反転型増幅回路である、ことを特徴とする請求項1〜5に記載の負荷駆動回路。
- 前記反転型増幅回路が、共通電流路に定電流源を挿入してなるカレントミラー型の作動増幅回路である、ことを特徴とする請求項6に記載の負荷駆動回路。
- 前記前段増幅回路が、入力信号を増幅する非反転型のバッファ回路であり、かつ出力素子の制御入力端子と電源端子との間にはプル抵抗素子が挿入されている、ことを特徴とする請求項1〜5のいずれかに記載の負荷駆動回路。
- 非反転型のバッファ回路が、高電位出力ステートと低電位出力ステートとハイインピーダンスステートとをとりうる3ステート型のバッファ回路である、ことを特徴とする請求項8に記載の負荷駆動回路。
- 前記プル抵抗素子が、ポリ抵抗である、ことを特徴とする請求項8又は9に記載の負荷駆動回路。
- 前記プル抵抗素子が、制御入力端子と一対の主端子とを有すると共に、この制御入力端子を一対の主端子の一方へ導通させることにより抵抗素子として機能させたトランジスタ素子である、ことを特徴とする請求項6又は7に記載の負荷駆動回路。
- 前記プル抵抗素子が、1又は2以上のトランジスタ素子で構成された定電流源である、ことを特徴とする請求項8又は9に記載の負荷駆動回路。
- 制御入力端子と、制御入力端子に与えられる制御入力信号に応じて、前記前段増幅回路および/または前記位相補償回路の動作を能動化/不能化するための回路とをさらに有することを特徴とする請求項1〜12のいずれかに記載の負荷駆動回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005095362A JP4579027B2 (ja) | 2005-03-29 | 2005-03-29 | 負荷駆動回路 |
US11/886,999 US7746126B2 (en) | 2005-03-29 | 2006-03-07 | Load driving circuit |
PCT/JP2006/304393 WO2006103889A1 (ja) | 2005-03-29 | 2006-03-07 | 負荷駆動回路 |
CN2006800106508A CN101151654B (zh) | 2005-03-29 | 2006-03-07 | 负载驱动电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005095362A JP4579027B2 (ja) | 2005-03-29 | 2005-03-29 | 負荷駆動回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006279512A JP2006279512A (ja) | 2006-10-12 |
JP4579027B2 true JP4579027B2 (ja) | 2010-11-10 |
Family
ID=37053155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005095362A Active JP4579027B2 (ja) | 2005-03-29 | 2005-03-29 | 負荷駆動回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7746126B2 (ja) |
JP (1) | JP4579027B2 (ja) |
CN (1) | CN101151654B (ja) |
WO (1) | WO2006103889A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4397401B2 (ja) | 2007-03-28 | 2010-01-13 | Okiセミコンダクタ株式会社 | オペアンプ及びそれが用いられる液晶表示装置の駆動回路 |
BRPI0914552A2 (pt) * | 2008-08-11 | 2015-12-15 | Sharp Kk | circuito de acionamento de carga capacitiva e dispositivo de exibição incluindo o mesmo |
US7924066B2 (en) * | 2009-03-25 | 2011-04-12 | Fairchild Semiconductor Corporation | Low speed, load independent, slew rate controlled output buffer with no DC power consumption |
JP5457220B2 (ja) | 2010-02-18 | 2014-04-02 | ルネサスエレクトロニクス株式会社 | 出力回路及びデータドライバ及び表示装置 |
TWI477078B (zh) * | 2012-10-17 | 2015-03-11 | Ind Tech Res Inst | 電容性負載驅動電路以及脈衝激發裝置 |
DE102014119479B4 (de) * | 2014-12-23 | 2023-11-16 | Intel Corporation | Ein Push-Pull-Treiber, ein Sender, ein Empfänger, ein Sendeempfänger, eine integrierte Schaltung, ein Verfahren zum Erzeugen eines Signals an einem Ausgang |
JP6719233B2 (ja) * | 2016-03-07 | 2020-07-08 | エイブリック株式会社 | 出力回路 |
JP6195393B1 (ja) | 2016-03-23 | 2017-09-13 | ウィンボンド エレクトロニクス コーポレーション | 出力回路 |
CN110212880B (zh) * | 2019-07-04 | 2024-03-22 | 深圳贝特莱电子科技股份有限公司 | 一种电荷放大器电路及其时序控制方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001022328A (ja) * | 1999-07-09 | 2001-01-26 | Hitachi Ltd | 液晶表示装置 |
JP2001285050A (ja) * | 2000-03-30 | 2001-10-12 | Mitsubishi Electric Corp | 出力バッファ回路 |
JP2005073155A (ja) * | 2003-08-27 | 2005-03-17 | Matsushita Electric Ind Co Ltd | 位相補償回路 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5628041B2 (ja) | 1972-10-07 | 1981-06-29 | ||
JPS6035290Y2 (ja) * | 1979-07-24 | 1985-10-21 | ヤマハ株式会社 | フイードフオワード同相アンプ |
JPS6038203B2 (ja) | 1979-07-25 | 1985-08-30 | 三菱重工業株式会社 | トツプキヤツプのクランプ装置 |
JPH0652864B2 (ja) | 1987-11-17 | 1994-07-06 | 日本電気株式会社 | 出力回路 |
JP2912512B2 (ja) * | 1992-12-07 | 1999-06-28 | 旭化成マイクロシステム株式会社 | 増幅器の位相補償回路 |
JPH07106871A (ja) * | 1993-10-07 | 1995-04-21 | Kanebo Ltd | 演算増幅回路 |
JPH08288825A (ja) | 1995-04-17 | 1996-11-01 | Oki Electric Ind Co Ltd | 出力回路 |
JP2990082B2 (ja) * | 1996-12-26 | 1999-12-13 | 日本電気アイシーマイコンシステム株式会社 | 液晶駆動回路及びその制御方法 |
JPH11249625A (ja) * | 1998-03-04 | 1999-09-17 | Matsushita Electric Ind Co Ltd | 液晶駆動装置 |
JP3228411B2 (ja) * | 1998-03-16 | 2001-11-12 | 日本電気株式会社 | 液晶表示装置の駆動回路 |
JP3846293B2 (ja) * | 2000-12-28 | 2006-11-15 | 日本電気株式会社 | 帰還型増幅回路及び駆動回路 |
TWI241064B (en) * | 2005-01-13 | 2005-10-01 | Denmos Technology Inc | Push-pull buffer amplifier and source driver |
US7495483B2 (en) * | 2005-06-30 | 2009-02-24 | Stmicroelectronics Pvt. Ltd. | Input buffer for CMOS integrated circuits |
TWI291806B (en) * | 2005-12-19 | 2007-12-21 | Denmos Technology Inc | Buffer for source driver |
JP4921106B2 (ja) * | 2006-10-20 | 2012-04-25 | キヤノン株式会社 | バッファ回路 |
-
2005
- 2005-03-29 JP JP2005095362A patent/JP4579027B2/ja active Active
-
2006
- 2006-03-07 US US11/886,999 patent/US7746126B2/en active Active
- 2006-03-07 WO PCT/JP2006/304393 patent/WO2006103889A1/ja active Application Filing
- 2006-03-07 CN CN2006800106508A patent/CN101151654B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001022328A (ja) * | 1999-07-09 | 2001-01-26 | Hitachi Ltd | 液晶表示装置 |
JP2001285050A (ja) * | 2000-03-30 | 2001-10-12 | Mitsubishi Electric Corp | 出力バッファ回路 |
JP2005073155A (ja) * | 2003-08-27 | 2005-03-17 | Matsushita Electric Ind Co Ltd | 位相補償回路 |
Also Published As
Publication number | Publication date |
---|---|
US20090212828A1 (en) | 2009-08-27 |
US7746126B2 (en) | 2010-06-29 |
WO2006103889A1 (ja) | 2006-10-05 |
CN101151654B (zh) | 2010-04-07 |
CN101151654A (zh) | 2008-03-26 |
JP2006279512A (ja) | 2006-10-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4579027B2 (ja) | 負荷駆動回路 | |
JP5048081B2 (ja) | バッファおよび表示装置 | |
US8044950B2 (en) | Driver circuit usable for display panel | |
US6459322B1 (en) | Level adjustment circuit and data output circuit thereof | |
JP4103468B2 (ja) | 差動回路と増幅回路及び該増幅回路を用いた表示装置 | |
US9030248B2 (en) | Level shifter with output spike reduction | |
WO2006117860A1 (ja) | 差動駆動回路およびそれを内蔵する電子機器 | |
US8604844B2 (en) | Output circuit | |
US20040160262A1 (en) | Level shifter having low peak current | |
US7446576B2 (en) | Output driver with slew rate control | |
JP5581263B2 (ja) | バッファ回路 | |
JPH07263971A (ja) | 外部接続された出力パワーデバイスを有する集積増幅器用出力段 | |
JP2022107053A (ja) | レベルシフト回路 | |
US7659748B2 (en) | Electronic device and integrated circuit | |
WO2012042683A1 (ja) | レベルシフト回路 | |
US20100090726A1 (en) | Data receiver of semiconductor integrated circuit | |
US8456211B2 (en) | Slew rate control circuit and method thereof and slew rate control device | |
JP2004128162A (ja) | 半導体装置 | |
JP5199941B2 (ja) | 電圧増幅回路 | |
JP4301404B2 (ja) | 出力バッファ回路 | |
US7826275B2 (en) | Memory circuit with high reading speed and low switching noise | |
JP3385100B2 (ja) | 演算増幅器 | |
JP2930227B2 (ja) | 半導体集積回路の出力バッファ回路 | |
US5773992A (en) | Output buffer circuit capable of supressing ringing | |
US9525349B1 (en) | Power supply decoupling circuit with decoupling capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080328 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100728 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100825 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130903 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4579027 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |