JP4549287B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP4549287B2 JP4549287B2 JP2005353247A JP2005353247A JP4549287B2 JP 4549287 B2 JP4549287 B2 JP 4549287B2 JP 2005353247 A JP2005353247 A JP 2005353247A JP 2005353247 A JP2005353247 A JP 2005353247A JP 4549287 B2 JP4549287 B2 JP 4549287B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor
- plate
- base plate
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 134
- 229910052751 metal Inorganic materials 0.000 claims description 149
- 239000002184 metal Substances 0.000 claims description 149
- 239000000758 substrate Substances 0.000 claims description 119
- 230000002093 peripheral effect Effects 0.000 claims description 39
- 229910000679 solder Inorganic materials 0.000 claims description 38
- 230000008602 contraction Effects 0.000 description 7
- 238000005304 joining Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
金属パターンが主面及び裏面に設けられた複数の絶縁基板と上記主面の金属パターンに接合された半導体素子とからなる半導体実装基板が、単一の金属ベース板上に接合された半導体モジュールであって、
上記半導体実装基板における上記複数の絶縁基板は、互いに近接して配置され、上記裏面の金属パターンが単一の金属薄板で共通化されてなり、
上記半導体実装基板と上記金属ベース板との接合は、上記金属薄板を介してはんだ部材を用いて行われ、
上記絶縁基板と金属薄板の積層方向から見たとき、上記金属薄板の周縁が対向する上記絶縁基板の周縁より外側に位置することを特徴とする。
本発明の一実施形態に係る、全体が符号10で示される半導体モジュールを図1、2に示す。図2は、図1における一点鎖線で示される半導体モジュール10の断面をA方向から見た図である。
本実施の形態が上述の実施形態と異なる点は、半導体実装基板における絶縁基板、および絶縁基板と金属薄板との一部関係が異なる点である。
Claims (3)
- 金属パターンが主面及び裏面に設けられた複数の絶縁基板と上記主面の金属パターンに接合された半導体素子とからなる半導体実装基板が、単一の金属ベース板上に接合された半導体モジュールであって、
上記半導体実装基板における上記複数の絶縁基板は、互いに近接して配置され、上記裏面の金属パターンが単一の金属薄板で共通化されてなり、
上記半導体実装基板と上記金属ベース板との接合は、上記金属薄板を介してはんだ部材を用いて行われ、
上記絶縁基板と金属薄板の積層方向から見たとき、上記金属薄板の周縁が対向する上記絶縁基板の周縁より外側に位置することを特徴とする半導体モジュール。 - 金属パターンが主面及び裏面に形成された複数の絶縁基板と上記主面の金属パターンに接合された半導体素子とからなる半導体実装基板が、単一の金属ベース板上に接合された半導体モジュールであって、
上記半導体実装基板における上記複数の絶縁基板は、互いに近接して配置され、上記裏面の金属パターンが単一の金属薄板で共通化されてなり、
上記半導体実装基板と上記金属ベース板との接合は、上記金属薄板を介してはんだ部材を用いて行われ、
上記絶縁基板と金属薄板の積層方向から見たとき、上記半導体素子近傍における上記絶縁基板の周縁の部分において、上記金属薄板の周縁が絶縁基板の周縁部分より外側に位置することを特徴とする半導体モジュール。 - 複数の絶縁基板の間にあって、絶縁基板と接合されていない金属薄板の部分に貫通孔が形成されていることを特徴とする請求項1または2のいずれかに記載の半導体モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005353247A JP4549287B2 (ja) | 2005-12-07 | 2005-12-07 | 半導体モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005353247A JP4549287B2 (ja) | 2005-12-07 | 2005-12-07 | 半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007158156A JP2007158156A (ja) | 2007-06-21 |
JP4549287B2 true JP4549287B2 (ja) | 2010-09-22 |
Family
ID=38242085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005353247A Active JP4549287B2 (ja) | 2005-12-07 | 2005-12-07 | 半導体モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4549287B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130308276A1 (en) * | 2011-01-07 | 2013-11-21 | Fuji Electric Co., Ltd | Semiconductor device and manufacturing method for same |
WO2023218680A1 (ja) * | 2022-05-11 | 2023-11-16 | 三菱電機株式会社 | 半導体装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56116631A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor device |
JP2000049425A (ja) * | 1998-07-27 | 2000-02-18 | Denki Kagaku Kogyo Kk | セラミックス回路基板とその製造方法、それを用いたパワーモジュール |
JP2000101203A (ja) * | 1998-09-28 | 2000-04-07 | Denki Kagaku Kogyo Kk | セラミックス回路基板とそれを用いたパワーモジュール |
JP2003133662A (ja) * | 2001-10-29 | 2003-05-09 | Kyocera Corp | セラミック回路基板 |
JP2004140199A (ja) * | 2002-10-18 | 2004-05-13 | Denki Kagaku Kogyo Kk | モジュール構造体とその製造方法 |
JP2005109374A (ja) * | 2003-10-02 | 2005-04-21 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
JP2005150309A (ja) * | 2003-11-13 | 2005-06-09 | Toyota Industries Corp | 半導体装置 |
-
2005
- 2005-12-07 JP JP2005353247A patent/JP4549287B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56116631A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor device |
JP2000049425A (ja) * | 1998-07-27 | 2000-02-18 | Denki Kagaku Kogyo Kk | セラミックス回路基板とその製造方法、それを用いたパワーモジュール |
JP2000101203A (ja) * | 1998-09-28 | 2000-04-07 | Denki Kagaku Kogyo Kk | セラミックス回路基板とそれを用いたパワーモジュール |
JP2003133662A (ja) * | 2001-10-29 | 2003-05-09 | Kyocera Corp | セラミック回路基板 |
JP2004140199A (ja) * | 2002-10-18 | 2004-05-13 | Denki Kagaku Kogyo Kk | モジュール構造体とその製造方法 |
JP2005109374A (ja) * | 2003-10-02 | 2005-04-21 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
JP2005150309A (ja) * | 2003-11-13 | 2005-06-09 | Toyota Industries Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2007158156A (ja) | 2007-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9418909B1 (en) | Stacked silicon package assembly having enhanced lid adhesion | |
WO2013118478A1 (ja) | 半導体装置 | |
US20170005030A1 (en) | Flat No-Leads Package With Improved Contact Pins | |
JPH09312357A (ja) | 半導体装置 | |
JP4627775B2 (ja) | 半導体装置の製造方法。 | |
JP2008277654A (ja) | ヒートシンク付パワーモジュール用基板及びパワーモジュール | |
JP2015076604A (ja) | 半導体パッケージ用フレーム補強材およびこれを用いた半導体パッケージの製造方法 | |
JP2007053349A (ja) | 絶縁基板および絶縁基板の製造方法並びにパワーモジュール用基板およびパワーモジュール | |
JP6165025B2 (ja) | 半導体モジュール | |
JP4549287B2 (ja) | 半導体モジュール | |
JP5217246B2 (ja) | パワーモジュール用ユニットの製造方法 | |
JP2016167502A (ja) | ヒートシンク付パワーモジュール用基板及びパワーモジュール | |
JP2018010929A (ja) | 半導体モジュール、電力変換装置 | |
US20180233459A1 (en) | Module, module manufacturing method, and package | |
JP4556732B2 (ja) | 半導体装置及びその製造方法 | |
JP2007184424A (ja) | 半導体装置 | |
JP2007053148A (ja) | 半導体モジュール | |
US11676882B2 (en) | Method of manufacturing power module substrate board and ceramic-copper bonded body | |
JP2018082069A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2998838B2 (ja) | 半導体装置 | |
JP2009076813A (ja) | 半導体装置 | |
JPH11214576A (ja) | 半導体チップ搭載用パッケージ | |
JP6320347B2 (ja) | 半導体装置 | |
JP4238864B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5268994B2 (ja) | 半導体モジュールとその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071127 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100408 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100413 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100629 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100706 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4549287 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130716 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |