CN105590920B - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN105590920B
CN105590920B CN201510767545.XA CN201510767545A CN105590920B CN 105590920 B CN105590920 B CN 105590920B CN 201510767545 A CN201510767545 A CN 201510767545A CN 105590920 B CN105590920 B CN 105590920B
Authority
CN
China
Prior art keywords
package
semiconductor package
core substrate
layer
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510767545.XA
Other languages
English (en)
Other versions
CN105590920A (zh
Inventor
柳盛旭
金东先
徐玄锡
李知行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of CN105590920A publication Critical patent/CN105590920A/zh
Application granted granted Critical
Publication of CN105590920B publication Critical patent/CN105590920B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

提供了一种半导体封装，包括：上封装，所述上封装上安装有元件，并且所述上封装包括由金属焊盘部分固定的金属柱；以及下封装，所述下封装上安装有元件，并且所述下封装连接到所述金属柱上。

Description

半导体封装
技术领域
本发明的实施例涉及半导体封装。
背景技术
随着半导体技术和用户需求的发展，实施了电子设备的尺寸微型化和重量轻量化。因此，出现了用于将同种或不同种半导体芯片实施为单个单元封装的多芯片封装技术。与将单个的半导体芯片实施为封装的封装方法相比，多芯片封装方法有效地减小封装尺寸或重量以贴装半导体芯片。具体地讲，多芯片封装普遍应用于要求微型化和减重的便携式通信终端等。
在各种类型的多芯片封装中，两个或更多个封装彼此堆叠的堆叠类型的多芯片封装被称为层叠封装(以下称为“PoP”)。随着半导体封装技术的发展以及半导体封装的高容量、减薄和微型化的改进，层压芯片的数量增加了。
在常规的层叠封装方法中，两个封装通过焊料球印刷和回流焊接工艺连接上，或者首先模制下封装，并且模制部分经过激光钻孔工艺使得在下封装的PoP焊盘中形成通孔(即，穿塑孔方法，Through Molded Via Method)，并且焊料球印制在通孔中，从而使用回流焊接工艺连接下封装和贴装有存储晶模的上封装。
为了实现高度集成度且高性能的层叠封装产品，增加了安装的裸片(die)数量或者尝试贴装无源元件。为此目的，要求增宽封装之间的距离。
然而，根据常规技术的半导体封装存在以下问题：当增加焊料球的尺寸或高度以增宽半导体封装之间的距离时，焊料球开裂或发生损毁。
发明内容
本发明考虑到上述问题，并且本发明的实施例的一个方面提供了一种半导体封装，所述半导体封装通过增加上封装与下封装之间的距离并且增加贴装芯片的数量来实现高密度，并且能够实施上封装和下封装的出色的接合可靠性。
本发明的实施例的另一个方面提供了一种半导体封装，所述半导体封装被配置成金属柱固定在上封装上使得可以简化生产工艺并且可以减少生产时间和成本。
根据本发明的实施例的一个方面，一种半导体封装可以包括：其上装有元件的上封装，所述上封装包括由金属焊盘部分固定的金属柱；以及其上装有元件的下封装，并且所述下封装连接到金属柱上。
所述金属柱可以进一步包括在所述金属柱与所述下封装之间的连接表面上由金属材料制成的焊料层。
所述焊料层可以接合在所述下封装的电路图案上。
所述焊料层可以由Sn和Cu的合金材料或Sn和Ag的合金材料制成。
所述焊料层可以形成在所述金属柱的顶面上。
所述焊料层可以形成为包围所述金属柱。
所述焊料层可以形成在所述金属柱的顶面和侧面上。
所述金属柱可以由Cu材料制成。
所述上封装可以包括芯部基板以及形成在芯部基板的背对的表面上的绝缘层。
所述金属焊盘部分可以形成在所述芯部基板的背对的表面的每个表面上。
附图说明
附图用于进一步理解本发明，并且并入且构成本说明书的一部分。附图与本说明书一起示出了本发明的示例性实施例，并且起到解释本发明的原理的作用。图中：
图1是示出了根据本发明的实施例的半导体封装的横截面图；
图2至图3是图示了用于说明根据本发明的实施例的半导体封装的金属柱的视图；
图4至图5是图示了用于说明根据本发明的另一个实施例的半导体封装的金属柱的视图；并且
图6至图13是图示了用于说明根据本发明的实施例的半导体封装的制造方法的视图。
具体实施方式
以下将参照附图更完整地描述根据本发明的实施例。然而，本发明能够以不同的方式来实施并且不应当被理解为限于本文所述实施例。在以下描述中，要注意，当常规元件的功能以及与本发明有关的元件的详细描述会使本发明的要旨模糊时，将会省略这些元件的详细描述。另外，应当理解，附图所示的元件的形状和大小可以被夸张地图示以便容易理解对本发明的结构的描述，并且不应当理解成元件的形状和尺寸是指实际应用的形状和尺寸。
图1是示出了根据本发明的实施例的半导体封装的横截面图。
参见图1，根据本发明的实施例的半导体封装可以被配置成POP(层叠封装)形式的封装，其中上封装400层叠在下封装300上，使得上、下封装可以彼此电连接。
半导体封装包括下封装300、上封装400和金属柱510。
下封装300被配置成使得至少一个下元件370贴装在下封装基板310上。同时，下元件370可以由半导体构成。
上封装400被配置成使得至少一个上元件430贴装在上封装基板401上。同时，上元件430可以由半导体构成。
此时，下封装基板310和上封装基板410的至少一个可以包括印刷电路板(PCB)。
举例来说，下封装300可以包括下封装基板310以及贴装在下封装基板上的下元件370。当形成多个下元件370时，通过在它们之间插设绝缘材料层而堆叠下元件。
可以在下封装基板310的底面上贴装焊料球形式的外部端子350，该外部端子将半导体封装电连接到外部设备上。
类似地，上封装400可以包括上封装基板410以及贴装在上封装基板410的顶面上的上元件430。当上元件430包括多个时，通过它们之间插设绝缘材料层可以堆叠上元件。
上元件430和上封装基板410可以通过多个接合线442彼此电连接上。
金属柱510被包括在具有上述构造的上封装400中，并且经由金属焊盘固定在上封装基板410上。金属柱510可以包括Cu材料。
此时，焊料层520形成在金属柱510的表面上。
也就是说，焊料层520形成在金属柱510与下封装300之间的连接表面上以便粘附在下封装300的电路图案上。
根据本发明的实施例，焊料层520可以是由Sn和Cu的合金材料或Sn和Ag的合金材料制成的，即，具有230℃至250℃熔点的高熔点焊接材料。金属柱510可以是由Cu材料制成的。
当使用常规的通用焊接材料时，通用焊接材料的熔点为210℃至220℃。然而，如同在本发明的实施例中，当焊料层520是由熔点为230℃至250℃的高熔点焊接材料制成的时候，接合稳定性很出色，并且因此在层压下封装300时，可以确保稳定的工艺成品率。
当使用由这种高熔点焊接材料制成的焊料层520时，可以确保在执行与下封装300的接合时稳定的工艺成品率，并且通过增大上封装400与下封装300之间的距离，可以实现半导体芯片的高密度层压，使得可以形成具有改善的可靠性和稳定性的半导体封装。
此外，可以进一步在金属柱510的表面上形成包括Au和Ni的至少一种材料的表面处理层。
如同根据本发明的实施例，当表面处理层进一步形成在金属柱510的表面上时，可以提高与下封装300的接合可靠性，并且可以确保在层压下封装300时的稳定的工艺成品率，并且与此同时，因为防止了金属柱510氧化，可以确保半导体封装的稳定性。
图2至图3是图示了用于说明根据本发明的实施例的半导体封装的金属柱的视图；图4至图5是图示了用于说明根据本发明的另一个实施例的半导体封装的金属柱的视图。
如图2所示，根据本发明的实施例的半导体封装的金属柱510布置在上封装基板410的底面上。
具体地讲，如图3所示，金属柱510形成在焊盘部分501上并且固定在上封装基板410上。
另外，如图4和图5所示，焊料层520可以进一步形成在金属柱510上。
具体地讲，如图4所示，焊料层520可以形成在金属柱510的顶面上，或者如图5所示，焊料层520可以形成为包围金属柱510。
此时，在图5的实施例中，焊料层520可以形成为覆盖金属柱510的顶面和侧面。
上述构造的焊料层520接合到下封装的电路图案上。
在图4所示的实施例中，焊料层通过使用电镀方法形成在金属柱510的顶面上。如此，当焊料层520通过使用电镀方法形成在金属柱510的顶面上时，由于在组装过程中不需要使用单独的焊料球或焊膏，所以简化了工序。
此外，在图5的实施例中，由于焊料层520形成为覆盖金属柱510，所以不需要使用单独的焊料球或焊膏。因此，可以简化组装过程。另外，由于金属柱510布置在焊料层520中，所以构成焊料层520的焊料的柔软特性得到补偿使得焊料层可以形成为具有更高的高度。
此外，在图5的实施例中，由于焊料层520形成为覆盖金属柱510的顶面和侧面，所以可以增加与下封装的表面接合可靠性。
同时，金属柱510可以包含Cu材料，并且焊料层520可以由Sn和Cu的合金材料或Sn和Ag的合金材料制成。
图6至图13是图示了用于说明根据本发明的实施例的半导体封装的制造方法的视图；
如图6所示，绝缘层412、413形成在芯部基板411上。芯部基板411上形成有焊盘部分501、502。
然后，如图7所示，焊盘部分501、502暴露到其中的开口形成在绝缘层412、413上。
然后，如图8所示，用于形成金属柱的金属种子层503形成在布置在焊盘部分501、502的绝缘层413上。
然后，如图9所示，在其上形成光致抗蚀剂层600，并且如图10所示，在光致抗蚀剂层600上形成开口。
然后，如图11所示，用金属材料填充形成在绝缘层413和光致抗蚀剂层600中的开口。此时，可以在填充有金属材料的开口的表面上进一步形成表面处理层。
然后，如图12所示，去除光致抗蚀剂层600，并且如图13所示，去除金属晶种层503，从而完成金属柱510。
如先前所述，在本发明的详细描述中，已经描述了本发明的详细的示例性实施例，明显的是，本领域的技术人员可以在不脱离本发明的精神和范围的情况下进行修改和变型。因此，应当理解的是，前述是为了说明本发明并且不应当被理解成局限于公开的特定实施例，并且所公开的实施例以及其他实施例的修改旨在包括在所附权利要求书及其等同形式的范围内。

Claims (8)

1.一种半导体封装，包括：
下封装；以及
上封装，该上封装连接在所述下封装上，
其中，所述上封装包括：
第一芯部基板；
焊盘部分，设置在所述第一芯部基板的下表面上；
最下绝缘层，设置在所述第一芯部基板的所述下表面上，并具有露出所述焊盘部分的下表面的第一开口；
金属柱，设置在所述焊盘部分的所述下表面上，并向下突出到所述最下绝缘层的下表面之外；以及
焊料层，一体地设置在所述金属柱的下表面以及所述金属柱的侧面上，
其中，所述下封装包括：
第二芯部基板；
电路图案，设置在所述第二芯部基板的上表面上，并连接到所述焊料层；
最上绝缘层，设置在所述第二芯部基板的所述上表面，并具有露出所述电路图案的上表面的第二开口，
其中，所述焊料层的一部分设置在所述最上绝缘层的所述第二开口中，
其中，所述焊料层的下表面直接接触由所述最上绝缘层的所述第二开口露出的所述电路图案的所述上表面，
其中，所述焊料层的所述下表面与所述最上绝缘层的下表面在同一平面内，
其中，所述焊料层的所述下表面比所述最上绝缘层的上表面和所述金属柱的下表面处于较低水平的位置，
其中，所述焊料层的上表面比所述最上绝缘层的所述上表面和所述金属柱的下表面处于较高水平的位置，
其中，所述焊料层的所述上表面比所述金属柱的上表面处于较低水平的位置，
其中，所述焊料层由熔点为230℃至250℃的高熔点焊接材料形成，
其中，所述金属柱由铜材料形成。
2.根据权利要求1所述的半导体封装，其中所述焊料层由Sn和Cu的合金材料或者Sn和Ag的合金材料制成。
3.根据权利要求1所述的半导体封装，其中所述上封装还包括：在所述第一芯部基板上的上元件。
4.根据权利要求3所述的半导体封装，进一步包括连接所述上元件和所述第一芯部基板的接合线。
5.根据权利要求1所述的半导体封装，其中所述下封装还包括：在所述第二芯部基板上的下元件。
6.根据权利要求5所述的半导体封装，进一步包括外部端子，所述外部端子形成在所述第二芯部基板的底面上并且将所述半导体封装电连接到外部设备。
7.根据权利要求1所述的半导体封装，进一步包括形成在所述金属柱的表面上的表面处理层。
8.根据权利要求7所述的半导体封装，其中所述表面处理层包含Au或Ni。
CN201510767545.XA 2014-11-11 2015-11-11 半导体封装 Active CN105590920B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020140156347A KR102270283B1 (ko) 2014-11-11 2014-11-11 반도체 패키지
KR10-2014-0156347 2014-11-11

Publications (2)

Publication Number Publication Date
CN105590920A CN105590920A (zh) 2016-05-18
CN105590920B true CN105590920B (zh) 2020-03-10

Family

ID=55912861

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510767545.XA Active CN105590920B (zh) 2014-11-11 2015-11-11 半导体封装

Country Status (3)

Country Link
US (1) US9589878B2 (zh)
KR (2) KR102270283B1 (zh)
CN (1) CN105590920B (zh)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811472A (zh) * 2012-11-05 2014-05-21 三星电子株式会社 半导体封装件和制造半导体封装件的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP2007287906A (ja) * 2006-04-17 2007-11-01 Elpida Memory Inc 電極と電極の製造方法、及びこの電極を備えた半導体装置
JP5003260B2 (ja) * 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
KR20100066821A (ko) * 2008-12-10 2010-06-18 삼성전자주식회사 패키지 온 패키지 및 그의 제조 방법
KR20100075204A (ko) * 2008-12-24 2010-07-02 삼성전자주식회사 스터드 범프를 이용한 적층형 반도체 패키지, 반도체 패키지 모듈, 및 그 제조방법
KR20100121231A (ko) * 2009-05-08 2010-11-17 삼성전자주식회사 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package
KR20110085481A (ko) * 2010-01-20 2011-07-27 삼성전자주식회사 적층 반도체 패키지
CN101778542B (zh) * 2010-01-22 2012-03-21 深圳市牧泰莱电路技术有限公司 一种带铜柱的pcb板件的制造方法
US8482111B2 (en) * 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
JP5462777B2 (ja) * 2010-12-09 2014-04-02 日本特殊陶業株式会社 多層配線基板の製造方法
US8853558B2 (en) * 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
US8803333B2 (en) * 2012-05-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
CN103311207A (zh) * 2013-05-29 2013-09-18 华为技术有限公司 堆叠式封装结构

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811472A (zh) * 2012-11-05 2014-05-21 三星电子株式会社 半导体封装件和制造半导体封装件的方法

Also Published As

Publication number Publication date
KR102270283B1 (ko) 2021-06-29
US20160133604A1 (en) 2016-05-12
KR20210084370A (ko) 2021-07-07
US9589878B2 (en) 2017-03-07
KR102472045B1 (ko) 2022-11-29
CN105590920A (zh) 2016-05-18
KR20160056212A (ko) 2016-05-19

Similar Documents

Publication Publication Date Title
KR101011863B1 (ko) 반도체 패키지 및 그 제조 방법
US7687899B1 (en) Dual laminate package structure with embedded elements
US7511371B2 (en) Multiple die integrated circuit package
US7352058B2 (en) Methods for a multiple die integrated circuit package
US7829990B1 (en) Stackable semiconductor package including laminate interposer
US7706148B2 (en) Stack structure of circuit boards embedded with semiconductor chips
TWI599009B (zh) 半導體晶片封裝元件，半導體模組，半導體封裝元件之製造方法及半導體模組之製造方法
JP2009506570A (ja) マイクロ電子ダイ用の配線基板、そのような基板にビアを形成する方法、およびマイクロ電子デバイスをパッケージ化する方法
KR20080007893A (ko) 적층형 반도체 패키지 및 그의 제조방법
US20190363073A1 (en) Package-on-package type semiconductor package and method for manufacturing the same
US20100123236A1 (en) Semiconductor package having adhesive layer and method of manufacturing the same
US9252112B2 (en) Semiconductor package
KR20160093248A (ko) 반도체 패키지 및 제조 방법
KR101394647B1 (ko) 반도체 패키지 및 그 제조방법
JP2006202997A (ja) 半導体装置およびその製造方法
CN105590920B (zh) 半导体封装
KR102029804B1 (ko) 패키지 온 패키지형 반도체 패키지 및 그 제조 방법
JP2013197341A (ja) 積層型半導体装置とその製造方法
KR102093927B1 (ko) 반도체 패키지
KR102026227B1 (ko) 패키지 온 패키지형 반도체 패키지 및 그 제조방법
KR102392784B1 (ko) 멀티칩 반도체 패키지
US9966364B2 (en) Semiconductor package and method for fabricating the same
KR102109042B1 (ko) 반도체 패키지
KR20150035120A (ko) 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant