JP4397210B2 - 半導体装置 - Google Patents
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- JP4397210B2 JP4397210B2 JP2003358599A JP2003358599A JP4397210B2 JP 4397210 B2 JP4397210 B2 JP 4397210B2 JP 2003358599 A JP2003358599 A JP 2003358599A JP 2003358599 A JP2003358599 A JP 2003358599A JP 4397210 B2 JP4397210 B2 JP 4397210B2
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 230000008878 coupling Effects 0.000 claims description 37
- 238000010168 coupling process Methods 0.000 claims description 37
- 238000005859 coupling reaction Methods 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 18
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Description
前記半導体集積回路本体の上に、前記N×M個の出力パッドに電気的に接続して各出力を出力する出力バンプが配置されており、前記N個の半導体パワー素子のうちの同じパワー素子に属する前記出力バンプを、前記半導体集積回路本体との間に絶縁層を介して設けられた出力結合配線で接続して、外部へ接続するための出力外部電極に接続する、再配線層と、を有することを特徴とする。
前記再配線層には、前記電源パッドまたはグランドパッドに電気的に接触するように電源バンプまたはグランドバンプが配置されており、前記電源バンプまたはグランドバンプに電源外部電極またはグランド外部電極が接続されていることを特徴とする。
1A−1〜1B−2 分割素子
2A、2B 制御回路
3A、3B 信号線
4A、4B 出力配線
5A、5B 出力パッド
6 電源配線
7 電源パッド
10,10′,30,50,70 ICチップ本体
20,40,60,80 再配線層
11A-1〜11B-2 分割素子
12A,12B 制御回路
13A,13B 信号線
14A-1〜14B-2 出力配線
15A-1〜15B-2 出力パッド
16 電源配線
17 電源パッド
21A-1〜21B-2 出力バンプ
22A,22B 出力結合配線
23 電源バンプ
24A,24B 出力外部電極
25 電源バンプ電極
26 絶縁層
Claims (7)
- 複数N(N≧2)個の半導体パワー素子を備える半導体装置において、
前記各半導体パワー素子を複数M(M≧2)個の分割素子から構成し、N×M個の分割素子を異なる半導体パワー素子に属する分割素子が順次繰り返して並ぶように配置し、前記N×M個の分割素子からの出力配線を各出力配線同士が交差しないようにN×M個の出力パッドに接続している半導体集積回路本体と、
前記半導体集積回路本体の上に、前記N×M個の出力パッドに電気的に接続して各出力を出力する出力バンプが配置されており、前記N個の半導体パワー素子のうちの同じパワー素子に属する前記出力バンプを、前記半導体集積回路本体との間に絶縁層を介して設けられた出力結合配線で接続して、外部へ接続するための出力外部電極に接続する、再配線層と、を有することを特徴とする、半導体装置。 - 前記半導体集積回路本体には、前記N×M個の分割素子を少なくとも1つの電源パッドまたはグランドパッドに接続する電源配線またはグランド配線を有しており、
前記再配線層には、前記電源パッドまたはグランドパッドに電気的に接触するように電源バンプまたはグランドバンプが配置されており、前記電源バンプまたはグランドバンプに電源外部電極またはグランド外部電極が接続されていることを特徴とする、請求項1記載の半導体装置。 - 前記電源配線またはグランド配線は前記出力配線のいずれとも同一平面上で交差しないように配置されていることを特徴とする、請求項2記載の半導体装置。
- 前記N×M個の出力パッドが、各半導体パワー素子に属する分割素子群毎に、各分割素子に対して異なる方向に配置されていることを特徴とする、請求項2記載の半導体装置。
- 前記N×M個の電源パッドまたはグランドパッドが、各半導体パワー素子に属する分割素子群毎に、各分割素子に対して前記出力パッドとはさらに異なる方向に配置されていることを特徴とする、請求項4記載の半導体装置。
- 前記出力結合配線は、前記出力バンプと前記絶縁層が形成された後に、前記出力バンプと同じ材料で形成されていることを特徴とする、請求項1乃至5記載の半導体装置。
- 前記出力外部電極は、ボール電極であることを特徴とする、請求項1乃至6記載の半導体装置。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003358599A JP4397210B2 (ja) | 2003-10-20 | 2003-10-20 | 半導体装置 |
US10/962,162 US7265395B2 (en) | 2003-10-20 | 2004-10-08 | Semiconductor device |
TW093130973A TWI348752B (en) | 2003-10-20 | 2004-10-13 | Semiconductor device |
KR1020040083794A KR20050037974A (ko) | 2003-10-20 | 2004-10-20 | 반도체 장치 |
CNB200410086909XA CN100511679C (zh) | 2003-10-20 | 2004-10-20 | 半导体装置 |
US11/778,526 US20070262419A1 (en) | 2003-10-20 | 2007-07-16 | Semiconductor Device |
US14/821,493 US9607945B2 (en) | 2003-10-20 | 2015-08-07 | Semiconductor device comprising power elements in juxtaposition order |
US15/429,744 US20170154849A1 (en) | 2003-10-20 | 2017-02-10 | Semiconductor device comprising power elements in juxtaposition order |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003358599A JP4397210B2 (ja) | 2003-10-20 | 2003-10-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2005123486A JP2005123486A (ja) | 2005-05-12 |
JP4397210B2 true JP4397210B2 (ja) | 2010-01-13 |
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Application Number | Title | Priority Date | Filing Date |
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JP2003358599A Expired - Fee Related JP4397210B2 (ja) | 2003-10-20 | 2003-10-20 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (4) | US7265395B2 (ja) |
JP (1) | JP4397210B2 (ja) |
KR (1) | KR20050037974A (ja) |
CN (1) | CN100511679C (ja) |
TW (1) | TWI348752B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008112776A (ja) | 2006-10-30 | 2008-05-15 | Oki Electric Ind Co Ltd | 半導体装置 |
TWI493675B (zh) | 2013-05-01 | 2015-07-21 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
JP6223126B2 (ja) * | 2013-10-30 | 2017-11-01 | キヤノン株式会社 | 発光素子の駆動回路、露光ヘッド及び画像形成装置 |
JP6530199B2 (ja) | 2015-02-20 | 2019-06-12 | ローム株式会社 | 半導体装置 |
US10709010B1 (en) * | 2019-06-12 | 2020-07-07 | Himax Technologies Limited | Flexible printed circuit and display module having flexible printed circuit |
US11252822B1 (en) * | 2020-11-16 | 2022-02-15 | Himax Technologies Limited | Flexible printed circuit board and display apparatus having the same |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5155570A (en) * | 1988-06-21 | 1992-10-13 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit having a pattern layout applicable to various custom ICs |
DE3937068C2 (de) * | 1988-11-07 | 1994-10-06 | Toshiba Kawasaki Kk | Dynamische Halbleiterspeicheranordnung |
US6067062A (en) * | 1990-09-05 | 2000-05-23 | Seiko Instruments Inc. | Light valve device |
JPH04256338A (ja) * | 1991-02-08 | 1992-09-11 | Nec Corp | 集積回路の自動レイアウト方式 |
US5239448A (en) * | 1991-10-28 | 1993-08-24 | International Business Machines Corporation | Formulation of multichip modules |
US5366906A (en) * | 1992-10-16 | 1994-11-22 | Martin Marietta Corporation | Wafer level integration and testing |
JP3048790B2 (ja) | 1993-06-25 | 2000-06-05 | 三洋電機株式会社 | 半導体集積回路装置 |
US5510747A (en) * | 1993-11-30 | 1996-04-23 | Siliconix Incorporated | Gate drive technique for a bidirectional blocking lateral MOSFET |
US5767546A (en) * | 1994-12-30 | 1998-06-16 | Siliconix Incorporated | Laternal power mosfet having metal strap layer to reduce distributed resistance |
US5875089A (en) * | 1996-04-22 | 1999-02-23 | Mitsubishi Denki Kabushiki Kaisha | Input protection circuit device |
AU6878398A (en) * | 1997-04-02 | 1998-10-22 | Tessera, Inc. | Chip with internal signal routing in external element |
JP4086343B2 (ja) * | 1997-06-30 | 2008-05-14 | 沖電気工業株式会社 | プリントヘッド |
JP3472455B2 (ja) * | 1997-09-12 | 2003-12-02 | 沖電気工業株式会社 | 半導体集積回路装置及びそのパッケージ構造 |
JPH11168178A (ja) | 1997-12-04 | 1999-06-22 | Toshiba Corp | 集積回路素子 |
KR100283907B1 (ko) * | 1998-12-09 | 2001-03-02 | 김영환 | 서브워드라인 구동회로를 구비한 반도체 메모리 |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6784558B2 (en) * | 1999-12-30 | 2004-08-31 | Intel Corporation | Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads |
JP2001274323A (ja) * | 2000-03-24 | 2001-10-05 | Hitachi Ltd | 半導体装置とそれを搭載した半導体モジュール、および半導体装置の製造方法 |
US6456472B1 (en) * | 2000-04-07 | 2002-09-24 | Philsar Semiconductor Inc. | ESD protection in mixed signal ICs |
US6737301B2 (en) * | 2000-07-13 | 2004-05-18 | Isothermal Systems Research, Inc. | Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor |
TW577152B (en) * | 2000-12-18 | 2004-02-21 | Hitachi Ltd | Semiconductor integrated circuit device |
JP3939504B2 (ja) * | 2001-04-17 | 2007-07-04 | カシオ計算機株式会社 | 半導体装置並びにその製造方法および実装構造 |
JP4092890B2 (ja) * | 2001-05-31 | 2008-05-28 | 株式会社日立製作所 | マルチチップモジュール |
JP3997730B2 (ja) * | 2001-06-20 | 2007-10-24 | 株式会社日立製作所 | 電力変換装置及びそれを備えた移動体 |
EP1321984A3 (en) * | 2001-08-24 | 2004-01-14 | STMicroelectronics Limited | Semiconductor input/output circuit arrangement |
JP2003133417A (ja) * | 2001-10-26 | 2003-05-09 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置及びその設計方法 |
US6844783B2 (en) * | 2002-03-04 | 2005-01-18 | Araftek, Inc. | Radio frequency monolithic power amplifier layout techniques |
US20030218246A1 (en) * | 2002-05-22 | 2003-11-27 | Hirofumi Abe | Semiconductor device passing large electric current |
US6858945B2 (en) * | 2002-08-21 | 2005-02-22 | Broadcom Corporation | Multi-concentric pad arrangements for integrated circuit pads |
-
2003
- 2003-10-20 JP JP2003358599A patent/JP4397210B2/ja not_active Expired - Fee Related
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2004
- 2004-10-08 US US10/962,162 patent/US7265395B2/en active Active
- 2004-10-13 TW TW093130973A patent/TWI348752B/zh not_active IP Right Cessation
- 2004-10-20 CN CNB200410086909XA patent/CN100511679C/zh not_active Expired - Fee Related
- 2004-10-20 KR KR1020040083794A patent/KR20050037974A/ko not_active Application Discontinuation
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2007
- 2007-07-16 US US11/778,526 patent/US20070262419A1/en not_active Abandoned
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2015
- 2015-08-07 US US14/821,493 patent/US9607945B2/en active Active
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Also Published As
Publication number | Publication date |
---|---|
US9607945B2 (en) | 2017-03-28 |
US7265395B2 (en) | 2007-09-04 |
US20170154849A1 (en) | 2017-06-01 |
TWI348752B (en) | 2011-09-11 |
KR20050037974A (ko) | 2005-04-25 |
TW200520193A (en) | 2005-06-16 |
CN100511679C (zh) | 2009-07-08 |
CN1617339A (zh) | 2005-05-18 |
JP2005123486A (ja) | 2005-05-12 |
US20070262419A1 (en) | 2007-11-15 |
US20050110154A1 (en) | 2005-05-26 |
US20160071798A1 (en) | 2016-03-10 |
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