JP4384199B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4384199B2 JP4384199B2 JP2007098227A JP2007098227A JP4384199B2 JP 4384199 B2 JP4384199 B2 JP 4384199B2 JP 2007098227 A JP2007098227 A JP 2007098227A JP 2007098227 A JP2007098227 A JP 2007098227A JP 4384199 B2 JP4384199 B2 JP 4384199B2
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- 239000004065 semiconductor Substances 0.000 title claims description 79
- 238000004519 manufacturing process Methods 0.000 title claims description 59
- 238000005530 etching Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims 1
- 238000002407 reforming Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 26
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 238000001459 lithography Methods 0.000 description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000012670 alkaline solution Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Description
Claims (3)
- 第1ハードマスクに隣接して形成される側壁膜をマスクとして第1方向に直線状に延びる半導体層が複数並列して形成される第1領域、前記第1ハードマスク及び前記側壁膜をマスクとして隣接する2つの前記半導体層が第2方向につながって形成される第2領域を有する半導体装置の製造方法であって、
被エッチング部材上に前記第1ハードマスクを形成する工程と、
前記第1ハードマスク上に第1方向に直線状に延びる第2ハードマスクを複数箇所に並列して形成する工程と、
前記第2領域において前記第2ハードマスクにイオン注入を行う一方前記第1領域はマスクによりイオン注入を防止することにより前記第2領域のウエットエッチングに対するエッチングレートを前記第1領域に比べて変化させるための改質を行う工程と、
前記第2ハードマスクをマスクとして前記第1ハードマスクをエッチングする工程と、
前記第2領域の前記第2ハードマスクを残存させつつ前記第1領域の前記第2ハードマスクを選択的にウエットエッチングにより除去する工程と、
前記第1ハードマスクの側壁に前記側壁膜を形成する工程と、
前記第1領域において前記第2ハードマスクに覆われず上部が露出している第1ハードマスクを選択的にエッチング除去する工程と、
前記側壁膜及び前記第1ハードマスクをマスクとして前記被エッチング部材をエッチング除去する工程と
を備えたことを特徴とする半導体装置の製造方法。 - 前記側壁膜は、前記第2領域の前記第2ハードマスクの側壁にも形成される請求項1記載の半導体装置の製造方法。
- 前記イオン注入を行う工程は、前記第2ハードマスクをパターニングした後に、前記第2領域以外の前記第1領域にマスクを形成して実行されることを特徴とする請求項1記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007098227A JP4384199B2 (ja) | 2007-04-04 | 2007-04-04 | 半導体装置の製造方法 |
US12/059,280 US7737041B2 (en) | 2007-04-04 | 2008-03-31 | Semiconductor device and method of manufacturing the same |
US12/776,454 US20100219538A1 (en) | 2007-04-04 | 2010-05-10 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007098227A JP4384199B2 (ja) | 2007-04-04 | 2007-04-04 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008258360A JP2008258360A (ja) | 2008-10-23 |
JP4384199B2 true JP4384199B2 (ja) | 2009-12-16 |
Family
ID=39826247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007098227A Active JP4384199B2 (ja) | 2007-04-04 | 2007-04-04 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7737041B2 (ja) |
JP (1) | JP4384199B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5322668B2 (ja) * | 2009-01-21 | 2013-10-23 | 株式会社東芝 | 半導体装置の製造方法およびフォトマスク |
KR101618749B1 (ko) | 2009-02-27 | 2016-05-09 | 삼성전자주식회사 | 반도체 소자의 패턴 형성 방법 |
US8536063B2 (en) * | 2011-08-30 | 2013-09-17 | Avalanche Technology Inc. | MRAM etching processes |
JP5659135B2 (ja) | 2011-12-19 | 2015-01-28 | 株式会社東芝 | パターン形成方法 |
TWI621210B (zh) * | 2014-08-27 | 2018-04-11 | 聯華電子股份有限公司 | 一種製作半導體元件的方法 |
US10269576B1 (en) * | 2017-11-15 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etching and structures formed thereby |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2582412B2 (ja) | 1988-09-09 | 1997-02-19 | 富士通株式会社 | 不揮発性半導体記憶装置 |
JP3207592B2 (ja) * | 1993-03-19 | 2001-09-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JPH09321255A (ja) * | 1996-05-31 | 1997-12-12 | Ricoh Co Ltd | 不揮発性半導体記憶装置の製造方法 |
JPH11176956A (ja) | 1997-12-05 | 1999-07-02 | Sony Corp | 半導体不揮発性記憶装置 |
JP2004363390A (ja) * | 2003-06-05 | 2004-12-24 | Toshiba Corp | フォトマスクの補正方法、及び半導体装置の製造方法 |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
JP4921723B2 (ja) | 2005-04-18 | 2012-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
JP4271243B2 (ja) | 2006-04-11 | 2009-06-03 | 株式会社東芝 | 集積回路パターンの形成方法 |
JP5132098B2 (ja) * | 2006-07-18 | 2013-01-30 | 株式会社東芝 | 半導体装置 |
JP4996155B2 (ja) * | 2006-07-18 | 2012-08-08 | 株式会社東芝 | 半導体装置及びその製造方法 |
-
2007
- 2007-04-04 JP JP2007098227A patent/JP4384199B2/ja active Active
-
2008
- 2008-03-31 US US12/059,280 patent/US7737041B2/en not_active Expired - Fee Related
-
2010
- 2010-05-10 US US12/776,454 patent/US20100219538A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US7737041B2 (en) | 2010-06-15 |
US20080246168A1 (en) | 2008-10-09 |
US20100219538A1 (en) | 2010-09-02 |
JP2008258360A (ja) | 2008-10-23 |
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