JP4362581B2 - Manufacturing method of parallel plate capacitor - Google Patents
Manufacturing method of parallel plate capacitor Download PDFInfo
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- JP4362581B2 JP4362581B2 JP2003296037A JP2003296037A JP4362581B2 JP 4362581 B2 JP4362581 B2 JP 4362581B2 JP 2003296037 A JP2003296037 A JP 2003296037A JP 2003296037 A JP2003296037 A JP 2003296037A JP 4362581 B2 JP4362581 B2 JP 4362581B2
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- 239000003990 capacitor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010409 thin film Substances 0.000 claims description 39
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 6
- 229910021521 yttrium barium copper oxide Inorganic materials 0.000 description 24
- 238000000034 method Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002128 reflection high energy electron diffraction Methods 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
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Description
本発明は、ＹＢａ２Ｃｕ３Ｏ７−δ薄膜を中心とする酸化物超伝導デバイスや低温で使用される半導体デバイス等に使用されるチタン酸ストロンチウム積層体を誘電体として用いたコンデンサに関する。 The present invention relates to a capacitor using a strontium titanate laminate used as a dielectric for an oxide superconducting device centering on a YBa 2 Cu 3 O 7-δ thin film, a semiconductor device used at a low temperature, and the like.
バルク単結晶のチタン酸ストロンチウム（以下「ＳＴＯ」という。）は、量子常誘電体として知られ、その比誘電率は、４．２Ｋで２０，０００以上の値を示す。また、その比誘電率は、バイアス依存性、ストレス依存性を持ち、それらによって低下する特長を持っている。 Bulk single crystal strontium titanate (hereinafter referred to as “STO”) is known as a quantum paraelectric, and has a relative dielectric constant of 20,000 or more at 4.2K. In addition, the relative dielectric constant has a bias dependency and a stress dependency, and has a feature of decreasing by them.
ＳＴＯの格子定数は、酸化物超伝導体に非常に近い値を持つことから、該超伝導体のエピタキシャル成長下地基板として用いられ、超伝導デバイスの開発には重要な材料である。 Since the lattice constant of STO has a value very close to that of an oxide superconductor, it is used as an underlying substrate for epitaxial growth of the superconductor and is an important material for the development of superconducting devices.
実際に、ＳＴＯ薄膜は、デバイスに使用されているが、その比誘電率は１０，０００以下（４．２Ｋ）であり、バルク単結晶で得られている ２０，０００には達していない。 Actually, although the STO thin film is used for a device, its relative dielectric constant is 10,000 or less (4.2K), and does not reach 20,000 obtained by a bulk single crystal.
図１に、例として、M. Lippmaa, M. Kawasakiらの報告によるものを示す。この場合の比誘電率は、８，２００にしか達していない。 FIG. 1 shows an example reported by M. Lippmaa, M. Kawasaki et al. In this case, the relative dielectric constant reaches only 8,200.
上述したように、バルク単結晶ＳＴＯは、低温で高い誘電率を示すため、超伝導デバイスや低温で使用される半導体デバイスで使用した場合は、極めて有用な誘電体であるにも関わらず、薄膜化すると誘電率が低下してしまうという欠点があった。そのため、低温で高い誘電率を有する薄膜ＳＴＯを平行平板コンデンサの誘電体として利用することができなかった。
本発明の目的は、上記の問題点に鑑み、薄膜ＳＴＯを誘電体として用い、低温で高い誘電率を有し、かつ電場依存性の小さい平行平板コンデンサを提供することにある。
As described above, the bulk single crystal STO exhibits a high dielectric constant at a low temperature. Therefore, when used in a superconducting device or a semiconductor device used at a low temperature, the bulk single crystal STO is a very useful dielectric. However, there is a drawback that the dielectric constant is lowered. Therefore, a thin film STO having a high dielectric constant at a low temperature cannot be used as a dielectric for a parallel plate capacitor.
In view of the above problems, an object of the present invention is to provide a parallel plate capacitor that uses a thin film STO as a dielectric, has a high dielectric constant at a low temperature, and has a small electric field dependency.
本発明は、表面に突起を有する電極が形成されたＳＴＯ（１００）基板上に第１のチタン酸ストロンチウム薄膜を形成する工程、該第１のチタン酸ストロンチウム薄膜表面から突出する該突起の部分を除去するように該第１のチタン酸ストロンチウム薄膜表面を化学的機械研磨する工程、該基板を熱処理する工程及び該第１のチタン酸ストロンチウム薄膜上に第２のチタン酸ストロンチウム薄膜をエピタキシャル成長する工程を含む平行平板コンデンサの作製方法である。 The present invention includes a step of forming a first strontium titanate thin film on an STO (100) substrate on which an electrode having a protrusion is formed, and a portion of the protrusion protruding from the surface of the first strontium titanate thin film. A step of chemically mechanically polishing the surface of the first strontium titanate thin film so as to remove, a step of heat-treating the substrate, and a step of epitaxially growing a second strontium titanate thin film on the first strontium titanate thin film. This is a method for manufacturing a parallel plate capacitor.
本発明によれば、１００ｋＨｚで温度４．２Ｋにおいて２０，０００以上の比誘電率を有し、かつ電場依存性の小さいキャパシタンス（比誘電率）を有する平行平板コンデンサが得られる。 According to the present invention, it is possible to obtain a parallel plate capacitor having a relative dielectric constant of 20,000 or more at 100 kHz and a temperature of 4.2 K, and having a capacitance (relative dielectric constant) having a small electric field dependency.
図２に、本願発明に係る平行平板コンデンサの概念図を示す。
同図において、基板上に平行平板コンデンの下部電極となる下部イットリウム系酸化物超伝導（以下「ＹＢＣＯ」という。）層を積層し、該下部ＹＢＣＯ層の上に、第１のＳＴＯ層を堆積する。該第１層のＳＴＯ層の表面をＣＭＰする。この後、該表面に第２のＳＴＯ層を形成し、該第２のＳＴＯ層の上に平行平板コンデンサの上部電極となるＹＢＣＯ層を形成し、平行平板コンデンサの誘電体となる高誘電率チタン酸ストロンチウム薄膜積層を構成する。上記基板は、ＹＢａ ２ Ｃｕ ３ Ｏ ７−δ （δは１以下の正数）又は半導体ウェーハ基板で構成される。
FIG. 2 shows a conceptual diagram of a parallel plate capacitor according to the present invention.
In the figure, a lower yttrium-based oxide superconducting (hereinafter referred to as “YBCO”) layer is formed on a substrate as a lower electrode of a parallel plate capacitor, and a first STO layer is deposited on the lower YBCO layer. To do. The surface of the first STO layer is subjected to CMP. Thereafter, a second STO layer is formed on the surface, and a YBCO layer serving as an upper electrode of a parallel plate capacitor is formed on the second STO layer, and a high dielectric constant titanium serving as a dielectric of the parallel plate capacitor is formed. A strontium acid thin film stack is constructed. The substrate is made of YBa 2 Cu 3 O 7-δ (δ is a positive number of 1 or less) or a semiconductor wafer substrate.
次に、本発明に係るＣＭＰを用いた３層構造の平行平板コンデンサの作製プロセスを図５を用いて説明する。
なお、該作製プロセスにおけるＹＢＣＯ薄膜の成膜条件およびＳＴＯ薄膜の成膜条件をそれぞれ図３および図４に示す。
まず、工程（ａ）において、パルスレーザ成長法（以下「ＰＬＤ法」という。）を用いて、ＳＴＯ（１００）基板上に下部ＹＢＣＯ膜としてｃ軸配向ＹＢＣＯ（００ｎ）薄膜を厚さ３００ｎｍ成膜後、真空を破ることなく連続してＳＴＯ（００１）薄膜を厚さ１０ｎｍ成膜して、ＳＴＯ／ＹＢＣＯ構造を作製する。
Next, a manufacturing process of a parallel plate capacitor having a three-layer structure using CMP according to the present invention will be described with reference to FIGS.
The film forming conditions for the YBCO thin film and the film forming conditions for the STO thin film in the manufacturing process are shown in FIGS. 3 and 4, respectively.
First, in step (a), a c-axis oriented YBCO (00n) thin film having a thickness of 300 nm is formed as a lower YBCO film on an STO (100) substrate by using a pulse laser growth method (hereinafter referred to as “PLD method”). Thereafter, an STO (001) thin film having a thickness of 10 nm is continuously formed without breaking the vacuum to produce an STO / YBCO structure.
この厚さ１０ｎｍのＳＴＯ薄膜は、カバーＳＴＯ薄膜とよばれ、作製プロセスでＹＢＣＯが直接、大気や純水にさらされることを防ぎ、ＹＢＣＯ本来の超伝導特性を低下させないために成膜される。 This STO thin film having a thickness of 10 nm is called a cover STO thin film, and is formed in order to prevent YBCO from being directly exposed to the atmosphere and pure water in the manufacturing process, and not to deteriorate YBCO's original superconducting characteristics.
次に半導体技術で利用されているフォトリソグラフィー法を用いて、レジストにより下部パターンを作製し、低エネルギーイオンミリングを用いてエッチングを行い、平行平板コンデンサの下部電極となる下部ＹＢＣＯのパターンを形成する。 Next, using a photolithography method used in semiconductor technology, a lower pattern is formed with a resist, and etching is performed using low energy ion milling to form a pattern of a lower YBCO that becomes a lower electrode of a parallel plate capacitor. .
次に、工程（ｂ）において、ＰＬＤ法により、ＳＴＯ（１００）薄膜厚さ１μm成膜を行う。この成膜は、まず、基板を２００℃に保持し、真空度が１０−４Ｐａに到達した後、酸素ガス雰囲気中（酸素圧１００Ｐａ）において温度上昇を行い、８１０℃に到達した後、ＳＴＯ薄膜を成長させる。
Next, in step (b), a STO (100) thin film having a thickness of 1 μm is formed by the PLD method. In this film formation, first, the substrate is held at 200 ° C., the degree of vacuum reaches 10 −4 Pa, the temperature is increased in an oxygen gas atmosphere (
次に、工程（ｃ）において、このＳＴＯ薄膜表面上に存在する突起物を除去し、下部ＹＢＣＯ薄膜の作るパターンの段差を平坦化するためにＣＭＰにより研磨する。 Next, in step (c), the protrusions present on the surface of the STO thin film are removed, and polishing is performed by CMP in order to flatten the step of the pattern formed by the lower YBCO thin film.
下部ＹＢＣＯ薄膜を直接研磨すると超伝導特性を劣化させる原因になるため、ＳＴＯ薄膜の研磨を行う。その後、ＣＭＰプロセスによって表面に付着したＳｉ粒子等の不純物を、アセトン中でサンプルを超音波洗浄による表面クリーニングによって取り除く。 Polishing the lower YBCO thin film directly causes deterioration of superconducting properties, so the STO thin film is polished. Thereafter, impurities such as Si particles attached to the surface by the CMP process are removed by surface cleaning by ultrasonic cleaning of the sample in acetone.
ＣＭＰプロセス後、ＲＨＥＥＤ観測で観測した結果、試料表面は、アモルファス的であることが分かった。アモルファス結晶上にはエピタキシャル成長は、期待できない。このため、酸素圧１００Ｐａ雰囲気中、温度６００℃、２時間の熱処理を行った。
原子間力顕微鏡（ＡＦＭ）を用いて表面構造の観察を行った結果を図６に示す。この写真に見られるように、ＣＭＰ前においては、かなり大きな突起が観察されるが、ＣＭＰ後においては、上記突起に比べるとはるかに小さな突起が見られる程度に表面が滑らかになっている。
As a result of observation by RHEED observation after the CMP process, it was found that the sample surface was amorphous. Epitaxial growth cannot be expected on amorphous crystals. Therefore, heat treatment was performed at a temperature of 600 ° C. for 2 hours in an atmosphere having an oxygen pressure of 100 Pa.
FIG. 6 shows the results of observation of the surface structure using an atomic force microscope (AFM). As can be seen in this photograph, fairly large protrusions are observed before CMP, but after CMP, the surface is smooth enough to have much smaller protrusions than the above protrusions.
典型的に、２００ｎｍ程度の高さの円錐状形状の突起物は、ＣＭＰにより、高さが１／１０以下の２０ｎｍ以下に減少し、底面の面積が０．０４μｍ２以下と１／１０以下になっていることが確認された。ＣＭＰによって突起物の形状が小さくなっていることから、超伝導マイクロショートが解消されるであろうことが期待される。 Typically, a conical protrusion having a height of about 200 nm is reduced by CMP to 20 nm or less, which is 1/10 or less, and the area of the bottom surface is 0.04 μm 2 or less and 1/10 or less. It was confirmed that Since the shape of the protrusion is reduced by CMP, it is expected that the superconducting micro-short will be eliminated.
次に、工程（ｄ）において、熱処理後、ＰＬＤを用いて絶縁層ＳＴＯ薄膜を２００ｎｍ成膜し、真空を破ることなく連続して上部ＹＢＣＯ薄膜を２５０ｎｍ成膜する。このＳＴＯ薄膜は、ＣＭＰによって下部ＹＢＣＯ薄膜から成長している突起物の上部を切断した後、上部平面がＳＴＯ研磨表面に出現していることで生じるマイクロショートによる絶縁性の低下を防ぐためである。
図７に絶縁層ＳＴＯ薄膜と上部ＹＢＣＯの境界面の観察結果を示す。この写真に示すように、この境界面において格子配列がエピタキシャル成長していることが分かる。
Next, in step (d), after heat treatment, an insulating layer STO thin film is formed to 200 nm using PLD, and an upper YBCO thin film is continuously formed to 250 nm without breaking the vacuum. This STO thin film is for preventing the deterioration of insulation due to the micro-short caused by the upper plane appearing on the STO polished surface after cutting the upper part of the protrusion growing from the lower YBCO thin film by CMP. .
FIG. 7 shows an observation result of the boundary surface between the insulating layer STO thin film and the upper YBCO. As shown in this photograph, it can be seen that the lattice arrangement is epitaxially grown at this boundary surface.
成膜した平行平板コンデンサの上部電極となる上部ＹＢＣＯのパターンをフォトリソグラフィー法及び低エネルギーイオンミリングを用いて行い、平行平板コンデンサを作製した。ＨＦ５％を用いて、下部ＹＢＣＯに作製した電極部分のＳＴＯ膜をエッチングにより取り除いた。 A pattern of the upper YBCO that becomes the upper electrode of the formed parallel plate capacitor was formed by using a photolithography method and low energy ion milling to produce a parallel plate capacitor. The STO film of the electrode portion formed on the lower YBCO was removed by etching using HF 5%.
上部ＹＢＣＯと下部ＹＢＣＯ薄膜のパターンは、クロスオーバーした構造であり、クロスした部分は、上部ＹＢＣＯ／絶縁層ＳＴＯ／ＣＭＰ-ＳＴＯ／ｃａｐｐｅｄ−ＳＴＯ／下部ＹＢＣＯの積層構造である。 The pattern of the upper YBCO and the lower YBCO thin film has a crossover structure, and the crossed portion has a stacked structure of upper YBCO / insulating layer STO / CMP-STO / capped-STO / lower YBCO.
図８に作製した平行平板コンデンサの絶縁抵抗率の温度特性を示す。
同図に示すように、該絶縁抵抗率は、ＣＭＰ研磨することによって半導体的挙動が確認され、従来のＣＭＰ研磨をせずに作製した３層構造のものでは、低温域で急激に絶縁抵抗率が減少したのに対して、低温域での絶縁抵抗率が大幅に改善されていることが分かる。
FIG. 8 shows the temperature characteristics of the insulation resistivity of the manufactured parallel plate capacitor.
As shown in the figure, the insulation resistivity is confirmed to be semiconducting by CMP polishing, and in the case of a three-layer structure manufactured without conventional CMP polishing, the insulation resistivity is rapidly increased in a low temperature range. It can be seen that the insulation resistivity in the low temperature region is greatly improved.
図９に作製した平行平板コンデンサの誘電率の温度特性を示す。
同図に示すように、１００ｋＨｚで温度４．２Ｋにおいて２０，０００以上の比誘電率が確認された。この比誘電率の温度依存性は単結晶で得られた特性と一致していることから、優れた誘電特性を持つＳＴＯ薄膜がＹＢＣＯ薄膜上に作製されていることが分かる。
FIG. 9 shows the temperature characteristics of the dielectric constant of the manufactured parallel plate capacitor.
As shown in the figure, a relative dielectric constant of 20,000 or more was confirmed at 100 kHz and at a temperature of 4.2 K. Since the temperature dependence of the relative dielectric constant is consistent with the characteristics obtained with the single crystal, it can be seen that an STO thin film having excellent dielectric characteristics is produced on the YBCO thin film.
図１０に２．２Ｋで測定した平行平板コンデンサのキャパシタンス（比誘電率）の電場特性を示す。
同図に示すように、電場強度の変化に対してほぼ一定のキャパシタンス（比誘電率）を有する平行平板コンデンサが得られることが分かる。
FIG. 10 shows the electric field characteristics of the capacitance (relative permittivity) of the parallel plate capacitor measured at 2.2K.
As shown in the figure, it can be seen that a parallel plate capacitor having a substantially constant capacitance (dielectric constant) with respect to a change in electric field strength can be obtained.
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| JPH04354875A (en) * | 1991-05-30 | 1992-12-09 | Hitachi Ltd | Formation of metal oxide thin film |
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| JPH0653350A (en) * | 1992-07-30 | 1994-02-25 | Hitachi Ltd | Multilayer circuit board and its manufacturing method, and electronic circuit module and electronic circuit device using the method |
| JP3275216B2 (en) * | 1993-06-17 | 2002-04-15 | 富士通株式会社 | Ferroelectric memory |
| JP3478095B2 (en) * | 1997-10-27 | 2003-12-10 | 宇部興産株式会社 | Ferroelectric thin film element and method of manufacturing the same |
| JPH11195552A (en) * | 1998-01-06 | 1999-07-21 | Hokuriku Electric Ind Co Ltd | Thin-type capacitor and production of the same |
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| JP4022620B2 (en) * | 2003-05-22 | 2007-12-19 | 独立行政法人産業技術総合研究所 | Strontium titanate thin film laminate and method for producing the same |
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