JP4301947B2 - 温度補正されたデータ読み出し可能な不揮発性メモリ - Google Patents
温度補正されたデータ読み出し可能な不揮発性メモリ Download PDFInfo
- Publication number
- JP4301947B2 JP4301947B2 JP2003543030A JP2003543030A JP4301947B2 JP 4301947 B2 JP4301947 B2 JP 4301947B2 JP 2003543030 A JP2003543030 A JP 2003543030A JP 2003543030 A JP2003543030 A JP 2003543030A JP 4301947 B2 JP4301947 B2 JP 4301947B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- source
- memory cell
- drain terminal
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000008859 change Effects 0.000 claims description 22
- 238000013500 data storage Methods 0.000 claims description 12
- 230000001419 dependent effect Effects 0.000 claims 1
- 210000004027 cell Anatomy 0.000 description 60
- 238000000034 method Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 210000000352 storage cell Anatomy 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 239000002279 physical standard Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Read Only Memory (AREA)
Description
Claims (9)
- 不揮発性メモリであって、
電荷記憶素子と、制御ゲートと、第1および第2のソース/ドレイン端子とを有するデータ記憶メモリセルと、
前記第1のソース/ドレイン端子に第1の電流を供給するように動作可能な第1の電流源と、
前記第2のソース/ドレイン端子に電気的に接続されるノードと、
前記ノードにバイアス電圧を供給するように動作可能なバイアス回路であって、前記バイアス電圧は温度と共に変化し、前記バイアス電圧の変化は前記データ記憶メモリセルのしきい値電圧の熱による変化のほぼ逆であるバイアス回路において、
前記ノードに第2の電流を供給するように動作可能な第2の電流源と、
温度によって変化しない基準電圧を発生させるように動作可能な基準電圧発生器と、
前記ノードに結合された第1のソース/ドレイン端子と、前記基準電圧発生器の基準電圧に結合されたゲート端子とを有するバイアストランジスタと、を備えるバイアス回路と、
前記制御ゲートに制御された電圧レベルを供給するように動作可能な制御ゲート電圧回路と、
を備える不揮発性メモリ。 - 請求項1記載の不揮発性メモリにおいて、
前記データ記憶メモリセルの前記第1のソース/ドレイン端子に結合されたデータ感知回路をさらに備え、前記データ感知回路は前記第1のソース/ドレイン端子の電圧を感知するように動作可能である不揮発性メモリ。 - 請求項1記載の不揮発性メモリにおいて、
前記制御ゲート電圧回路は、前記データ記憶メモリセルの読み出しサイクル中に前記データ記憶メモリセルの前記制御ゲートに所定系列の電圧レベルを供給するように動作可能である不揮発性メモリ。 - 不揮発性メモリであって、
電荷記憶素子と、制御ゲートと、第1および第2のソース/ドレイン端子とを有するデータを記憶する手段と、
前記データを記憶する手段の前記第1のソース/ドレイン端子に第1の電流を供給する手段と、
前記データを記憶する手段の前記第2のソース/ドレイン端子にバイアス電圧を供給する手段であって、前記バイアス電圧は温度と共に変化し、前記バイアス電圧の変化は前記データを記憶する手段のしきい値電圧の熱による変化のほぼ逆である手段において、
前記データを記憶する手段の前記第2のソース/ドレイン端子から第2の電流を引き出す手段と、
温度によってほぼ変化しない基準電圧を発生させる手段と、
前記データを記憶する手段の前記第2のソース/ドレイン端子に結合された第1のソース/ドレイン端子と、前記基準電圧を発生させる手段に結合されたゲート端子とを有するバイアストランジスタと、を有する手段と、
前記データを記憶する手段の前記制御ゲートに制御された電圧レベルを供給する手段と、
を備える不揮発性メモリ。 - 請求項4記載の不揮発性メモリにおいて、
前記データを記憶する手段の前記第1のソース/ドレイン端子の電圧を感知する手段をさらに備える不揮発性メモリ。 - 請求項4記載の不揮発性メモリにおいて、
前記制御ゲートに制御された電圧レベルを供給する手段は、前記データを記憶する手段の読み出しサイクル中に前記制御ゲートに所定系列の電圧レベルを供給するように動作可能である不揮発性メモリ。 - 第1および第2のソース/ドレイン端子と少なくとも1つの記憶素子に結合された制御ゲートとの間のチャネルの少なくとも一部分の上に配置される、前記少なくとも1つの記憶素子をそれぞれ有する不揮発性メモリセルアレイであって、
データを読み出すために複数のメモリセルを同時にアドレス指定する手段であって、前記アドレス指定されたメモリセルの前記制御ゲートに制御された電圧レベルを供給する手段も備える手段と、
前記アドレス指定されたメモリセルの前記第1のソース/ドレイン端子に第1の電流を供給する手段と、
前記アドレス指定されたメモリセルの前記第2のソース/ドレイン端子にバイアス電圧を供給する手段であって、前記バイアス電圧は温度と共に変化し、前記バイアス電圧の変化は前記アドレス指定されたメモリセルのしきい値電圧の熱による変化のほぼ逆である手段において、
前記アドレス指定されたメモリセルの前記第2のソース/ドレイン端子から第2の電流を引き出す手段と、
温度によってほぼ変化しない基準電圧を発生させる手段と、
前記アドレス指定されたメモリセルの前記第2のソース/ドレイン端子に結合された第1のソース/ドレイン端子と、前記基準電圧を発生させる手段に結合されたゲート端子とを有するバイアストランジスタと、を有する手段と、
を備える不揮発性メモリセルアレイ。 - 請求項7記載の不揮発性メモリセルアレイにおいて、
前記アドレス指定されたメモリセルの前記第1のソース/ドレイン端子の電圧を感知する手段をさらに備える不揮発性メモリセルアレイ。 - 請求項7記載の不揮発性メモリセルアレイにおいて、
前記制御ゲートに制御された電圧レベルを供給する手段は、前記アドレス指定されたメモリセルの読み出しサイクル中に前記制御ゲートに所定系列の電圧レベルを供給するように動作可能である不揮発性メモリセルアレイ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/053,171 US6560152B1 (en) | 2001-11-02 | 2001-11-02 | Non-volatile memory with temperature-compensated data read |
PCT/US2002/034236 WO2003041082A1 (en) | 2001-11-02 | 2002-10-24 | Non-volatile memory with temperature-compensated data read |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005509240A JP2005509240A (ja) | 2005-04-07 |
JP4301947B2 true JP4301947B2 (ja) | 2009-07-22 |
Family
ID=21982373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003543030A Expired - Fee Related JP4301947B2 (ja) | 2001-11-02 | 2002-10-24 | 温度補正されたデータ読み出し可能な不揮発性メモリ |
Country Status (7)
Country | Link |
---|---|
US (1) | US6560152B1 (ja) |
EP (1) | EP1440446A4 (ja) |
JP (1) | JP4301947B2 (ja) |
KR (1) | KR100912795B1 (ja) |
CN (1) | CN100490157C (ja) |
TW (1) | TWI261267B (ja) |
WO (1) | WO2003041082A1 (ja) |
Families Citing this family (147)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5657332A (en) * | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
US6735546B2 (en) | 2001-08-31 | 2004-05-11 | Matrix Semiconductor, Inc. | Memory device and method for temperature-based control over write and/or read operations |
US6724665B2 (en) | 2001-08-31 | 2004-04-20 | Matrix Semiconductor, Inc. | Memory device and method for selectable sub-array activation |
US6801454B2 (en) * | 2002-10-01 | 2004-10-05 | Sandisk Corporation | Voltage generation circuitry having temperature compensation |
US6954394B2 (en) * | 2002-11-27 | 2005-10-11 | Matrix Semiconductor, Inc. | Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions |
US6839281B2 (en) * | 2003-04-14 | 2005-01-04 | Jian Chen | Read and erase verify methods and circuits suitable for low voltage non-volatile memories |
US7057958B2 (en) * | 2003-09-30 | 2006-06-06 | Sandisk Corporation | Method and system for temperature compensation for memory cells with temperature-dependent behavior |
US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
US7173852B2 (en) * | 2003-10-03 | 2007-02-06 | Sandisk Corporation | Corrected data storage and handling methods |
US7321516B2 (en) * | 2004-02-19 | 2008-01-22 | Stmicroelectronics, S.R.L. | Biasing structure for accessing semiconductor memory cell storage elements |
US20050199937A1 (en) * | 2004-03-11 | 2005-09-15 | Chang Augustine W. | 3D flash EEPROM cell and methods of implementing the same |
US20050258863A1 (en) * | 2004-05-20 | 2005-11-24 | Chang Augustine W | Quaternary and trinary logic switching circuits |
US7110298B2 (en) * | 2004-07-20 | 2006-09-19 | Sandisk Corporation | Non-volatile system with program time control |
US7116588B2 (en) * | 2004-09-01 | 2006-10-03 | Micron Technology, Inc. | Low supply voltage temperature compensated reference voltage generator and method |
US7395404B2 (en) | 2004-12-16 | 2008-07-01 | Sandisk Corporation | Cluster auto-alignment for storing addressable data packets in a non-volatile memory array |
US7412560B2 (en) * | 2004-12-16 | 2008-08-12 | Sandisk Corporation | Non-volatile memory and method with multi-stream updating |
US7366826B2 (en) * | 2004-12-16 | 2008-04-29 | Sandisk Corporation | Non-volatile memory and method with multi-stream update tracking |
US7386655B2 (en) * | 2004-12-16 | 2008-06-10 | Sandisk Corporation | Non-volatile memory and method with improved indexing for scratch pad and update blocks |
US7315916B2 (en) * | 2004-12-16 | 2008-01-01 | Sandisk Corporation | Scratch pad block |
US7218570B2 (en) * | 2004-12-17 | 2007-05-15 | Sandisk 3D Llc | Apparatus and method for memory operations using address-dependent conditions |
JP4746326B2 (ja) * | 2005-01-13 | 2011-08-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7327608B2 (en) * | 2006-03-28 | 2008-02-05 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in programming method |
US7330373B2 (en) * | 2006-03-28 | 2008-02-12 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in memory system |
WO2007132452A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies | Reducing programming error in memory devices |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
WO2007132456A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device with adaptive capacity |
WO2007132457A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
US7283414B1 (en) | 2006-05-24 | 2007-10-16 | Sandisk 3D Llc | Method for improving the precision of a temperature-sensor circuit |
US7391650B2 (en) * | 2006-06-16 | 2008-06-24 | Sandisk Corporation | Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
US7342831B2 (en) * | 2006-06-16 | 2008-03-11 | Sandisk Corporation | System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
US7436724B2 (en) * | 2006-08-04 | 2008-10-14 | Sandisk Corporation | Method and system for independent control of voltage and its temperature co-efficient in non-volatile memory devices |
US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
US7886204B2 (en) * | 2006-09-27 | 2011-02-08 | Sandisk Corporation | Methods of cell population distribution assisted read margining |
US7716538B2 (en) * | 2006-09-27 | 2010-05-11 | Sandisk Corporation | Memory with cell population distribution assisted read margining |
US7456678B2 (en) * | 2006-10-10 | 2008-11-25 | Atmel Corporation | Apparatus and method for providing a temperature compensated reference current |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
WO2008068747A2 (en) | 2006-12-03 | 2008-06-12 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US7593263B2 (en) | 2006-12-17 | 2009-09-22 | Anobit Technologies Ltd. | Memory device with reduced reading latency |
US7403434B1 (en) * | 2006-12-29 | 2008-07-22 | Sandisk Corporation | System for controlling voltage in non-volatile memory systems |
US7447093B2 (en) * | 2006-12-29 | 2008-11-04 | Sandisk Corporation | Method for controlling voltage in non-volatile memory systems |
US7554853B2 (en) * | 2006-12-30 | 2009-06-30 | Sandisk Corporation | Non-volatile storage with bias based on selective word line |
US7468920B2 (en) | 2006-12-30 | 2008-12-23 | Sandisk Corporation | Applying adaptive body bias to non-volatile storage |
US7525843B2 (en) * | 2006-12-30 | 2009-04-28 | Sandisk Corporation | Non-volatile storage with adaptive body bias |
US7583539B2 (en) * | 2006-12-30 | 2009-09-01 | Sandisk Corporation | Non-volatile storage with bias for temperature compensation |
US7468919B2 (en) * | 2006-12-30 | 2008-12-23 | Sandisk Corporation | Biasing non-volatile storage based on selected word line |
US7583535B2 (en) * | 2006-12-30 | 2009-09-01 | Sandisk Corporation | Biasing non-volatile storage to compensate for temperature variations |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
US7477547B2 (en) * | 2007-03-28 | 2009-01-13 | Sandisk Corporation | Flash memory refresh techniques triggered by controlled scrub data reads |
US7573773B2 (en) * | 2007-03-28 | 2009-08-11 | Sandisk Corporation | Flash memory with data refresh triggered by controlled scrub data reads |
US7532516B2 (en) * | 2007-04-05 | 2009-05-12 | Sandisk Corporation | Non-volatile storage with current sensing of negative threshold voltages |
US7606076B2 (en) * | 2007-04-05 | 2009-10-20 | Sandisk Corporation | Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US7606072B2 (en) * | 2007-04-24 | 2009-10-20 | Sandisk Corporation | Non-volatile storage with compensation for source voltage drop |
US7606071B2 (en) * | 2007-04-24 | 2009-10-20 | Sandisk Corporation | Compensating source voltage drop in non-volatile storage |
WO2008139441A2 (en) | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
KR101509836B1 (ko) | 2007-11-13 | 2015-04-06 | 애플 인크. | 멀티 유닛 메모리 디바이스에서의 메모리 유닛의 최적화된 선택 |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
KR100940268B1 (ko) | 2007-12-28 | 2010-02-04 | 주식회사 하이닉스반도체 | 온도 센서 회로 |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8059457B2 (en) * | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US7755946B2 (en) * | 2008-09-19 | 2010-07-13 | Sandisk Corporation | Data state-based temperature compensation during sensing in non-volatile memory |
US8004917B2 (en) | 2008-09-22 | 2011-08-23 | Sandisk Technologies Inc. | Bandgap voltage and temperature coefficient trimming algorithm |
US8197683B2 (en) * | 2008-10-16 | 2012-06-12 | William Steven Lopes | System for conditioning fluids utilizing a magnetic fluid processor |
US7889575B2 (en) * | 2008-09-22 | 2011-02-15 | Sandisk Corporation | On-chip bias voltage temperature coefficient self-calibration mechanism |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US7876618B2 (en) * | 2009-03-23 | 2011-01-25 | Sandisk Corporation | Non-volatile memory with reduced leakage current for unselected blocks and method for operating same |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8045384B2 (en) | 2009-06-22 | 2011-10-25 | Sandisk Technologies Inc. | Reduced programming pulse width for enhanced channel boosting in non-volatile storage |
US7916533B2 (en) * | 2009-06-24 | 2011-03-29 | Sandisk Corporation | Forecasting program disturb in memory by detecting natural threshold voltage distribution |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US7974134B2 (en) * | 2009-11-13 | 2011-07-05 | Sandisk Technologies Inc. | Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
US8213255B2 (en) | 2010-02-19 | 2012-07-03 | Sandisk Technologies Inc. | Non-volatile storage with temperature compensation based on neighbor state information |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US8526233B2 (en) | 2011-05-23 | 2013-09-03 | Sandisk Technologies Inc. | Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation |
EP2565175B1 (en) | 2011-08-31 | 2021-04-21 | Aristotle University of Thessaloniki | Catalytic process for the production of 1,2-propanediol from crude glycerol stream |
CN103021451B (zh) * | 2011-09-22 | 2016-03-30 | 复旦大学 | 一种基于阈值电压调节的多级温度控制自刷新存储设备及其方法 |
CN103035281B (zh) * | 2011-09-29 | 2016-01-13 | 复旦大学 | 一种基于单元漏电检测的温度控制自刷新方法 |
CN103035283B (zh) * | 2011-09-29 | 2016-09-07 | 复旦大学 | 一种不含温度传感器的多级温度控制自刷新存储设备及其方法 |
US8687421B2 (en) | 2011-11-21 | 2014-04-01 | Sandisk Technologies Inc. | Scrub techniques for use with dynamic read |
US8611157B2 (en) | 2011-12-22 | 2013-12-17 | Sandisk Technologies Inc. | Program temperature dependent read |
US8576651B2 (en) | 2012-01-20 | 2013-11-05 | Sandisk 3D Llc | Temperature compensation of conductive bridge memory arrays |
US8941369B2 (en) | 2012-03-19 | 2015-01-27 | Sandisk Technologies Inc. | Curvature compensated band-gap design trimmable at a single temperature |
US8542000B1 (en) | 2012-03-19 | 2013-09-24 | Sandisk Technologies Inc. | Curvature compensated band-gap design |
US9541456B2 (en) | 2014-02-07 | 2017-01-10 | Sandisk Technologies Llc | Reference voltage generator for temperature sensor with trimming capability at two temperatures |
CN103871465A (zh) * | 2014-03-17 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | 非易失性存储器及其操作方法 |
US9361994B1 (en) | 2014-09-04 | 2016-06-07 | Cypress Semiconductor Corporation | Method of increasing read current window in non-volatile memory |
US9543028B2 (en) | 2014-09-19 | 2017-01-10 | Sandisk Technologies Llc | Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect |
US9552171B2 (en) | 2014-10-29 | 2017-01-24 | Sandisk Technologies Llc | Read scrub with adaptive counter management |
US9978456B2 (en) | 2014-11-17 | 2018-05-22 | Sandisk Technologies Llc | Techniques for reducing read disturb in partially written blocks of non-volatile memory |
US9349479B1 (en) | 2014-11-18 | 2016-05-24 | Sandisk Technologies Inc. | Boundary word line operation in nonvolatile memory |
US9449700B2 (en) | 2015-02-13 | 2016-09-20 | Sandisk Technologies Llc | Boundary word line search and open block read methods with reduced read disturb |
US9715913B1 (en) | 2015-07-30 | 2017-07-25 | Sandisk Technologies Llc | Temperature code circuit with single ramp for calibration and determination |
US9653154B2 (en) | 2015-09-21 | 2017-05-16 | Sandisk Technologies Llc | Write abort detection for multi-state memories |
US9881683B1 (en) | 2016-12-13 | 2018-01-30 | Cypress Semiconductor Corporation | Suppression of program disturb with bit line and select gate voltage regulation |
US9928126B1 (en) | 2017-06-01 | 2018-03-27 | Apple Inc. | Recovery from cross-temperature read failures by programming neighbor word lines |
US10755783B2 (en) * | 2018-08-27 | 2020-08-25 | Silicon Storage Technology | Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network |
CN112309476B (zh) * | 2019-07-26 | 2023-03-10 | 西安格易安创集成电路有限公司 | 一种NAND Flash单元数据的读取方法和装置 |
US11257550B2 (en) * | 2020-06-12 | 2022-02-22 | Taiwan Semiconductor Manufacturing Company Limited | Bias control for memory cells with multiple gate electrodes |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
US12046314B2 (en) | 2022-08-29 | 2024-07-23 | SanDisk Technologies, Inc. | NAND memory with different pass voltage ramp rates for binary and multi-state memory |
US11875043B1 (en) | 2022-08-29 | 2024-01-16 | Sandisk Technologies Llc | Loop dependent word line ramp start time for program verify of multi-level NAND memory |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5172338B1 (en) | 1989-04-13 | 1997-07-08 | Sandisk Corp | Multi-state eeprom read and write circuits and techniques |
JPH0344895A (ja) * | 1989-07-12 | 1991-02-26 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2000011671A (ja) | 1998-06-29 | 2000-01-14 | Hitachi Ltd | 半導体記憶装置 |
EP1058270B1 (en) * | 1999-06-04 | 2007-03-21 | STMicroelectronics S.r.l. | Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase |
US6205074B1 (en) * | 2000-02-29 | 2001-03-20 | Advanced Micro Devices, Inc. | Temperature-compensated bias generator |
-
2001
- 2001-11-02 US US10/053,171 patent/US6560152B1/en not_active Expired - Lifetime
-
2002
- 2002-10-24 WO PCT/US2002/034236 patent/WO2003041082A1/en active Application Filing
- 2002-10-24 KR KR1020047006728A patent/KR100912795B1/ko active IP Right Grant
- 2002-10-24 CN CNB028265947A patent/CN100490157C/zh not_active Expired - Fee Related
- 2002-10-24 EP EP02773907A patent/EP1440446A4/en not_active Withdrawn
- 2002-10-24 JP JP2003543030A patent/JP4301947B2/ja not_active Expired - Fee Related
- 2002-10-30 TW TW091132174A patent/TWI261267B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN100490157C (zh) | 2009-05-20 |
JP2005509240A (ja) | 2005-04-07 |
US6560152B1 (en) | 2003-05-06 |
CN1610948A (zh) | 2005-04-27 |
WO2003041082A1 (en) | 2003-05-15 |
EP1440446A4 (en) | 2005-02-02 |
TW200300259A (en) | 2003-05-16 |
EP1440446A1 (en) | 2004-07-28 |
KR100912795B1 (ko) | 2009-08-19 |
TWI261267B (en) | 2006-09-01 |
KR20040070351A (ko) | 2004-08-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4301947B2 (ja) | 温度補正されたデータ読み出し可能な不揮発性メモリ | |
CN101432821B (zh) | 模仿存储器装置中的编程验证漏极电阻 | |
JP4988156B2 (ja) | 隣接フィールドエラーが低減された不揮発性メモリおよび方法 | |
KR100829790B1 (ko) | 플래시 메모리 장치 및 플래시 메모리 장치의 데이터 독출방법 | |
US8614923B2 (en) | Memory cell sensing using negative voltage | |
KR101196936B1 (ko) | 불휘발성 반도체 기억 장치 | |
JP3987715B2 (ja) | 不揮発性半導体メモリおよび不揮発性半導体メモリのプログラム電圧制御方法 | |
TWI494930B (zh) | 記憶體裝置之數個操作 | |
US9230679B2 (en) | Apparatuses and methods for sensing fuse states | |
US8274842B1 (en) | Variable impedance memory device having simultaneous program and erase, and corresponding methods and circuits | |
KR100660534B1 (ko) | 불휘발성 메모리 장치의 프로그램 검증방법 | |
JP2008165980A (ja) | 不揮発性メモリにおけるステアリングゲートとビットラインとのセグメンテーション | |
KR101699476B1 (ko) | 반도체 기억장치 | |
WO2008008466A2 (en) | Current sensing for flash | |
JP2004095001A (ja) | 不揮発性半導体記憶装置、不揮発性半導体記憶装置組込システムおよび不良ブロック検出方法 | |
US20080094905A1 (en) | Nonvolatile Memory | |
US7830708B1 (en) | Compensating for variations in memory cell programmed state distributions | |
US6108263A (en) | Memory system, method for verifying data stored in a memory system after a write cycle and method for writing to a memory system | |
US8520465B2 (en) | Semiconductor device | |
JP2009295221A (ja) | 半導体記憶装置 | |
KR19990013057A (ko) | 단일 비트 데이터와 다중 비트 데이터를 동일한 칩에 선택적으로 저장하는 플래시 메모리 장치의 독출 및 기입 방법 | |
US7616497B2 (en) | NOR flash memory and related read method | |
CN114783488A (zh) | 页缓冲器、编程方法、存储器装置及*** | |
US7190619B2 (en) | Circuit for indicating termination of scan of bits to be programmed in nonvolatile semiconductor memory device | |
CN111429961A (zh) | 补偿非易失存储元件编程时电荷流失与源极线偏置的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050928 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080724 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080819 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081117 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090324 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090421 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120501 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4301947 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120501 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130501 Year of fee payment: 4 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130501 Year of fee payment: 4 |
|
R370 | Written measure of declining of transfer procedure |
Free format text: JAPANESE INTERMEDIATE CODE: R370 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130501 Year of fee payment: 4 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |