JP4265668B2 - 回路基板の製造方法および回路基板 - Google Patents
回路基板の製造方法および回路基板 Download PDFInfo
- Publication number
- JP4265668B2 JP4265668B2 JP2007058596A JP2007058596A JP4265668B2 JP 4265668 B2 JP4265668 B2 JP 4265668B2 JP 2007058596 A JP2007058596 A JP 2007058596A JP 2007058596 A JP2007058596 A JP 2007058596A JP 4265668 B2 JP4265668 B2 JP 4265668B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- semiconductor substrate
- insulating layer
- conductive layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C26/00—Coating not provided for in groups C23C2/00 - C23C24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Organic Chemistry (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (3)
- 半導体基板に表面に向かって開口された複数の第1孔部を形成する第1工程と、
前記複数の第1孔部の底部側に絶縁層を埋め込む第2工程と、
底部側に前記絶縁層が埋め込まれた前記第1孔部を第1導電層で埋め込む第3工程と、
前記複数の第1孔部に埋め込まれた各絶縁層が露出するまで、前記半導体基板を裏面側から研磨する第4工程と、
露出された前記各絶縁層に、前記第1導電層に達する状態の第2孔部をそれぞれ形成し、当該第2孔部内に前記第1導電層に接続される第2導電層を埋め込み形成する第5工程とを有する
ことを特徴とする回路基板の製造方法。 - 請求項1記載の回路基板の製造方法において、
前記第4工程では、前記複数の第1孔部のうち、最も深い第1孔部内の前記絶縁層の表面が露出するまで、前記半導体基板を裏面側から研磨し、さらに、当該絶縁層の膜厚分の前記半導体基板と当該絶縁層とを裏面側から研磨する
ことを特徴とする回路基板の製造方法。 - 半導体基板を貫通する状態で設けられた複数の第1孔部と、
前記複数の第1孔部内の前記半導体基板の裏面側に設けられた膜厚の異なる絶縁層と、
前記絶縁層に前記第1孔部と連通する状態で設けられた第2孔部と、
前記第1孔部と前記第2孔部の内部に前記半導体基板を貫通する状態で設けられた導電層とを備えた
ことを特徴とする回路基板。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007058596A JP4265668B2 (ja) | 2007-03-08 | 2007-03-08 | 回路基板の製造方法および回路基板 |
TW097105967A TWI377623B (en) | 2007-03-08 | 2008-02-20 | Method of manufacturing circuit board and circuit board |
US12/043,272 US8141243B2 (en) | 2007-03-08 | 2008-03-06 | Method of manufacturing circuit board |
KR1020080020859A KR101430202B1 (ko) | 2007-03-08 | 2008-03-06 | 회로기판 제조방법 및 회로기판 |
CN2008100855108A CN101261947B (zh) | 2007-03-08 | 2008-03-10 | 制造电路板的方法及电路板 |
US13/178,615 US8461464B2 (en) | 2007-03-08 | 2011-07-08 | Circuit board having interconnected holes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007058596A JP4265668B2 (ja) | 2007-03-08 | 2007-03-08 | 回路基板の製造方法および回路基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008226882A JP2008226882A (ja) | 2008-09-25 |
JP4265668B2 true JP4265668B2 (ja) | 2009-05-20 |
Family
ID=39741414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007058596A Expired - Fee Related JP4265668B2 (ja) | 2007-03-08 | 2007-03-08 | 回路基板の製造方法および回路基板 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8141243B2 (ja) |
JP (1) | JP4265668B2 (ja) |
KR (1) | KR101430202B1 (ja) |
CN (1) | CN101261947B (ja) |
TW (1) | TWI377623B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9859191B2 (en) | 2015-03-10 | 2018-01-02 | Samsung Electronics Co., Ltd. | Semiconductor device including conductive via with buffer layer at tapered portion of conductive via |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8263497B2 (en) * | 2009-01-13 | 2012-09-11 | International Business Machines Corporation | High-yield method of exposing and contacting through-silicon vias |
US9420707B2 (en) * | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
FR2985088B1 (fr) * | 2011-12-23 | 2015-04-17 | Commissariat Energie Atomique | Via tsv dote d'une structure de liberation de contraintes et son procede de fabrication |
KR101867961B1 (ko) | 2012-02-13 | 2018-06-15 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US9947609B2 (en) | 2012-03-09 | 2018-04-17 | Honeywell International Inc. | Integrated circuit stack |
US9576881B2 (en) | 2013-02-18 | 2017-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP5834030B2 (ja) | 2013-02-18 | 2015-12-16 | 株式会社東芝 | 半導体装置 |
TWI514531B (zh) * | 2014-01-15 | 2015-12-21 | 矽品精密工業股份有限公司 | 半導體結構及其製法 |
US10026660B2 (en) * | 2014-10-31 | 2018-07-17 | Veeco Precision Surface Processing Llc | Method of etching the back of a wafer to expose TSVs |
US9548277B2 (en) | 2015-04-21 | 2017-01-17 | Honeywell International Inc. | Integrated circuit stack including a patterned array of electrically conductive pillars |
TWI738757B (zh) | 2016-04-05 | 2021-09-11 | 美商維克儀器公司 | 經由化學的適應性峰化來控制蝕刻速率的裝置和方法 |
WO2018160461A1 (en) | 2017-03-03 | 2018-09-07 | Veeco Precision Surface Processing Llc | An apparatus and method for wafer thinning in advanced packaging applications |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5447871A (en) * | 1993-03-05 | 1995-09-05 | Goldstein; Edward F. | Electrically conductive interconnection through a body of semiconductor material |
JP2004228598A (ja) | 1997-10-01 | 2004-08-12 | Toshiba Corp | マルチチップ半導体装置 |
TW594972B (en) * | 2002-03-19 | 2004-06-21 | Seiko Epson Corp | Semiconductor device and its manufacturing method, circuit board and electronic machine |
KR100537892B1 (ko) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
JP4127207B2 (ja) | 2003-12-25 | 2008-07-30 | Jsr株式会社 | 回路基板の製造方法 |
JP4339152B2 (ja) * | 2004-03-08 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | 配線構造の形成方法 |
JP4327644B2 (ja) * | 2004-03-31 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006032864A (ja) * | 2004-07-21 | 2006-02-02 | Sony Corp | 多層配線構造と多層配線構造を有する半導体装置とこれらの製造方法 |
JP4564342B2 (ja) * | 2004-11-24 | 2010-10-20 | 大日本印刷株式会社 | 多層配線基板およびその製造方法 |
-
2007
- 2007-03-08 JP JP2007058596A patent/JP4265668B2/ja not_active Expired - Fee Related
-
2008
- 2008-02-20 TW TW097105967A patent/TWI377623B/zh not_active IP Right Cessation
- 2008-03-06 KR KR1020080020859A patent/KR101430202B1/ko not_active IP Right Cessation
- 2008-03-06 US US12/043,272 patent/US8141243B2/en not_active Expired - Fee Related
- 2008-03-10 CN CN2008100855108A patent/CN101261947B/zh active Active
-
2011
- 2011-07-08 US US13/178,615 patent/US8461464B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9859191B2 (en) | 2015-03-10 | 2018-01-02 | Samsung Electronics Co., Ltd. | Semiconductor device including conductive via with buffer layer at tapered portion of conductive via |
Also Published As
Publication number | Publication date |
---|---|
TWI377623B (en) | 2012-11-21 |
CN101261947B (zh) | 2010-04-07 |
CN101261947A (zh) | 2008-09-10 |
US20080218983A1 (en) | 2008-09-11 |
KR20080082491A (ko) | 2008-09-11 |
US8141243B2 (en) | 2012-03-27 |
US8461464B2 (en) | 2013-06-11 |
JP2008226882A (ja) | 2008-09-25 |
US20120031660A1 (en) | 2012-02-09 |
KR101430202B1 (ko) | 2014-08-18 |
TW200849397A (en) | 2008-12-16 |
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