JP4213601B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4213601B2 JP4213601B2 JP2004041445A JP2004041445A JP4213601B2 JP 4213601 B2 JP4213601 B2 JP 4213601B2 JP 2004041445 A JP2004041445 A JP 2004041445A JP 2004041445 A JP2004041445 A JP 2004041445A JP 4213601 B2 JP4213601 B2 JP 4213601B2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- semiconductor device
- resin
- mold resin
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
このように、従来では、Agめっき膜とダイボンド材30との密着力が小さいため、リフロー時にAgめっき膜とダイボンド材30との間で剥離が発生してしまい、その結果、上記図6中の太線H3に示されるように、ヒートシンク10とモールド樹脂60とは突起部12の下側部分を除いてほぼ全面で剥離してしまう。
なお、上記実施形態では、ICチップ20とリードフレーム40との電気的な接続はワイヤ50にて行っていたが、これに限定されるものではない。それ以外にも、バンプなどによりICチップ20とリードフレーム40との電気的な接続が行われていてもよい。
30…ダイボンド材、40…リードとしてのリードフレーム、60…モールド樹脂、
100…外部基板、120…はんだ、
t…ヒートシンクの他面から突起部までの距離としてのコイニング深さ。
Claims (5)
- ヒートシンク(10)と、
前記ヒートシンク(10)の一面側にダイボンド材(30)を介して搭載された半導体チップ(20)と、
前記半導体チップ(20)の周囲に配置され前記半導体チップ(20)と電気的に接続されたリード(40)と、
前記ヒートシンク(10)の他面が露出するように、前記半導体チップ(20)、前記ヒートシンク(10)、前記リード(40)を包み込むように封止するモールド樹脂(60)とを備える樹脂モールドパッケージタイプの半導体装置において、
前記モールド樹脂(60)の260℃におけるヤング率が0.7GPa以下であることを特徴とする半導体装置。 - 前記ヒートシンク(10)は、前記一面と前記他面との間の側面に突起部(12)を有するものであり、前記ヒートシンク(10)の前記他面から前記突起部(12)までの距離(t)は0.25mm以上であることを特徴とする請求項1に記載の半導体装置。
- 前記ヒートシンク(10)の前記一面のうち前記半導体チップ(20)が搭載される領域の最表面には、めっきが施されていないことを特徴とする請求項1または2に記載の半導体装置。
- 前記モールド樹脂(60)から前記リード(40)の一部が露出しており、このリード(40)の露出部が、外部基板(100)にはんだ(120)を介して接合される部位となっていることを特徴とする請求項1ないし3のいずれか1つに記載の半導体装置。
- 前記はんだ(120)は、Pbフリーはんだであることを特徴とする請求項4に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004041445A JP4213601B2 (ja) | 2004-02-18 | 2004-02-18 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004041445A JP4213601B2 (ja) | 2004-02-18 | 2004-02-18 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005235925A JP2005235925A (ja) | 2005-09-02 |
JP4213601B2 true JP4213601B2 (ja) | 2009-01-21 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004041445A Expired - Fee Related JP4213601B2 (ja) | 2004-02-18 | 2004-02-18 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4213601B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5541393B2 (ja) * | 2013-06-05 | 2014-07-09 | 三菱電機株式会社 | 電力用半導体装置の製造方法 |
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2004
- 2004-02-18 JP JP2004041445A patent/JP4213601B2/ja not_active Expired - Fee Related
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JP2005235925A (ja) | 2005-09-02 |
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