JP4076925B2 - 電圧生成回路 - Google Patents
電圧生成回路 Download PDFInfo
- Publication number
- JP4076925B2 JP4076925B2 JP2003292518A JP2003292518A JP4076925B2 JP 4076925 B2 JP4076925 B2 JP 4076925B2 JP 2003292518 A JP2003292518 A JP 2003292518A JP 2003292518 A JP2003292518 A JP 2003292518A JP 4076925 B2 JP4076925 B2 JP 4076925B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- value
- voltage
- digital value
- fuses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000006243 chemical reaction Methods 0.000 claims description 28
- 238000009966 trimming Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/108—Converters having special provisions for facilitating access for testing purposes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Analogue/Digital Conversion (AREA)
- Semiconductor Integrated Circuits (AREA)
- Control Of Voltage And Current In General (AREA)
Description
Claims (1)
- デジタル値をアナログ値に変換することにより電圧信号を生成するD/A変換回路と、
前記電圧信号のアナログ電圧値が目標値となるように前記D/A変換回路における変換対象のデジタル値を設定する設定回路と、を有し、
前記D/A変換回路は、前記設定回路により設定されたデジタル値を変換対象のデジタル値として固定するための複数のヒューズと、前記設定回路から入力されるデジタル値の各ビットのレベルに応じてそれぞれオンオフが制御される複数のスイッチング素子を含み、
前記設定回路により設定されたデジタル値は、前記複数のヒューズのうち1以上のヒューズを切断することにより、前記D/A変換回路における変換対象のデジタル値として固定され、
前記複数のスイッチング素子は、それぞれ前記複数のヒューズのうちのいずれかと直列に接続され、そのオンオフによって各ヒューズの接続または切断の状態が再現され、
前記設定回路は、前記ヒューズの切断に先立って前記複数のスイッチング素子をオンオフ制御するデジタル値を一時的に保持するレジスタをさらに有し、
前記D/A変換回路は、前記複数のヒューズとして、変換すべきデジタル値のビット数と同数のヒューズを含むとともに、前記設定回路により変換対象のデジタル値が設定される前においては、変換すべきデジタル値を、そのデジタル値のビット数で設定できる範囲の中間値となるよう一部のビットの初期値を反転させることを特徴とする電圧生成回路。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003292518A JP4076925B2 (ja) | 2003-08-12 | 2003-08-12 | 電圧生成回路 |
US10/896,341 US7049985B2 (en) | 2003-08-12 | 2004-07-21 | Method and circuit for producing trimmed voltage using D/A converter circuit |
TW093121845A TWI334071B (en) | 2003-08-12 | 2004-07-22 | Circuit and method for producing trimmed voltage using d/a converter circuit |
CNB2004100559765A CN100377020C (zh) | 2003-08-12 | 2004-08-03 | 利用数/模变换电路进行电压微调的电压生成电路和方法 |
KR1020040063164A KR20050016227A (ko) | 2003-08-12 | 2004-08-11 | D/a 변환 회로를 사용하여 전압 트리밍하는 전압 생성회로 및 전압 생성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003292518A JP4076925B2 (ja) | 2003-08-12 | 2003-08-12 | 電圧生成回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005063147A JP2005063147A (ja) | 2005-03-10 |
JP4076925B2 true JP4076925B2 (ja) | 2008-04-16 |
Family
ID=34369838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003292518A Expired - Fee Related JP4076925B2 (ja) | 2003-08-12 | 2003-08-12 | 電圧生成回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7049985B2 (ja) |
JP (1) | JP4076925B2 (ja) |
KR (1) | KR20050016227A (ja) |
CN (1) | CN100377020C (ja) |
TW (1) | TWI334071B (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4670458B2 (ja) * | 2005-04-27 | 2011-04-13 | 株式会社日立製作所 | 半導体装置 |
US7579673B2 (en) * | 2005-08-24 | 2009-08-25 | Nec Electronics Corporation | Semiconductor device having electrical fuse |
US7602327B2 (en) * | 2007-05-08 | 2009-10-13 | Telefonaktiebolaget Lm Ericsson (Publ) | Digitally controllable on-chip resistors and methods |
JP5437871B2 (ja) * | 2010-03-18 | 2014-03-12 | セイコーインスツル株式会社 | 分圧回路及び半導体装置 |
CN101997546B (zh) * | 2010-11-10 | 2013-05-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | 数模转换电路零位和量程参数高精度微调方法 |
EP2487797B1 (en) * | 2011-02-11 | 2014-04-09 | Dialog Semiconductor GmbH | Minimum differential non-linearity trim DAC |
JP6125769B2 (ja) | 2012-07-06 | 2017-05-10 | ローム株式会社 | 半導体装置、液晶表示装置、電子機器 |
JP6111701B2 (ja) * | 2013-01-31 | 2017-04-12 | 株式会社ソシオネクスト | D/a変換器 |
CN103531576B (zh) * | 2013-10-25 | 2016-05-04 | 无锡中感微电子股份有限公司 | 修调电阻控制装置及使用该装置的晶圆测试*** |
CN104750162B (zh) * | 2013-12-31 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | 参考电压产生电路及一种参考电压校准方法 |
US9608586B2 (en) * | 2014-09-25 | 2017-03-28 | Qualcomm Incorporated | Voltage-to-current converter |
CN104407655B (zh) * | 2014-12-01 | 2016-02-24 | 北京机械设备研究所 | 一种调节电阻值的程控方法 |
JP6767732B2 (ja) * | 2015-03-30 | 2020-10-14 | ラピスセミコンダクタ株式会社 | R−2rラダー抵抗回路、ラダー抵抗型d/a変換回路、及び半導体装置 |
KR20180123384A (ko) * | 2017-05-08 | 2018-11-16 | 에스케이하이닉스 주식회사 | 내부 전압을 생성하는 반도체 장치 및 그의 내부 전압 조정 방법 |
CN108551343A (zh) * | 2018-04-04 | 2018-09-18 | 思瑞浦微电子科技(苏州)股份有限公司 | 应用于信号链模拟增益的校准电路及其校准方法 |
CN109586725B (zh) * | 2018-12-22 | 2023-04-28 | 成都华微科技有限公司 | 超高精度r-2r电阻网络开关阵列 |
CN110070971A (zh) * | 2019-05-13 | 2019-07-30 | 深圳市杰普特光电股份有限公司 | 激光调阻*** |
CN113311895A (zh) * | 2021-05-27 | 2021-08-27 | 二十一世纪(北京)微电子技术有限公司 | 一种基于r2r_vdac模块的ldo电路及电子设备 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4689494A (en) * | 1986-09-18 | 1987-08-25 | Advanced Micro Devices, Inc. | Redundancy enable/disable circuit |
JP3175981B2 (ja) * | 1992-10-28 | 2001-06-11 | 株式会社東芝 | トリミング回路 |
JP2000150799A (ja) | 1998-11-17 | 2000-05-30 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
US6307490B1 (en) * | 1999-09-30 | 2001-10-23 | The Engineering Consortium, Inc. | Digital to analog converter trim apparatus and method |
-
2003
- 2003-08-12 JP JP2003292518A patent/JP4076925B2/ja not_active Expired - Fee Related
-
2004
- 2004-07-21 US US10/896,341 patent/US7049985B2/en not_active Expired - Lifetime
- 2004-07-22 TW TW093121845A patent/TWI334071B/zh not_active IP Right Cessation
- 2004-08-03 CN CNB2004100559765A patent/CN100377020C/zh not_active Expired - Lifetime
- 2004-08-11 KR KR1020040063164A patent/KR20050016227A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR20050016227A (ko) | 2005-02-21 |
US20050035890A1 (en) | 2005-02-17 |
CN1581009A (zh) | 2005-02-16 |
CN100377020C (zh) | 2008-03-26 |
JP2005063147A (ja) | 2005-03-10 |
TWI334071B (en) | 2010-12-01 |
US7049985B2 (en) | 2006-05-23 |
TW200508833A (en) | 2005-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4076925B2 (ja) | 電圧生成回路 | |
CN108718196B (zh) | 一种应用于音圈马达驱动芯片的运放失调自校准电路 | |
EP3531559B1 (en) | Current detection circuit, semiconductor device and semiconductor system | |
TWI454062B (zh) | 自我校正的電流源及使用該電流源的數位類比轉換器及其操作方法 | |
US8089380B2 (en) | Voltage mode DAC with calibration circuit using current mode DAC and ROM lookup | |
US20050184896A1 (en) | Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy | |
JP2007024625A (ja) | 電圧測定方法および電圧測定装置 | |
KR100431256B1 (ko) | 디지털/아날로그 변환기 | |
US5134398A (en) | Digital-to-analog converter having a circuit for compensating for variation in output dependent on temperature change | |
JP4140528B2 (ja) | A/d変換装置 | |
JP2015128203A (ja) | 半導体装置 | |
CN114373497A (zh) | 熔丝烧录电路 | |
JP2008515378A (ja) | 間接電流検出を使用する充電方法及び回路 | |
JP4962715B2 (ja) | 終端抵抗調整方法および終端抵抗調整回路 | |
JPH08298462A (ja) | 半導体装置 | |
CN112636755A (zh) | 数模转换器电流源、校准装置、校准***及校准方法 | |
RU2568323C2 (ru) | Цифро-аналоговый преобразователь и способ его калибровки | |
JP3499813B2 (ja) | 電流セル型デジタル・アナログ変換器 | |
JP4898539B2 (ja) | D/aコンバータ及びその動作テスト方法 | |
KR20190046571A (ko) | R-2r 래더를 갖는 디지털-아날로그 변환기 | |
JP3125189B2 (ja) | 複数のしきい電圧を有するメモリのセンシング回路 | |
JP3090098B2 (ja) | 基準電圧発生回路 | |
US6469646B1 (en) | Converting digital signals to analog signals | |
KR20040006416A (ko) | 플래시 메모리 셀의 기준전압 트리밍 방법 및 트리밍 장치 | |
JP2006197052A (ja) | 電流セルマトリクス型da変換器 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060828 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060905 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061031 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070522 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070717 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080129 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080130 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110208 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120208 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120208 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130208 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140208 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |