JP3486421B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はアクティブマトリックス
液晶ディスプレイ等に応用される薄膜トランジスタや三
次元ＬＳＩデバイスなど、絶縁性物質上に作成される薄
膜半導体装置の製造方法に関するもので有る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device formed on an insulating material such as a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display or the like.

【０００２】[0002]

【従来の技術】近年、液晶ディスプレイの大画面化、高
解像度化に伴い、その駆動方式は単純マトリックス方式
からアクティブマトリックス方式へ移行し、大容量の情
報を表示出来るように成りつつ有る。アクティブマトリ
ックス方式は数十万を越える画素を有する液晶ディスプ
レイが可能で有り、各画素毎にスイッチングトランジス
タを形成するもので有る。各種液晶ディスプレイの基板
としては、透過型ディスプレイを可能ならしめる溶融石
英板やガラスなどの透明絶縁基板が使用されている。2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays, the drive system is shifting from the simple matrix system to the active matrix system, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused silica plate or glass that enables a transmissive display is used.

【０００３】しかしながら、表示画面の拡大化や低価格
化を進める場合には絶縁基板として安価な通常ガラスを
使用するのが必要不可欠で有る。従って、この経済性を
維持して尚、アクティブマトリックス方式の液晶ディス
プレイを動作させる薄膜トランジスタを安価なガラス基
板上に安定した性能で形成する事が可能な技術が望まれ
ていた。However, in order to expand the display screen and reduce the price, it is essential to use inexpensive ordinary glass as an insulating substrate. Therefore, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining the economical efficiency.

【０００４】薄膜トランジスタのチャンネル部半導体層
としては、通常アモルファス・シリコンや多結晶シリコ
ンが用いられているが、駆動回路迄一体化して薄膜トラ
ンジスタで形成しようとする場合には動作速度の速い多
結晶シリコンが有利である。Amorphous silicon or polycrystalline silicon is usually used for the channel semiconductor layer of the thin film transistor. However, when the driving circuit is integrated into a thin film transistor, polycrystalline silicon having a high operating speed is used. It is advantageous.

【０００５】従来この様な薄膜トランジスタを作成する
場合、チャンネル部シリコン層を形成した後、ゲート絶
縁層を形成するには基板を酸素（Ｏ₂）、笑気ガス（Ｎ₂
Ｏ）、水蒸気（Ｈ₂Ｏ）などを含む酸化性雰囲気下に挿
入し、その温度を８００℃から１１００℃程度の高温と
してチャンネル部シリコン層の一部を酸化し、ゲート絶
縁層を形成する熱酸化法が用いられていた。一方、多結
晶シリコンを用いた薄膜半導体装置を安価な通常ガラス
基板の使用に耐え得る６００℃程度以下の工程最高温度
で作成するのに種々の方法が試みられている。例えば、
チャンネル部半導体層を減圧気相化学堆積法（ＬＰＣＶ
Ｄ法）で形成した後、ゲート絶縁膜を電子サイクロトロ
ン共鳴プラズマＣＶＤ法（ＥＣＲ−ＰＥＣＶＤ法）に依
り形成し、更に水素プラズマ照射などの水素化処理を施
す方法。或いはチャンネル部半導体層にアモルファス・
シリコン薄膜を堆積し、その後６００℃、２４時間程度
の熱処理を施し、次に常圧気相化学堆積法（ＡＰＣＶＤ
法）にてゲート絶縁膜を形成し、水素化処理を行う方法
などが有る。（Ｊａｐａｎｅｓｅ Ｊ， Ａｐｐｌ，Ｐ
ｈｙｓ，３０Ｌ ８４ '９１）Conventionally, in the case of forming such a thin film transistor, after forming a silicon layer of a channel portion, a substrate of oxygen (O ₂ ) or laughing gas (N ₂ ) is used to form a gate insulating layer.
O), water vapor (H ₂ O), etc., and the temperature is set to a high temperature of about 800 ° C. to 1100 ° C. to oxidize a part of the channel silicon layer to form a gate insulating layer. The oxidation method was used. On the other hand, various methods have been attempted to manufacture a thin film semiconductor device using polycrystalline silicon at a process maximum temperature of about 600 ° C. or less that can withstand the use of an inexpensive ordinary glass substrate. For example,
The channel layer semiconductor layer is formed on the channel layer by low pressure chemical vapor deposition (LPCV).
D method), a gate insulating film is formed by an electron cyclotron resonance plasma CVD method (ECR-PECVD method), and then hydrogenation treatment such as hydrogen plasma irradiation is performed. Or the channel semiconductor layer is amorphous
A silicon thin film is deposited, then heat-treated at 600 ° C. for about 24 hours, and then atmospheric pressure chemical vapor deposition (APCVD).
Method), a gate insulating film is formed, and hydrogenation treatment is performed. (Japane J, Appl, P
hys, 30L 84 '91)

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、先に述
べた従来の方法に於いては、数多くの問題が指摘されて
いる。まず第一に熱酸化法に依るＳｉＯ₂膜の形成で
は、その形成に少なくとも８００℃以上の高温熱処理が
伴う為、酸化膜より下部に位置する薄膜層や基板などの
耐熱性が問題となる。例えば大面積液晶ディスプレイの
スイッチング・トランジスタを作成する場合、基板とし
ては非常に高価な溶融石英板以外はこの様な高温に耐え
得ない。又、三次元ＬＳＩ素子に於いても下層部トラン
ジスタが高温で劣化する為、この熱酸化法は事実上使用
不可能となっている。However, many problems have been pointed out in the above-mentioned conventional methods. First of all, in the formation of a SiO ₂ film by the thermal oxidation method, high temperature heat treatment of at least 800 ° C. or more accompanies the formation thereof, so that the heat resistance of a thin film layer or a substrate located below the oxide film becomes a problem. For example, when making a switching transistor of a large area liquid crystal display, a substrate such as a fused quartz plate, which is very expensive, cannot withstand such a high temperature. Further, even in a three-dimensional LSI device, the lower layer transistor is deteriorated at a high temperature, so that this thermal oxidation method is practically unusable.

【０００７】次にチャンネル部半導体層をＬＰＣＶＤ法
で形成し、ゲート絶縁膜をＥＣＲ−ＰＥＣＶＤ法に依り
形成し、更に水素プラズマ処理を行う方法に於いては移
動度が４〜５cm² ／Ｖ．ｓｅｃと低く、薄膜半導体装置
として未だ不十分で有る。加えて薄膜半導体装置の特性
を向上させる為に行われている水素化処理に依り、薄膜
半導体装置を構成する各種薄膜の一部がエッチングされ
て沢山有る薄膜半導体装置の幾つかが破壊されて仕舞う
と言った問題が有る。又、チャンネル部半導体層にアモ
ルファス・シリコン薄膜を堆積し、その後６００℃程度
の熱処理を施し、ＡＰＣＶＤ法にてゲート絶縁膜を形成
し、更に水素プラズマ照射等の水素化処理を行う方法に
於いては、界面捕獲準位が１０¹²程度と大きく、又デプ
レッション型の半導体装置特性を示すなど、薄膜半導体
装置として未だ不十分で有る。又、先と同様矢張水素化
処理に伴う問題が残り、大面積に均一に且つ安定的に薄
膜半導体装置を作成する事が出来なかった。Next, the channel semiconductor layer is formed by the LPCVD method, the gate insulating film is formed by the ECR-PECVD method, and further the hydrogen plasma treatment is performed, the mobility is 4 to 5 cm ² / V. It is as low as sec, which is still insufficient as a thin film semiconductor device. In addition, due to the hydrogenation process performed to improve the characteristics of the thin film semiconductor device, some of the various thin films forming the thin film semiconductor device are etched and some of the many thin film semiconductor devices are destroyed. There is a problem that I said. In addition, a method of depositing an amorphous silicon thin film on the channel semiconductor layer, then performing a heat treatment at about 600 ° C., forming a gate insulating film by the APCVD method, and further performing a hydrogenation treatment such as hydrogen plasma irradiation. Has a large interface trap level of about 10 ¹² and exhibits depletion type semiconductor device characteristics, and is still insufficient as a thin film semiconductor device. Further, as in the previous case, the problems associated with the Yahari hydrogenation treatment remain, and it has been impossible to uniformly and stably form a thin film semiconductor device over a large area.

【０００８】従って、薄膜半導体装置としては移動度が
大きく、同時に清浄ＭＯＳ界面を有して界面捕獲準位が
低く、且つデプレッションを呈さぬ物が求められて居
り、しかもこうした薄膜半導体装置を作成する工程で水
素化処理の必要が無く、先述の如き良好な薄膜半導体装
置を大面積に均一且つ安定的に作成する製造方法が求め
られていた。Therefore, there is a demand for a thin film semiconductor device having a high mobility, a clean MOS interface, a low interface trap level, and no depletion, and a thin film semiconductor device is manufactured. There has been a demand for a manufacturing method that does not require hydrogenation in the process and can produce a good thin film semiconductor device as described above in a large area uniformly and stably.

【０００９】本発明は上記の事情に鑑みてなされた物
で、その目的とする所はＭＩＳ型薄膜半導体装置に於い
て、工程最高温度が６００℃程度以下と言う低温工程で
良好な半導体装置特性を有する薄膜半導体装置と、この
様な薄膜半導体装置を大面積に渡り均一且つ安定的に製
造する方法を提供する事に有る。The present invention has been made in view of the above circumstances, and its object is to obtain good semiconductor device characteristics in a low temperature process in which the maximum process temperature is about 600 ° C. or less in a MIS thin film semiconductor device. And a method of manufacturing such a thin film semiconductor device uniformly and stably over a large area.

【００１０】[0010]

【課題を解決するための手段】本発明は、６００℃以下
で基板上にシリコン膜を形成する工程と、６００℃以下
の熱処理によって前記シリコン膜の結晶性を高める工程
と、プラズマを照射して前記シリコン膜上に酸化珪素膜
を堆積する工程と、ドナー又はアクセプターとなる不純
物の水素化物気体と水素気体との混合物を原料ガスとし
て、質量非分離型のイオン注入装置により、前記不純物
元素のイオンおよび前記不純物元素の水素化物のイオン
および水素イオンを所定のエネルギーに加速し前記酸化
珪素膜を介して前記シリコン膜に打ち込む工程とを有す
ることを特徴とする。また、前記酸化珪素膜を電子サイ
クロトロン共鳴プラズマＣＶＤ法により形成することを
特徴とする。According to the present invention, a step of forming a silicon film on a substrate at 600 ° C. or lower, a step of increasing the crystallinity of the silicon film by heat treatment at 600 ° C. or lower, and a plasma irradiation are performed. The step of depositing a silicon oxide film on the silicon film and the ion of the impurity element by a mass non-separation type ion implantation apparatus using a mixture of a hydride gas of an impurity serving as a donor or an acceptor and a hydrogen gas as a source gas. And a step of accelerating ions of the hydride of the impurity element and hydrogen ions to a predetermined energy and implanting them into the silicon film through the silicon oxide film. The silicon oxide film is formed by an electron cyclotron resonance plasma CVD method.

【００１１】[0011]

【実施例】以下図面を用いて本発明の実施例を詳述する
が、本発明は以下の実施例に限定されるものでは無い。Embodiments of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following embodiments.

【００１２】（参考例１） 図１（ａ）〜（ｅ）は本参考例１に於ける自己非整合型
スタガード構造のＭＩＳ型電界効果トランジスタを構成
するシリコン薄膜半導体装置の製造工程を断面で示した
図で有る。Reference Example 1 FIGS. 1 (a) to 1 (e) are sectional views showing a manufacturing process of a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-unaligned staggered structure in Reference Example 1. It is the figure shown.

【００１３】本参考例１では、下地基板１０１として２
３５mm□の溶融石英ガラスを用いたが、６００℃の工程
最高温度に耐え得る基板又は下地物質で有るならば、そ
の種類や大きさは無論問われない。例えば通常ガラス基
板の他にシリコンウェハーなどの半導体基板及びそれら
を加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン・
カーバイト、アルミナ、窒化アルミニウムなどのセラミ
ックス基板なども下地基板として可能で有る。In this reference example 1, as the base substrate 101, 2
35 mm square fused silica glass was used, but of course the type and size are not limited as long as it is a substrate or base material that can withstand the maximum process temperature of 600 ° C. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a silicon substrate.
Ceramic substrates such as carbide, alumina, and aluminum nitride can also be used as the base substrate.

【００１４】まずアセトン又はメチル・エチル・ケト
ン、メチル・イソブチル・ケトンやシクロヘキサノンな
どの有機溶剤中に下地基板１０１を浸し、超音波洗浄を
行う。洗浄後、窒素中又は減圧下にて乾燥を施し、更に
エタノールによる超音波洗浄を行った後、窒素バブリン
グされている純水にて水洗を施す。次に、下地基板１０
１を沸騰している濃度６０％の硝酸中に５分間浸し、更
に窒素バブリングされている純水中で洗浄した。基板と
して金属など酸に依り腐食されたり、変質して仕舞う物
質を用いる場合、この硝酸に依る洗浄は必要とされな
い。又この強酸に依る洗浄では、酸として硝酸の他に硫
酸などの可能で有る。First, the base substrate 101 is immersed in an organic solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone, and ultrasonic cleaning is performed. After the cleaning, drying is performed in nitrogen or under reduced pressure, ultrasonic cleaning is further performed with ethanol, and then water cleaning is performed with pure water bubbled with nitrogen. Next, the base substrate 10
1 was immersed in boiling 60% concentration of nitric acid for 5 minutes, and further washed in pure water with nitrogen bubbling. When a substance such as a metal that is corroded by acid or deteriorates and is used as a substrate is used, the cleaning by nitric acid is not required. Further, in the case of washing with this strong acid, sulfuric acid can be used as the acid in addition to nitric acid.

【００１５】こうして洗浄された石英基板上に常圧気相
化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化
硅素膜（ＳｉＯ₂ 膜）１０２を２０００Å堆積した。こ
の下地ＳｉＯ₂ 膜１０２は前述の如き種々多様な物質を
基板として用いる際、後に堆積されるシリコン薄膜の膜
質、及びそれを用いて構成される薄膜トランジスタの性
能を安定化する為に必要で有る。と同時に、例えば基板
１０１として通常ガラスを用いた場合、ガラス中に含ま
れているナトリウムなどの可動イオンが、又基板１０１
として各種セラミック板を用いた際には基板中に添加さ
れている焼結助材原料などがトランジスタ部に拡散混入
するのを防ぐ役割をも演じている。又金属板を基板１０
１として用いる場合は、絶縁性を確保する為に下地Ｓｉ
Ｏ₂ は必要不可欠で有る。又、三次元ＬＳＩ素子では、
トランジスタ間や配線間の層間絶縁膜に相当している。
下地ＳｉＯ₂ 膜１０２堆積時の基板温度は３００℃で、
窒素に依り２０％に希釈されたシラン６００SCCMを８４
０SCCMの酸素と共にＡＰＣＶＤ法で堆積した。この時の
ＳｉＯ₂膜の堆積速度は３．９Å／ｓｅｃで有った。2000 Å of silicon dioxide film (SiO ₂ film) 102 to be a base protection film was deposited on the thus cleaned quartz substrate by atmospheric pressure chemical vapor deposition (APCVD method). The underlying SiO ₂ film 102 is necessary for stabilizing the film quality of a silicon thin film to be deposited later and the performance of a thin film transistor using the same when using various substances as described above as a substrate. At the same time, for example, when ordinary glass is used as the substrate 101, mobile ions such as sodium contained in the glass are also generated in the substrate 101.
Also, when various ceramic plates are used, they also play a role of preventing the sintering aid raw material added to the substrate from diffusing into the transistor section. In addition, the metal plate is the substrate 10
When used as 1, the base Si is used to ensure insulation.
O ₂ is essential. Moreover, in the three-dimensional LSI element,
It corresponds to an interlayer insulating film between transistors and between wirings.
The substrate temperature at the time of depositing the underlying SiO ₂ film 102 is 300 ° C.
84 silane 600 SCCM diluted to 20% with nitrogen
It was deposited by APCVD with 0 SCCM oxygen. At this time, the deposition rate of the SiO ₂ film was 3.9 Å / sec.

【００１６】続いてドナー又はアクセプターとなる不純
物を含んだシリコン薄膜１０３を減圧ＣＶＤ法にて堆積
した。本参考例１ではｎ型トランジスタ作成を目指し不
純物としてリンを選んだが、ｎ型ならばリン以外に５
族、６族の元素、Ｐ型ならばボロンを始めとして２族、
３族の元素が不純物元素として添加され得る。この不純
物を含んだシリコン薄膜１０３はいずれソース・ドレイ
ン領域となる部位で、本参考例１の如く不純物をＣＶＤ
法で添加する方法の他、まず最初に不純物を含まない真
性シリコン膜を形成して居き、後に気相或いは真性シリ
コン膜に接する固相より不純物を拡散させて添加する方
法や、不純物をイオン化して真性シリコン膜に打ち込む
方法などが有る。これら、真性シリコン膜を形成した後
拡散法やイオン打ち込み法で不純物を添加する手法を用
いると真性シリコン膜の所望の部位のみに不純物を添加
する事が可能となり、これにより例えばトランジスタの
ゲート電極端とソース端又はドレイン端が自己整合した
セルフ・アライン・トランジスタが可能となったり、不
純物添加濃度を各部位で変える事に依りシリコン膜中の
電流密度や比抵抗を変えて所望の部位のみに電流を流す
事などが可能となる。本参考例１では不純物としてリン
を選んだ為、ホスフィン（ＰＨ₃ ）とシランを混合した
ガスを用いて、不純物を含んだシリコン薄膜１０３を１
５００Å堆積した。Then, a silicon thin film 103 containing impurities serving as a donor or an acceptor was deposited by a low pressure CVD method. In Reference Example 1, phosphorus was selected as an impurity for the purpose of producing an n-type transistor.
Group 6 and 6 elements, if P type, boron and other groups 2,
Group 3 elements can be added as impurity elements. The silicon thin film 103 containing the impurities is to be a source / drain region at a site, and the impurities are deposited by CVD as in Reference Example 1.
In addition to the method of adding impurities, first, an intrinsic silicon film containing no impurities is formed, and then the impurities are diffused and added from the vapor phase or the solid phase in contact with the intrinsic silicon film. Then, there is a method of implanting into the intrinsic silicon film. By using the method of adding impurities by the diffusion method or the ion implantation method after forming the intrinsic silicon film, it becomes possible to add the impurity only to a desired portion of the intrinsic silicon film. A self-aligned transistor in which the source end or the drain end is self-aligned becomes possible, and the current density or specific resistance in the silicon film is changed by changing the impurity concentration to be changed in each part. It is possible to flush the water. Since phosphorus was selected as the impurity in Reference Example 1, the silicon thin film 103 containing the impurity was formed by using a gas in which phosphine (PH ₃ ) and silane were mixed.
500Å accumulated.

【００１７】本参考例１では１８４．５ｌの容積を有す
る減圧ＣＶＤ炉内にモノシランを２００SCCM、ヘリウム
が９９．５％でホスフィンが０．５％のヘリウム・ホス
フィン混合ガスを６SCCM、更にヘリウム１００SCCMを流
し、堆積温度６００℃、炉内圧力１００mtorr で堆積し
た。この時の堆積速度は２９．６Å／ｍｉｎで、成膜直
後のシート抵抗値は２，０２５Ω／□で有った。In this reference example 1, 200 SCCM of monosilane, 6 SCCM of helium / phosphine mixed gas of 99.5% of helium and 0.5% of phosphine, and 100 SCCM of helium were placed in a low pressure CVD furnace having a volume of 184.5 l. It was flown and deposited at a deposition temperature of 600 ° C. and a furnace pressure of 100 mtorr. The deposition rate at this time was 29.6 Å / min, and the sheet resistance immediately after film formation was 2,025 Ω / □.

【００１８】次に、前記シリコン薄膜上にレジストを形
成し、四弗化炭素（ＣＦ₄ ）と酸素（Ｏ₂） の混合プラ
ズマに依り、前記薄膜をパターニングし、ソース・ドレ
イン領域１０３を形成した（図１（ａ））。続いて沸騰
硝酸中に五分間浸す洗浄で残留レジストなどの不純物を
取り除き、１．６７％弗化水素酸に２０秒浸してソース
・ドレイン領域１０３表面上の自然酸化膜を取り除き、
直ちに減圧ＣＶＤ法でチャンネル部となるシリコン薄膜
を堆積した。Next, a resist is formed on the silicon thin film, and the thin film is patterned by using a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form source / drain regions 103. (FIG. 1 (a)). Then, impurities such as residual resist are removed by washing in boiling nitric acid for 5 minutes, and then immersed in 1.67% hydrofluoric acid for 20 seconds to remove the natural oxide film on the surface of the source / drain region 103.
Immediately, a silicon thin film to serve as a channel portion was deposited by the low pressure CVD method.

【００１９】この時減圧ＣＶＤ反応炉の容積は１８４．
５ｌで、基板は反応炉中央付近に水平に置かれる。原料
ガス及びヘリウム・窒素・アルゴン・水素等の希釈ガス
は必要に応じて反応炉下部より炉内に導入され、反応炉
上部から排気される。石英ガラスで作られた反応炉の外
側には３ゾーンに分かれたヒーターが設置されて居り、
それらを独立に調整する事で反応炉内中央部付近に所望
の温度で均熱帯を形成する。この均熱帯は約３５０mmの
高さで広がり、その範囲内での温度のずれは、例えば６
００℃に設定した時０．２℃以内である。従って挿入基
板間の間隔を１０mmとすれば１バッチで３５枚の基板の
処理が可能で有る。本参考例１では２０mm間隔で１７枚
の基板を均熱帯内に設置した。At this time, the volume of the low pressure CVD reactor is 184.
At 51, the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, hydrogen, etc. are introduced into the furnace from the lower part of the reaction furnace and exhausted from the upper part of the reaction furnace as needed. Outside the reactor made of quartz glass, there are heaters divided into 3 zones,
By adjusting them independently, a soaking zone is formed at the desired temperature near the central part of the reactor. This soaking zone spreads at a height of about 350 mm, and the temperature difference within that range is, for example, 6
When set to 00 ° C, it is within 0.2 ° C. Therefore, if the distance between the inserted substrates is 10 mm, it is possible to process 35 substrates in one batch. In Reference Example 1, 17 substrates were installed in the soaking zone at intervals of 20 mm.

【００２０】排気はロータリーポンプとメカニカル・ブ
ースターポンプを直結して行い、反応炉内の圧力は測定
値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バ
ラトロン・マノメーター）に依り測定した。反応炉を５
５０℃に保って、ガス導入用のバルブを閉じて両ポンプ
にて真空引きを行った場合、反応炉内圧は０ｍｔｏｒｒ
で有る為、背景真空度は悪くとも１０^-4ｔｏｒｒ程度以
下で有る。Exhaust was carried out by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reaction furnace was measured by a diaphragm type pressure gauge (MKS Corp. Baratron Manometer) whose measured value did not depend on the type of gas. 5 reactors
When the temperature of the reactor was kept at 50 ° C and the gas inlet valve was closed and both pumps were evacuated, the reactor internal pressure was 0 mtorr.
Therefore, the background vacuum degree is at most about 10 ⁻⁴ torr.

【００２１】ソース・ドレイン領域１０３が形成され、
該領域表面上の自然酸化膜を取り除かれた基板は、表側
を下向きとして直ちに減圧ＣＶＤ炉内に挿入された。挿
入時の反応炉内温度は３９５℃から４００℃程度に保た
れている。これはソース・ドレイン領域１０３上に自然
酸化膜が形成されるのを極力少なくする為で有るから、
挿入時の反応炉内温度は出来る丈低く有るのが望まし
い。例えば挿入時の反応炉内温度を室温とする事も可能
で有るが、この場合堆積温度迄反応炉内温度を昇温する
のに数時間以上費やし、又堆積後室温に戻すのに矢張り
数時間必要となる。基板挿入時に反応炉内には約４ＳＬ
Ｍ〜１０ＳＬＭの窒素を流し反応炉内を不活性雰囲気に
保っている。更に反応炉内入り口付近には約６ＳＬＭ〜
２０ＳＬＭの窒素で窒素カーテンを形成し、基板挿入時
に空気が反応炉内に流れ込む事を最小限に止めている。
反応炉内に空気中の水分や酸素が入ると、これらは反応
炉内壁のＳｉ層に吸着し、又はＳｉと反応して反応炉内
に残留し、チャンネル部となるシリコン膜堆積の際、脱
ガスとして現れ、堆積シリコン膜の膜品質を低下させる
原因となる。Source / drain regions 103 are formed,
The substrate from which the native oxide film on the surface of the region was removed was immediately inserted into the low pressure CVD furnace with the front side facing downward. The temperature inside the reaction furnace at the time of insertion is kept at about 395 ° C to 400 ° C. This is to reduce the formation of a natural oxide film on the source / drain regions 103 as much as possible.
It is desirable that the temperature inside the reaction furnace at the time of insertion is as low as possible. For example, it is possible to set the temperature in the reaction furnace at the time of insertion to room temperature, but in this case, it takes several hours or more to raise the temperature in the reaction furnace to the deposition temperature, and the number of arrows to return to room temperature after deposition. It takes time. About 4 SL in the reaction furnace when inserting the substrate
Nitrogen of M to 10 SLM is flowed to keep the inside of the reaction furnace in an inert atmosphere. Furthermore, about 6 SLM or more near the entrance of the reactor
A nitrogen curtain is formed with 20 SLM of nitrogen to minimize the flow of air into the reaction furnace when the substrate is inserted.
When moisture and oxygen in the air enter the reaction furnace, they are adsorbed by the Si layer on the inner wall of the reaction furnace or react with Si and remain in the reaction furnace, and are removed during the deposition of the silicon film that becomes the channel part. It appears as a gas and causes deterioration of the film quality of the deposited silicon film.

【００２２】基板挿入後、真空引き、漏洩検査を施し
た。漏洩検査では反応炉に通ずる全バルブを閉じて反応
炉を完全に孤立させて、反応炉内圧力の変化を調べた。
本参考例１では反応炉内温度が４００℃で２分間の完全
孤立後、反応炉内圧力は１ｍｔｏｒｒ以下で有った。漏
洩検査にて異常が無い事を確認した後、反応炉内温度を
挿入温度の４００℃から堆積温度まで昇温する。本参考
例１では５５０℃でチャンネル部となるシリコン薄膜を
堆積した為、昇温するのに一時間費やした。炉内温度が
堆積温度の５５０℃に達するには３５分間程度で済む
が、反応炉壁からの脱ガスを充分放出する為にも、最短
一時間以上、好ましくは数時間の昇温期間が望ましい。
この昇温期間中、二つのポンプは運転状態に有り、少な
くとも純度が９９．９９５％以上の不活性又は還元性ガ
スを流し続ける。これらのガス種は水素・ヘリウム・窒
素・ネオン・アルゴン・キセノン・クリプトン等の純ガ
スの他、これらのガスの混合ガスも可能で有る。本参考
例１では純度９９．９９９９％以上のヘリウムを３５０
SCCM流し続け、反応炉内圧力は８０．７±１．２mtorr
で有った。After inserting the substrate, vacuuming and leakage inspection were performed. In the leak test, all the valves leading to the reactor were closed to completely isolate the reactor, and the change in pressure inside the reactor was examined.
In Reference Example 1, the temperature inside the reaction furnace was 400 ° C. and, after complete isolation for 2 minutes, the pressure inside the reaction furnace was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature inside the reaction furnace is raised from the insertion temperature of 400 ° C. to the deposition temperature. In this reference example 1, since the silicon thin film to be the channel portion was deposited at 550 ° C., it took 1 hour to raise the temperature. It takes about 35 minutes for the temperature in the furnace to reach the deposition temperature of 550 ° C., but in order to sufficiently release the degas from the reaction furnace wall, the temperature rising period of at least 1 hour or more, preferably several hours is desirable. .
During this temperature rising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995%. These gas species can be pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton, and also mixed gases of these gases. In this Reference Example 1, helium having a purity of 99.9999% or more is used as 350
SCCM flow continues, reactor pressure is 80.7 ± 1.2 mtorr
It was.

【００２３】堆積温度到達後、原料ガスで有る所定量の
シラン又はシランと希釈ガスの混合ガスを反応炉内に導
入し、シリコン薄膜１０４を堆積する。希釈ガスとして
は、先の昇温期間に流したガスと同種の組み合わせが可
能で有るが、望ましくは各ガスの純度はそれぞれが９
９．９９９％以上が良い。本参考例１では希釈ガスを用
いず、純度９９．９９９％以上のシランを１００SCCM流
してシリコン薄膜１０４を堆積した。この時、反応炉内
の圧力は反応炉とメカニカル・ブースターポンプの間に
設置されたコンダクタンスバルヴの開閉度を調整して、
３９８．６±１．９mtorr に保った。本参考例１ではチ
ャンネル部となるシリコン薄膜１０４は２１．２Å／ｍ
ｉｎの堆積速度で２４８Åの膜厚に堆積した（図１
（ｂ））。After reaching the deposition temperature, a predetermined amount of silane, which is a source gas, or a mixed gas of silane and a diluent gas is introduced into the reaction furnace to deposit the silicon thin film 104. As the dilution gas, the same kind of combination as the gas that has been flown during the previous temperature rising period can be used, but preferably the purity of each gas is 9
9.999% or more is good. In this reference example 1, a silicon thin film 104 was deposited by using 100 SCCM of silane having a purity of 99.999% or more without using a diluent gas. At this time, the pressure inside the reactor is adjusted by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump.
It was maintained at 398.6 ± 1.9 mtorr. In the first reference example, the silicon thin film 104 that becomes the channel portion is 21.2 Å / m.
It was deposited to a film thickness of 248Å at a deposition rate of in (Fig. 1
(B)).

【００２４】本参考例１ではシリコン薄膜の堆積をＬＰ
ＣＶＤ法で行い、原料ガスもモノシランを用いたが、こ
れ以外にもプラズマＣＶＤ法やＡＰＣＶＤ法やスパッタ
ー法などで堆積する事も可能で有る。又原料ガスもモノ
シランに限らず、ジシランやトリシランなどの高次シラ
ンやジクロールシランなども可能で有る。又、無論上記
種々のＣＶＤ法と上記種々の原料の組み合わせに依って
シリコン薄膜を堆積する事も可能で有る。In this reference example 1, the deposition of the silicon thin film was performed by LP.
Although the CVD method was used and monosilane was used as the source gas, the plasma CVD method, the APCVD method, the sputtering method or the like may be used instead. In addition, the source gas is not limited to monosilane, but higher order silanes such as disilane and trisilane, and dichlorosilane can also be used. Of course, it is also possible to deposit a silicon thin film by a combination of the above various CVD methods and the above various raw materials.

【００２５】次にこうして得られた基板に熱処理を施し
て、シリコン薄膜１０４の結晶化を進め、結晶粒の増大
を行った。熱処理炉は縦型炉で通常４００℃に保持され
て居り、純度９９．９９９％以上の窒素ガスを２０ＳＬ
Ｍ流し続けて、熱処理炉内部を不活性雰囲気に保持して
いる。室温と温度平衡に達している基板は１７分間掛け
て４００℃の縦型熱処理炉に挿入した。挿入後３０分間
４００℃に保ち、基板の位置に依らず炉内が総て４００
℃の均一温度に達した後、熱処理炉の温度を６００℃に
昇温する。この４００℃でまず３０分間保持する事に依
り基板の位置にかかわらず、どこでも同じ熱履歴を得る
事が出来、シリコン薄膜の結晶化を均一に行う事が可能
となる。熱処理炉には常に２０ＳＬＭの窒素が流れ続
け、熱処理炉の容積は約１７６ｌで有るため、この４０
０℃に於ける予備加熱に依り熱処理炉内部は完全に窒素
雰囲気に置換される。４００℃から６００℃への昇温は
約１時間掛けて行われ、６００℃で温度平衡に達した
後、７時間以上の熱処理に依り、シリコン薄膜の結晶化
は進められる。本参考例１では６００℃に達した後２３
時間の熱処理を施した。Next, the substrate thus obtained was subjected to heat treatment to promote crystallization of the silicon thin film 104 and increase the number of crystal grains. The heat treatment furnace is a vertical furnace, which is usually kept at 400 ° C, and nitrogen gas with a purity of 99.999% or more is used for 20 SL.
The flow of M is continued to keep the inside of the heat treatment furnace in an inert atmosphere. The substrate that had reached temperature equilibrium with room temperature was placed in a vertical heat treatment furnace at 400 ° C. for 17 minutes. Keep the temperature at 400 ° C for 30 minutes after insertion, and keep the temperature in the furnace at 400 ° C regardless of the position of the substrate.
After reaching the uniform temperature of ° C, the temperature of the heat treatment furnace is raised to 600 ° C. By holding at 400 ° C. for 30 minutes first, the same thermal history can be obtained anywhere regardless of the position of the substrate, and the crystallization of the silicon thin film can be performed uniformly. Since 20 SLM of nitrogen continues to flow into the heat treatment furnace and the volume of the heat treatment furnace is about 176 l, this 40
Preheating at 0 ° C. completely replaces the inside of the heat treatment furnace with a nitrogen atmosphere. The temperature rise from 400 ° C. to 600 ° C. is performed over about 1 hour, and after reaching the temperature equilibrium at 600 ° C., the crystallization of the silicon thin film proceeds by the heat treatment for 7 hours or more. In this reference example 1, 23 after reaching 600 ° C.
Heat treatment was applied for an hour.

【００２６】こうして得られたシリコン薄膜は、レジス
トでパターニングされた後、四弗化炭素（ＣＦ₄）と酸
素（Ｏ₂）の混合プラズマに依りエッチングされ、チャ
ンネル部シリコン薄膜１０５を形成した。（図１
（Ｃ））本参考例１で形成したシリコン薄膜はＣＦ₄と
Ｏ₂の比が５０SCCM対１００SCCMで有る１５Ｐａの真空
プラズマ放電で、その出力が７００Ｗの時のエッチング
では２．１Å／ｓｅｃのエッチング速度を有していた。The silicon thin film thus obtained was patterned with a resist and then etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form a channel portion silicon thin film 105. (Fig. 1
(C)) The silicon thin film formed in Reference Example 1 was subjected to vacuum plasma discharge of 15 Pa with a ratio of CF ₄ and O ₂ of 50 SCCM to 100 SCCM, and the etching was 2.1 Å / sec when the output was 700 W. Had speed.

【００２７】次にこの基板を沸騰している濃度６０％の
硝酸にて洗浄し、更に１．６７％弗化水素酸水溶液に２
０秒間浸してソース・ドレイン領域１０３とチャンネル
部シリコン薄膜１０５上の自然酸化膜を取り除いて清浄
なシリコン表面が出現した後、直ちに電子サイクロトロ
ン共鳴プラズマＣＶＤ装置（ＥＣＲ−ＰＥＣＶＤ装置）
にてゲート絶縁膜となるＳｉＯ₂ 膜１０６を堆積した。
（図１（ｄ））本参考例１で用いたＥＣＲ−ＰＥＣＶＤ
装置の概要を図２に示す。ゲート絶縁膜堆積に際して
は、２．４５ＧＨＺのマイクロ波が導波管２０１を通じ
て反応室２０２に導かれ、ガス導入管２０３より導入さ
れる１００SCCMの酸素をまずプラズマ化する。この時、
マイクロ波の出力は２２５０Ｗで有り、反応室２０２の
外側に設置された外部コイル２０４に依り反応室２０２
内の酸素プラズマに８７５Ｇａｕｓｓの磁場を掛けてプ
ラズマ中の電子にＥＣＲ条件を満足せしめている。この
酸素プラズマは前記発散磁場に依って反応室外に引き出
され、プラズマに対して垂直に置かれた基板２０５を１
０秒間照射する。基板２０５の背面にはヒーター２０６
が有り、基板全体を１００℃に保っていた。この時反応
室内の圧力は１．８５ｍｔｏｒｒで有った。酸素プラズ
マ引き出し口の直後には別のガス導入管２０７が設けら
れて居り、１０秒間で酸素プラズマが十分安定化した
後、このガス導入管２０７より純度９９．９９９％以上
のシラン６０SCCMを酸素プラズマ中に混入させる。こう
して得られた酸素シラン混合プラズマを３０秒間基板に
照射してゲート絶縁層となるＳｉＯ₂ 膜１０６を１５０
０Å堆積した（図１（ｄ））。この時反応室の圧力は
２．３５ｍｔｏｒｒで有った。Next, this substrate was washed with boiling nitric acid having a concentration of 60%, and further washed with a 1.67% hydrofluoric acid aqueous solution.
Immersion for 0 seconds to remove the native oxide film on the source / drain region 103 and the channel silicon thin film 105 to expose a clean silicon surface, and immediately thereafter, an electron cyclotron resonance plasma CVD device (ECR-PECVD device)
Then, a SiO ₂ film 106 to be a gate insulating film was deposited.
(FIG. 1D) ECR-PECVD used in Reference Example 1
The outline of the apparatus is shown in FIG. At the time of depositing the gate insulating film, a microwave of 2.45 GHZ is guided to the reaction chamber 202 through the waveguide 201, and 100 SCCM of oxygen introduced from the gas introduction pipe 203 is first turned into plasma. At this time,
The microwave output is 2250 W, and the external coil 204 installed outside the reaction chamber 202 allows the reaction chamber 202
By applying a magnetic field of 875 Gauss to the oxygen plasma inside, the electrons in the plasma satisfy the ECR condition. This oxygen plasma is drawn out of the reaction chamber by the divergent magnetic field, and the substrate 205 placed vertically to the plasma is removed.
Irradiate for 0 seconds. A heater 206 is provided on the back surface of the substrate 205.
However, the entire substrate was kept at 100 ° C. At this time, the pressure in the reaction chamber was 1.85 mtorr. Immediately after the oxygen plasma outlet, another gas introducing pipe 207 is provided, and after the oxygen plasma is sufficiently stabilized for 10 seconds, the silane 60SCCM having a purity of 99.999% or more is supplied to the oxygen plasma through the gas introducing pipe 207. Mix in. The substrate thus obtained is irradiated with the oxygen-silane mixed plasma thus obtained for 30 seconds so that the SiO ₂ film 106 serving as a gate insulating layer is formed into 150
0Å was deposited (Fig. 1 (d)). At this time, the pressure in the reaction chamber was 2.35 mtorr.

【００２８】次にクロムをスパッター法で１５００Å堆
積し、パターニングに依り、ゲート電極１０７を形成し
た。この時シート抵抗値は１．３５６±０．０４７Ω／
□で有った。本参考例１ではゲート電極材料としてクロ
ムを用いたが、無論これ以外の導電性物質も可能で有る
し、又その形成方法もスパッター法に限らず蒸着法やＣ
ＶＤ法なども可能で有る。続いてＡＰＣＶＤ法で層間絶
縁膜１０８となるＳｉＯ₂膜を５０００Å堆積した。こ
の堆積は本参考例１で下地ＳｉＯ₂膜１０２を堆積した
条件と全く同一で唯一堆積時間のみを変えて行った。層
間絶縁膜形成後、コンタクトホールを開け、ソース・ド
レイン取り出し電極１０９をスパッター法などで形成
し、トランジスタが完成する（図１（ｅ））。本参考例
１ではソース・ドレイン取り出し電極材料としてアルミ
ニウムを用いスパッター法で８０００Åの膜厚に堆積し
て、ソース・ドレイン取り出し電極を形成した。この時
堆積アルミニウム膜のシート抵抗は４２．４８±２．０
２ｍΩ／□で有った。Next, chrome was deposited 1500 Å by the sputtering method, and the gate electrode 107 was formed by patterning. At this time, the sheet resistance value is 1.356 ± 0.047Ω /
It was □. Chromium was used as the gate electrode material in this reference example 1, but other conductive materials can of course be used, and the formation method is not limited to the sputtering method, and the vapor deposition method or C
VD method and the like are also possible. Then, a SiO ₂ film to be the interlayer insulating film 108 was deposited by 5000 Å by the APCVD method. This deposition was performed under exactly the same conditions as the deposition of the underlying SiO ₂ film 102 in Reference Example 1, except that only the deposition time was changed. After forming the interlayer insulating film, contact holes are opened, and source / drain extraction electrodes 109 are formed by a sputtering method or the like to complete the transistor (FIG. 1E). In this reference example 1, aluminum was used as a source / drain extraction electrode material and deposited by sputtering to a film thickness of 8000Å to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film is 42.48 ± 2.0.
It was 2 mΩ / □.

【００２９】この様にして試作した薄膜トランジスタ
（ＴＦＴ）の特性の一例Ｖｇｓ−Ｉｄｓ曲線を図３の３
−ａに示した。ここでソース・ドレイン電流Ｉｄｓはソ
ース・ドレイン間電圧Ｖｄｓ＝４Ｖ、温度２５℃で測定
した。トランジスタサイズはチャンネル部の長さＬ＝１
０μｍ、幅Ｗ＝１０μｍで有った。Ｖｄｓ＝４Ｖ、Ｖｇ
ｓ＝１０Ｖでトランジスタをオンさせた時のオン電流は
２３５mm□の基板の中央と四角の５ヶのトランジスタを
測定した所、ＩON＝４．６５±０．３９μＡと良好なト
ランジスタ特性を有する薄膜半導体装置が得られた。
又、トランジスタの飽和電流領域より求めた電界効果移
動μｏと捕獲密度Ｎｔ（Ｊ．Ｌｅｖｉｎｓｏｎ ｅｔ
ａｌ． Ｊ．Ａｐｐｌ．Ｐｈｙｓ ５３．１１９３．１
９８２）はそれぞれμｏ＝２５．８５±０．９６cm² ／
ｖ．ｓｅｃ、Ｎｔ＝（６．８１±０．１５）×１０¹¹１
／cm² で有った。図３の３−ｂには比較の為に従来技術
の一例に依って作成した薄膜半導体装置のトランジスタ
特性を図示した。即ち、チャンネル部シリコン薄膜を減
圧ＣＶＤ法にて６００℃で堆積し、２４時間の熱処理を
施さぬ他は総て本参考例１と同一の工程で薄膜半導体装
置を作成したもので有る。この時、減圧ＣＶＤ法でチャ
ンネル部シリコン薄膜を堆積する装置は本参考例１で用
いた装置と同一で有り、原料ガスのモノシランは１２．
５SCCM流し、反応炉内圧力は９．０ｍｔｏｒｒ、堆積速
度は１１．７５Å／ｍｉｎで２５６Åの膜厚に堆積し
た。この従来技術の一例のＴＦＴのオン電流はＩｄｓ＝
０．９１±０．１２μＡで電界効果移動度はμｏ＝４．
７５±０．２０cm² ／ｖ．ｓｅｃ、捕獲密度Ｎｔ＝
（５．１８±０．１３）×１０¹¹１／cm² で有った。こ
の他に、チャンネル部シリコン薄膜を同様に減圧ＣＶＤ
法にて６００℃モノシラン流量１２．５SCCMにて堆積
し、本参考例１と同一の工程でゲート絶縁膜を堆積した
後、ＥＣＲ−ＰＥＣＶＤ装置にて水素プラズマ処理を施
し、それ以外は本参考例１と同一工程で薄膜半導体装置
を作成した。これも水素化処理を行う従来技術の一例で
有る。水素化処理は図２に示したＥＣＲ−ＰＥＣＶＤ装
置にてゲート絶縁膜堆積後、真空引きを行い、更にヒー
ター２０６により基板２０５の温度を３００℃に１時間
掛けて昇温した後に行った。純度９９．９９９９％以上
の水素ガス１２５SCCMはガス導入管２０３より反応室２
０２に導かれ、水素プラズマを立てた。マイクロ波出力
は２０００Ｗで、反応室の圧力は２．６３ｍｔｏｒｒで
有った。水素プラズマ照射は３０分間行った。こうして
作成した薄膜半導体装置のＴＦＴ特性を測定した所、オ
ン電流Ｉｄｓ＝０．９６±０．１３μＡ、電界効果移動
度μｏ＝４．６８±０．２２cm² ／ｖ．ｓｅｃ、捕獲密
度Ｎｔ＝（５．１２±０．１３）×１０¹¹１／cm² で有
った。即ち、水素プラズマ処理の有無にかかわらずチャ
ンネル部シリコン膜を６００℃にて減圧ＣＶＤ法で堆積
する従来技術に比べると、本発明では例えば電界効果移
動度を５倍程度に高めるとのトランジスタ特性の大幅な
向上をもたらす。An example of the characteristics of the thin film transistor (TFT) prototyped in this manner is shown by the Vgs-Ids curve in FIG.
-A. Here, the source-drain current Ids was measured at a source-drain voltage Vds = 4V and a temperature of 25 ° C. Transistor size is channel length L = 1
The width was 0 μm and the width W was 10 μm. Vds = 4V, Vg
The on-current when the transistor was turned on at s = 10V was measured on five transistors in the center and square of the 235 mm square substrate, and ION = 4.65 ± 0.39 μA. A thin film semiconductor with good transistor characteristics. The device is obtained.
Also, the field effect transfer μo and the trap density Nt (J. Levinson et.
al. J. Appl. Phys 53 . 1193.1
982) is μo = 25.85 ± 0.96 cm ² /
v. sec, Nt = (6.81 ± 0.15) × 10 ¹¹ 1
It was / cm ² . For comparison, 3-b in FIG. 3 shows the transistor characteristics of a thin film semiconductor device manufactured according to an example of the conventional technique. That is, a thin film semiconductor device was prepared by the same steps as those in Reference Example 1 except that the channel portion silicon thin film was deposited at 600 ° C. by the low pressure CVD method and the heat treatment was not performed for 24 hours. At this time, the apparatus for depositing the channel silicon thin film by the low pressure CVD method is the same as the apparatus used in this reference example 1, and the source gas monosilane is 12.
5 SCCM was flown, the pressure in the reaction furnace was 9.0 mtorr, and the deposition rate was 11.75 Å / min. The on-current of the TFT in this example of the prior art is Ids =
At 0.91 ± 0.12 μA, the field effect mobility is μo = 4.
75 ± 0.20 cm ² / v. sec, capture density Nt =
It was (5.18 ± 0.13) × 10 ¹¹ 1 / cm ² . In addition to this, the silicon thin film in the channel portion is similarly subjected to low pressure CVD.
Method, 600 ° C. monosilane flow rate 12.5 SCCM, and a gate insulating film is deposited in the same process as in Reference Example 1, and then hydrogen plasma treatment is performed by an ECR-PECVD apparatus. A thin film semiconductor device was produced in the same process as 1. This is also an example of a conventional technique for performing hydrotreating. The hydrogenation treatment was performed after the gate insulating film was deposited by the ECR-PECVD apparatus shown in FIG. 2 and then evacuated, and then the temperature of the substrate 205 was raised to 300 ° C. for 1 hour by the heater 206. 125 SCCM of hydrogen gas with a purity of 99.9999% or higher is fed into the reaction chamber 2 through the gas introduction pipe 203.
02, the hydrogen plasma was set up. The microwave power was 2000 W and the pressure in the reaction chamber was 2.63 mtorr. Hydrogen plasma irradiation was performed for 30 minutes. When the TFT characteristics of the thin film semiconductor device thus prepared were measured, the on-current Ids = 0.96 ± 0.13 μA and the field effect mobility μo = 4.68 ± 0.22 cm ² / v. sec, the trap density Nt = (5.12 ± 0.13) × 10 ¹¹ 1 / cm ² . That is, in the present invention, for example, in comparison with the prior art in which the channel silicon film is deposited by the low pressure CVD method at 600 ° C. regardless of the presence or absence of the hydrogen plasma treatment, the field effect mobility is increased by about 5 times. Bring significant improvements.

【００３０】次に従来技術の別な一例と本発明との比較
を行う。即ち従来技術の別な一例として、チャンネル部
シリコン薄膜の形成は本参考例１と同様に行うものの、
ゲート絶縁膜をＡＰＣＶＤ法で堆積する従来技術及びゲ
ート絶縁膜をＡＰＣＶＤ法で堆積した後、水素プラズマ
処理を行う従来技術に対する本発明の多大なる優位性を
見る。従来技術で有るゲート絶縁膜をＡＰＣＶＤ法で堆
積して薄膜半導体装置を作成する工程では、ゲート絶縁
膜をＡＰＣＶＤ法で１５００Åに堆積した以外、本参考
例１と同一の工程で薄膜半導体装置を作成した。ＡＰＣ
ＶＤ法では基板温度を３００℃に保ち、窒素中に２０％
シランを含んだ窒素、シラン混合ガスを３００SCCM、酸
素を４２０SCCM流し、約１４０ＳＬＭの希釈用窒素をこ
れらの原料ガスと共に流してＳｉＯ₂膜を堆積した。堆
積速度は１．８５Å／ｓｅｃで有った。この様にして作
成した従来技術による薄膜半導体装置のトランジスタ特
性を図３の３−Ｃに示した。このトランジスタのオン電
流はＩON＝１．４９±０．０５μＡ、電界効果移動度μ
ｏ＝２４．６０±０．７２cm²／ｖ・ｓｅｃ、捕獲密度
Ｎｔ＝（９．２０±０．１５）×１０¹¹１／cm² で有っ
た。この従来技術と本発明を比較すると、本発明は捕獲
準位を大幅に低減し、ゲート電圧Ｏｖ付近で急激に立ち
上がる極めて優良な薄膜半導体装置を作成した事が明瞭
となる。ＡＰＣＶＤ法でゲート絶縁膜を堆積する従来技
術では、移動度丈は本発明並に高める事が出来たが、そ
の実、ソース・ドレイン電流の最小値が−１１ｖ付近に
有り捕獲密度も高い為、立ち上がりの傾斜もゆるやかで
薄膜半導体装置として実用的ではなかった。一方更に別
なる従来技術の一例を図３の３−ｄに示す。ここではチ
ャンネル部シリコン薄膜の形成は本参考例１と同様に行
うものの、ゲート絶縁膜はＡＰＣＶＤ法で堆積し、その
後水素プラズマ処理を施す技術で有る。ゲート絶縁膜を
前述と同一の条件で堆積し、その後直ちにＥＣＲ−ＰＥ
ＣＶＤ装置により前述と同一の条件で水素プラズマ照射
を施した他は本参考例１と同一の工程を経て薄膜半導体
装置を作成した。こうして得られたＴＦＴの特性を図３
の３−ｄに示した。オン電流はＩｄｓ＝２．９１±０．
３０μＡ、電界効果移動度μｏ＝２４．５１±０．６７
cm² ／ｖ・ｓｅｃ、捕獲密度Ｎｔ＝（７．９４±０．１
５）×１０¹¹１／cm² で有った。このプラズマ処理を用
いた従来技術に比較しても本発明はあらゆるパラメータ
ーで良好な特性を示している事が分かる。又水素プラズ
マ処理を施した従来技術で作成したトランジスタでは測
定した５つのトランジスタの内１つが＋２Ｖ程度しきい
値電圧Ｖｔｈがずれており、前述の各パラメーターの平
均値と標準偏差の値にこのトランジスタの値を含ませて
いない。即ち水素プラズマ処理を用いた従来技術では水
素プラズマ処理を行わない従来技術に対してトランジス
タ特性は改善されるが、大面積に均一に同質なトランジ
スタを作成する事は困難で有った。加えて水素プラズマ
処理を施した試料はロット間の変動が大きく、安定的な
生産が困難で有る。とりわけ、しきい値電圧のずれとソ
ース・ドレイン電流が最小となるゲート電圧値の変動が
ロット間で非常に大きい。これに対して本発明に依り、
ばらつきの原因となる水素化処理を排除して尚、従来よ
りも優良なトランジスタを大面積上に均一に作成し得た
事が分かる。Next, another example of the prior art will be compared with the present invention. That is, as another example of the prior art, although the formation of the channel portion silicon thin film is performed in the same manner as in Reference Example 1,
We will see a great advantage of the present invention over the prior art of depositing a gate insulating film by APCVD and the prior art of depositing a gate insulating film by APCVD followed by hydrogen plasma treatment. In the conventional process of depositing a gate insulating film by the APCVD method to create a thin film semiconductor device, the thin film semiconductor device is produced by the same process as in Reference Example 1 except that the gate insulating film is deposited at 1500Å by the APCVD method. did. APC
In the VD method, the substrate temperature is kept at 300 ° C, and 20% in nitrogen
Nitrogen containing silane, a silane mixed gas of 300 SCCM and oxygen of 420 SCCM were flowed, and about 140 SLM of diluting nitrogen was flowed together with these source gases to deposit a SiO ₂ film. The deposition rate was 1.85Å / sec. Transistor characteristics of the thin film semiconductor device according to the conventional technique thus produced are shown in 3-C of FIG. The on-current of this transistor is ION = 1.49 ± 0.05 μA, field effect mobility μ
o = 24.60 ± 0.72 cm ² / v · sec, and trap density Nt = (9.20 ± 0.15) × 10 ¹¹ 1 / cm ² . Comparing the present invention with this prior art, it becomes clear that the present invention has produced a very good thin film semiconductor device in which the trap level is significantly reduced and which rises sharply near the gate voltage Ov. In the conventional technique of depositing the gate insulating film by the APCVD method, the mobility can be increased as much as in the present invention, but in fact, the minimum value of the source / drain current is around -11v and the trap density is high, so The slope of was also not practical as a thin film semiconductor device. On the other hand, an example of another conventional technique is shown in 3-d of FIG. Here, although the channel portion silicon thin film is formed in the same manner as in Reference Example 1, this is a technique in which the gate insulating film is deposited by the APCVD method and then subjected to hydrogen plasma treatment. A gate insulating film is deposited under the same conditions as described above, and immediately thereafter, ECR-PE is performed.
A thin film semiconductor device was produced through the same steps as in Reference Example 1 except that the hydrogen plasma irradiation was performed by the CVD apparatus under the same conditions as described above. The characteristics of the TFT thus obtained are shown in FIG.
3-d. The on-current is Ids = 2.91 ± 0.
30 μA, electric field effect mobility μo = 24.51 ± 0.67
cm ² / v · sec, capture density Nt = (7.94 ± 0.1
5) It was × 10 ¹¹ 1 / cm ² . It can be seen that the present invention exhibits good characteristics in all parameters even when compared with the conventional technique using this plasma treatment. Also, in the transistor manufactured by the prior art that has been subjected to the hydrogen plasma treatment, one of the five transistors measured has a deviation of the threshold voltage Vth by about + 2V. The value of is not included. That is, the conventional technique using the hydrogen plasma treatment improves the transistor characteristics as compared with the conventional technique in which the hydrogen plasma treatment is not performed, but it is difficult to form a uniform transistor in a large area uniformly. In addition, the samples subjected to hydrogen plasma treatment have large lot-to-lot variations, making stable production difficult. In particular, the shift of the threshold voltage and the variation of the gate voltage value that minimizes the source / drain current are very large between lots. On the other hand, according to the present invention,
It can be seen that the transistor which is superior to the conventional one can be uniformly formed on a large area by eliminating the hydrogenation process that causes the variation.

【００３１】（参考例２） チャンネル部となるシリコン薄膜（図１．１０４）の堆
積時間を変えてシリコン薄膜１０４の堆積膜厚を変えた
他は総て参考例１と同じ工程に依り薄膜半導体装置を作
成した。本参考例２ではシリコン薄膜１０４を１９０
Å、２８０Å、５１５Å、１０００Å、１１００Å、１
６４５Åと六種の異なった膜厚とし、それぞれ薄膜半導
体装置を作成した。こうして得られた薄膜半導体装置の
オン電流とオフ電流の比をチャンネル部シリコン膜の膜
厚に対して図示した結果が図４で有る。この図から分か
る様にチャンネル部シリコン膜半導体層の膜厚が５００
Å以下となる薄膜半導体装置ではオン・オフ比が急激に
改善されて７桁以上を示す良好な特性が得られた。Reference Example 2 A thin film semiconductor was manufactured by the same steps as in Reference Example 1 except that the deposition time of the silicon thin film (FIG. 1.104) to be the channel portion was changed to change the deposited film thickness of the silicon thin film 104. Created the device. In this reference example 2, the silicon thin film 104 is set to 190
Å, 280 Å, 515 Å, 1000 Å, 1100 Å, 1
645Å and six different film thicknesses were formed, and thin film semiconductor devices were prepared. FIG. 4 shows the result of the ratio of the on-current and the off-current of the thin film semiconductor device thus obtained plotted against the film thickness of the channel portion silicon film. As can be seen from this figure, the film thickness of the channel silicon film semiconductor layer is 500.
In the thin film semiconductor device having a thickness of Å or less, the on / off ratio was drastically improved, and good characteristics of 7 digits or more were obtained.

【００３２】（参考例３） ソース領域或いはドレイン領域の少なくともどちらか一
方の領域がゲート絶縁膜を介してゲート電極と重なり合
っていない構造を有する薄膜半導体装置（オフ・セット
型薄膜半導体装置）を参考例１と同一の製造方法にて作
成した。本参考例３ではオフ・セット型薄膜半導体装置
として図５（ａ）に示すスタガード型薄膜半導体装置を
アラインメントを高精度に行う事に依り作成したが、オ
フ・セット型薄膜半導体装置としては無論これ以外の構
造の物も可能で有る。例えば図５（ｂ）に示すようにソ
ース・ドレイン領域５０３を真性シリコン薄膜にゲート
電極５０４をマスクとして不純物イオンを打ち込んで作
成する方法や図５（ｃ）に示すゲート電極５０５が下側
に有る逆スタガード型薄膜半導体装置でソース・ドレイ
ン領域５０７をマスク材５０６を用いて作成した物など
も可能で有る。Reference Example 3 Reference is made to a thin film semiconductor device (off-set type thin film semiconductor device) having a structure in which at least one of a source region and a drain region does not overlap with a gate electrode through a gate insulating film. It was prepared by the same manufacturing method as in Example 1. In this reference example 3, the staggered thin film semiconductor device shown in FIG. 5A was prepared as an off-set thin film semiconductor device by performing alignment with high accuracy. Other structures are possible. For example, as shown in FIG. 5B, the source / drain region 503 is formed by implanting impurity ions in the intrinsic silicon thin film using the gate electrode 504 as a mask, and the gate electrode 505 shown in FIG. 5C is on the lower side. It is also possible to use an inverted staggered thin film semiconductor device in which the source / drain regions 507 are formed using the mask material 506.

【００３３】本参考例３では下地基板として直径７５mm
の溶融石英ガラスを用いた他は参考例１と同じ製造方法
でオフ・セット型薄膜半導体装置を作成した。即ち、ま
ず基板洗浄を施し、下地ＳｉＯ₂ 膜をＡＰＣＶＤ法など
で堆積した後、リン添加されたシリコン膜をＬＰＣＶＤ
法で堆積し、更にパターニングする事に依りソース・ド
レイン領域５０１を形成した。ここで後にチャンネル長
Ｌとなるソース・ドレイン領域間距離は１０．５μｍで
有った。次に参考例１と同様にしてチャンネル部となる
シリコン薄膜を２１．２Å／ｍｉｎの堆積速度で２４８
Åの膜厚に堆積した。但し、参考例１では基板の表側を
下向きとして基板を反応炉に挿入したが、本参考例３で
は２３５mm□のダミー石英板上に直径７５mmの基板を表
側を上向きに乗せて、反応炉に挿入した。以下参考例１
と全く同じ製造方法で熱処理を施し、ゲート絶縁層を堆
積し、更にゲート電極５０２を形成した。このゲート電
極５０２の幅は１０．０μｍで、ソース・ドレイン間距
離１０．５μｍの中心とゲート電極幅１０．０μｍの中
心が一致するように高精度アラインメントを行った。こ
の結果、チャンネル領域に於けるゲート電極端位置とソ
ース領域端との距離（オフセット距離）はそれぞれ０．
２５μｍとなる。その後参考例１と同様の製造方法で層
間絶縁膜を堆積し、コンタクト・ホール開口後アルミニ
ウムを用いて配線し、薄膜半導体装置が完成した。In this reference example 3, the diameter of the base substrate is 75 mm.
An off-set type thin film semiconductor device was prepared by the same manufacturing method as in Reference Example 1 except that the fused silica glass in Example 1 was used. That is, first, the substrate is washed, a base SiO ₂ film is deposited by the APCVD method or the like, and then a phosphorus-added silicon film is LPCVD-deposited.
Then, the source / drain regions 501 are formed by depositing by the method and further patterning. Here, the distance between the source and drain regions, which later becomes the channel length L, was 10.5 μm. Then, in the same manner as in Reference Example 1, a silicon thin film serving as a channel portion was deposited at a deposition rate of 21.2Å / min for 248
Deposited to a film thickness of Å. However, in Reference Example 1, the substrate was inserted into the reaction furnace with the front side facing down, but in Reference Example 3, the substrate with a diameter of 75 mm was placed on the 235 mm square dummy quartz plate with the front side facing upward and inserted into the reaction furnace. did. Reference example 1 below
A heat treatment was performed by the same manufacturing method as above, a gate insulating layer was deposited, and a gate electrode 502 was further formed. The width of the gate electrode 502 was 10.0 μm, and high precision alignment was performed so that the center of the source-drain distance of 10.5 μm and the center of the gate electrode width of 10.0 μm coincided with each other. As a result, the distance (offset distance) between the end position of the gate electrode and the end of the source region in the channel region is 0.
It becomes 25 μm. After that, an interlayer insulating film was deposited by the same manufacturing method as in Reference Example 1, a contact hole was opened, and wiring was performed using aluminum to complete a thin film semiconductor device.

【００３４】この様にして作成した薄膜半導体装置のト
ランジスタ特性の一例Ｖｇｓ−Ｉｄｓ曲線を図６の６−
ａに示した。図６の３−ａは参考例１で試作した自己非
整合型スタガード構造薄膜半導体装置のトランジスタ特
性で有る。図からも明確に分かる様に本参考例３ではゲ
ート電圧が負の時に生じるリーク電流を大幅に低下させ
る事が可能で有る。実際本参考例３に於いてはゲート電
圧が−２．５Ｖ以下ではソース・ドレイン電流を０．１
ｐＡ程度に押さえている。図６の６−ｂは参考例１の従
来技術に依りオフセット型薄膜半導体装置を作成した時
に得られるトランジスタ特性を比較の為に示している。
即ち、チャンネル部シリコン薄膜は６００℃の減圧ＣＶ
Ｄ法で堆積され、ソース・ドレイン間距離１０．５μｍ
の中心とゲート電極幅１０．０μｍの中心を高精度アラ
インメントで位置合わせしオフセット型薄膜半導体装置
を作成した時に得られるトランジスタ特性で有る。これ
故図６の６−ｂは従来技術の自己非整合型スタガード構
造薄膜半導体装置のトランジスタ特性図６の３−ｂと直
接比較し得る。従来技術に依るオフ・セット型薄膜半導
体装置に於いてもリーク電流を０．１ｐＡ程度以下に低
く保つ事は可能で有るが、従来技術に於いてオフセット
型薄膜半導体装置を作成するとオン電流や移動度などト
ランジスタの正特性も低下して仕舞い、実用的では無か
った。例えば従来技術に依るオフセット型薄膜半導体装
置のオン電流はＩｄｓ＝０．０９０±０．０１μＡと自
己非整合型薄膜半導体装置に比べてオン電流は一桁以上
低下して仕舞う。又この時の移動度もμｏ＝３．３３±
０．１５cm² ／ｖ・ｓｅｃと同様に約３割劣化してい
る。この理由に依り、従来技術に依るオフセット型薄膜
半導体装置の製造はその価値が無かった。これに対し、
本参考例３は図６の６−ａに示されている通り、リーク
電流は低く押さえ、且つオン電流も高く維持している。
本参考例３ではオン電流としてＩｄｓ＝３．７１±０．
４３μＡが得られ、自己非整合型薄膜半導体装置のオン
電流に比べても殆ど遜色は見られない。又本参考例３で
は移動度もμｏ＝２２．００±０．９５cm²／ｖ・ｓｅ
ｃと良好な値を示した。An example of the transistor characteristics of the thin film semiconductor device thus prepared is shown in FIG. 6 by the Vgs-Ids curve.
shown in a. 6A shows transistor characteristics of the self-unaligned staggered structure thin film semiconductor device manufactured as a prototype in Reference Example 1. FIG. As is clear from the figure, in Reference Example 3, it is possible to significantly reduce the leak current generated when the gate voltage is negative. In fact, in Reference Example 3, the source / drain current is 0.1 when the gate voltage is −2.5 V or less.
It is suppressed to about pA. 6-b of FIG. 6 shows, for comparison, transistor characteristics obtained when an offset type thin film semiconductor device is manufactured according to the conventional technique of Reference Example 1.
That is, the silicon thin film in the channel part is a reduced pressure CV of 600 °
Deposited by D method, source-drain distance 10.5 μm
And the center of the gate electrode width of 10.0 μm are aligned with high precision alignment to produce an offset type thin film semiconductor device. Therefore, 6-b of FIG. 6 can be directly compared with 3-b of FIG. 6 of the transistor characteristics of the conventional self-unaligned staggered thin film semiconductor device. Even in the off-set type thin film semiconductor device according to the conventional technology, it is possible to keep the leakage current as low as about 0.1 pA or less. The positive characteristics of the transistor, such as frequency, have also deteriorated, and it has been impractical. For example, the on-current of the offset type thin film semiconductor device according to the conventional technique is Ids = 0.090 ± 0.01 μA, which is one or more digits lower than that of the self-unmatched thin film semiconductor device. The mobility at this time is also μo = 3.33 ±
Similar to 0.15 cm ² / v · sec, it is deteriorated by about 30%. For this reason, the manufacturing of offset type thin film semiconductor devices according to the prior art was not worth it. In contrast,
In Reference Example 3, as shown by 6-a in FIG. 6, the leak current is kept low and the on-current is kept high.
In this reference example 3, the on-current is Ids = 3.71 ± 0.
43 μA is obtained, which is almost comparable to the on-current of the self-non-matching type thin film semiconductor device. Further, in Reference Example 3, the mobility is also μo = 22.00 ± 0.95 cm ² / v · se
It showed a good value of c.

【００３５】（実施例１） 参考例３では高精度アラインメントを行う事に依りオフ
セット型薄膜半導体装置を作成したが、図５（ｂ）では
真性シリコン膜を堆積し、ゲート電極をパターニングし
た後、不純物イオンを添加する事でオフセット型薄膜半
導体装置を作成した。この方法について詳述する。Example 1 In Reference Example 3, an offset type thin film semiconductor device was produced by performing high precision alignment. In FIG. 5B, an intrinsic silicon film is deposited and a gate electrode is patterned, An offset type thin film semiconductor device was prepared by adding impurity ions. This method will be described in detail.

【００３６】図７（ａ）〜（ｄ）は本実施例１に於ける
オフセット型スタガード構造のＭＩＳ型電界効果トラン
ジスタを構成するシリコン薄膜半導体装置の構造工程を
断面で示した図で有る。まず参考例１と同様基板７０１
を洗浄した後、下地保護膜７０２としてＳｉＯ₂ 膜を２
０００Å程度堆積する。続いて第一のシリコン膜を３０
０Å程度以上堆積し、パターニングを行う事でパッドと
なるシリコン膜７０３を形成する。この第一のシリコン
膜として本実施例２では参考例１でチャンネル部シリコ
ン膜を堆積したＬＰＣＶＤ装置を用いて堆積温度６００
℃シラン流量１２．５SCCMで１２５０Åに堆積したが、
これ以外にも同じＬＰＣＶＤ装置を用いて堆積温度５５
０℃程度でシリコン膜を堆積する事も、原料ガスとして
ジシラン（Ｓｉ₂Ｈ₆）を用いて堆積温度４５０℃程度で
堆積する事も、ＰＥＣＶＤ法にて２５０℃程度でシリコ
ン膜を堆積する事も可能で有る。工程最高温度６００℃
を越えぬ膜形成温度で有るならば、如何なる方法であっ
ても構わない。次に第二のシリコン膜７０４を堆積する
が、この第二のシリコン膜の膜厚が３００Å程度以上有
り、不純物注入後のソース・ドレイン領域の抵抗値がト
ランジスタを動作させた時のチャンネル領域の抵抗値に
比べて充分低ければ、第一のシリコン膜又はパッドとな
るシリコン膜７０３は必要とされない。本実施例１では
第二のシリコン膜７０４を参考例１でチャンネル部とな
るシリコン薄膜と同じ方法で堆積した。即ちＬＰＣＶＤ
法にてモノシランを原料ガスとし、堆積温度５５０℃、
シラン流量１００SCCM堆積速度２１．２Å／ｍｉｎで２
５０Åの膜厚に堆積した。しかし、第二のシリコン膜形
成方法は第一のシリコン膜と同様、工程最高温度６００
℃を越えぬ膜形成温度で有るならば、如何なる方法でも
可能で有る。例えば、第二のシリコン膜も堆積温度６０
０℃、シラン流量１２．５SCCM、反応炉内圧力９．０mt
orrで堆積しても構わぬし、又、原料ガスにジシランや
トリシランなどの高次シランを用いて更に低温で膜形成
する事も可能で有る。この様に何らかの方法で第二のシ
リコン膜７０４を形成し（図７（ｂ））、パターニング
を行った後、参考例１と同様の方法でゲート絶縁層７０
５を形成した。即ち、ＥＣＲ−ＰＥＣＶＤ法でＳｉＯ₂
膜を１５００Å堆積した。ゲート絶縁層７０５の形成手
段としては第二のシリコン膜７０４が多結晶シリコン膜
である場合、ＡＰＣＶＤ法で形成する事も出来る。次に
ゲート電極となる金属膜などを形成する。本実施例１で
はゲート電極材料として燐を高濃度に添加したシリコン
膜を用いた。ここではＬＰＣＶＤ法で堆積温度６００
℃、モノシラン２００SCCM、ヘリウムが９９．５％でホ
スフィンが０．５％のヘリウム・ホスフィン混合ガスを
６SCCM更にヘリウム１００SCCMを流し、炉内圧力１００
mtorr で３０００Åの膜厚に堆積した。成膜直後のシー
ト抵抗値は７４４Ω／□で有った。引き続いてレジスト
を塗布し、レジストのパターニングを行った後、ＣＦ₄
とＯ₂の混合プラズマに依り燐添加シリコン膜のパター
ニングを行った。ＣＦ₄とＯ₂の比がそれぞれ２００SCCM
と２００SCCMで入射波出力７００Ｗでパターニングを行
った。この時の燐添加シリコン膜のエッチング速度は１
５．４Å／ｓｅｃで５分５７秒間エッチングを行い、ゲ
ート電極７０６を作成した。燐添加シリコン膜の膜厚は
３０００Åで有ったので、このプラズマエッチングに依
り、ゲート電極幅はレジスト７０７に比べて左右それぞ
れ２５００Å程度細められている（図７（ｃ））。次に
ゲート電極７０６作成に用いたレジスト７０７を剥離せ
ずに残したまま、不純物イオンを添加する。本実施例１
では不純物として燐を選びｎ型薄膜半導体装置を目指し
たが、無論他元素もその目的に応じて可能で有る。本実
施例１では質量分析装置が付いていないイオン打ち込み
装置を用いて不純物イオン添加を施した。原料ガスとし
て水素中に希釈された濃度５％のホスフィンを用い、加
速電圧１１０ｋＶで３×１０¹⁵１／cm² の濃度に打ち込
んだ。この様にして、第一のシリコン膜と第二のシリコ
ン膜の一部はソース・ドレイン領域７０８となり、又ゲ
ート電極作成に用いたレジスト７０７は膜厚がおよそ２
μｍ程度有るため、この下に位置する第二のシリコン膜
はイオン添加されず、チャンネル部７０９を構成するに
至る（図７（ｃ））。又、この方法に依り、オフセット
型薄膜半導体装置が作成される。次にゲート電極作成用
レジスト７０７を剥離した後、該基板に６００℃で７時
間以上の熱処理を施し、添加不純物イオンの活性化及
び、チャンネル部シリコン膜７０９の結晶性が不充分な
場合の結晶化を促進する。本実施例１では参考例１で行
った熱処理と同様窒素雰囲気下６００℃にて２３時間の
熱処理を施した。続いて層間絶縁膜としてＳｉＯ₂ ７１
０をＡＰＣＶＤ法などで５０００Å堆積し、更に質量分
析装置の付いていないイオン打ち込み装置にて、水素を
加速電圧８０ｋＶで５×１０¹⁵１／cm² 打ち込んだ後、
コンタクト・ホールを開口し、アルミニウムなどで配線
７１１をし、オフセット型薄膜半導体装置が完成する。FIGS. 7A to 7D are sectional views showing the structural steps of the silicon thin film semiconductor device which constitutes the MIS field effect transistor of the offset type staggered structure according to the first embodiment. First, a substrate 701 similar to that of Reference Example 1
After cleaning the SiO ₂ film, a SiO ₂ film is used as a base protective film 702.
Accumulate about 000Å. Then, the first silicon film is applied to 30
A silicon film 703 to be a pad is formed by depositing 0 Å or more and patterning. In the second embodiment, as the first silicon film, the deposition temperature of 600 is obtained by using the LPCVD apparatus in which the channel portion silicon film is deposited in the first reference example.
℃ silane flow rate 12.5SCCM deposited on 1250Å,
Other than this, the same LPCVD apparatus is used and the deposition temperature is 55
Depositing a silicon film at about 0 ° C., using disilane (Si ₂ H ₆ ) as a source gas at a deposition temperature of about 450 ° C., or depositing a silicon film at about 250 ° C. by PECVD. Is also possible. Process maximum temperature 600 ℃
Any method may be used as long as the film forming temperature does not exceed the range. Next, a second silicon film 704 is deposited. The thickness of this second silicon film is about 300 Å or more, and the resistance value of the source / drain region after the impurity implantation is in the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 703 to be the pad is not required. In the present Example 1, the second silicon film 704 was deposited by the same method as the silicon thin film to be the channel portion in Reference Example 1. That is, LPCVD
Method using monosilane as a raw material gas and a deposition temperature of 550 ° C.,
Silane flow rate 100 SCCM Deposition rate 21.2 Å / min 2
It was deposited to a film thickness of 50Å. However, the second silicon film formation method is similar to the first silicon film, and the maximum process temperature 600
Any method is possible as long as the film forming temperature does not exceed ℃. For example, the second silicon film also has a deposition temperature of 60.
0 ℃, silane flow rate 12.5SCCM, reactor pressure 9.0mt
It may be deposited by orr, or it is possible to form a film at a lower temperature by using a higher order silane such as disilane or trisilane as a source gas. In this way, the second silicon film 704 is formed by some method (FIG. 7B), and after patterning, the gate insulating layer 70 is formed by the same method as in Reference Example 1.
5 was formed. That is, SiO ₂ is formed by the ECR-PECVD method.
The film was deposited at 1500Å. As a method for forming the gate insulating layer 705, when the second silicon film 704 is a polycrystalline silicon film, it can be formed by the APCVD method. Next, a metal film or the like to be the gate electrode is formed. In Example 1, a silicon film to which phosphorus was added at a high concentration was used as the gate electrode material. Here, the deposition temperature is 600 by the LPCVD method.
℃, monosilane 200SCCM, helium 99.5% and phosphine 0.5% helium-phosphine mixed gas 6SCCM and helium 100SCCM flow, furnace pressure 100
It was deposited with mtorr to a film thickness of 3000Å. The sheet resistance value immediately after film formation was 744 Ω / □. Subsequently, a resist is applied, and after patterning the resist, CF ₄
The phosphorus-added silicon film was patterned by the mixed plasma of oxygen and O ₂ . The ratio of CF ₄ and O ₂ is 200 SCCM each
Patterning was performed with an incident wave output of 700 W at 200 SCCM. At this time, the etching rate of the phosphorus-added silicon film is 1
Etching was performed for 5 minutes and 57 seconds at 5.4 Å / sec to form a gate electrode 706. Since the film thickness of the phosphorus-added silicon film was 3000 Å, the width of the gate electrode was narrowed by 2,500 Å in each of the left and right sides as compared with the resist 707 due to this plasma etching (FIG. 7C). Next, impurity ions are added while the resist 707 used for forming the gate electrode 706 is left without being peeled off. Example 1
Then, phosphorus was selected as an impurity to aim at an n-type thin film semiconductor device, but of course other elements are possible depending on the purpose. In the present Example 1, impurity ion addition was performed using an ion implanter without a mass spectrometer. A phosphine having a concentration of 5% diluted in hydrogen was used as a source gas, and it was implanted at a concentration of 3 × 10 ¹⁵ 1 / cm ² at an accelerating voltage of 110 kV. In this way, the first silicon film and a part of the second silicon film become the source / drain regions 708, and the resist 707 used for forming the gate electrode has a film thickness of about 2
Since the thickness is about μm, the second silicon film located thereunder is not ion-added, and reaches the channel portion 709 (FIG. 7C). Further, according to this method, an offset type thin film semiconductor device is produced. Next, after removing the resist 707 for forming the gate electrode, the substrate is subjected to heat treatment at 600 ° C. for 7 hours or more to activate the additive impurity ions and crystallize when the crystallinity of the channel portion silicon film 709 is insufficient. Promote the transformation. In Example 1, the same heat treatment as in Reference Example 1 was performed at 600 ° C. for 23 hours in a nitrogen atmosphere. Then, as an interlayer insulating film, SiO ₂ 71
0 was deposited to 5000 Å by the APCVD method or the like, and further hydrogen was implanted at 5 × 10 ¹⁵ 1 / cm ² at an accelerating voltage of 80 kV by an ion implanter without a mass spectrometer.
The contact hole is opened and the wiring 711 is made of aluminum or the like to complete the offset type thin film semiconductor device.

【００３７】こうして作成したオフセット型薄膜半導体
装置のトランジスタ特性を測定した所、Ｌ＝Ｗ＝１０μ
ｍ、Ｖｄｓ＝４Ｖでオン電流は３．４μＡ、ソース・ド
レイン電流の最小値はＶｇｓ＝−３．５Ｖの時０．０９
ｐＡ、又Ｖｇｓ＝−１０Ｖで定義したオフ電流は０．２
８ｐＡと、トランジスタ・オフ時のリーク電流を低く押
さえ、且つ良好なオン電流を得る事が出来た。When the transistor characteristics of the offset type thin film semiconductor device thus produced were measured, L = W = 10 μ
m, Vds = 4V, the on-current is 3.4 μA, and the minimum source / drain current is 0.09 when Vgs = −3.5V.
The off current defined by pA and Vgs = -10V is 0.2.
The leakage current when the transistor is off was kept low at 8 pA, and a good on-current could be obtained.

【００３８】実施例１で述べた様にオフセット型薄膜半
導体装置でソース領域・ドレイン領域が形成された後、
熱処理を加える事でオン電流は高く、リーク電流の小さ
い薄膜半導体装置を作成可能で有るが、本発明が実施例
１で詳述したオフセット型薄膜半導体装置の製造方法だ
けに限定される物では決して無い。例えば実施例１でオ
フセット型薄膜半導体装置を作成する方法としてゲート
電極幅よりも広い幅を持つレジストを打ち込みのマスク
としたが、他にも様々な方法が有る。例えば金属をゲー
ト電極として用い、この表面及び側面を酸化してゲート
電極を細めた後に不純物イオンを打ち込む事などでもオ
フセット型薄膜半導体装置を作成出来る。又、図５
（ｃ）に示したように逆スタガード構造に於いてもマス
ク材５０６の幅をゲート電極５０５よりも広げる事など
でオフセット型薄膜半導体装置となる。本発明はこれら
あらゆる製造方法で作成されたオフセット型薄膜半導体
装置に有効で有る。After the source and drain regions are formed in the offset type thin film semiconductor device as described in the first embodiment,
By applying heat treatment, a thin film semiconductor device having a high on-current and a small leak current can be produced, but the present invention is by no means limited to the method of manufacturing an offset type thin film semiconductor device described in detail in the first embodiment. There is no. For example, as the method of forming the offset type thin film semiconductor device in the first embodiment, a resist having a width wider than the gate electrode width is used as the implantation mask, but there are various other methods. For example, an offset type thin film semiconductor device can be produced by using a metal as a gate electrode, oxidizing the surface and side surfaces of the gate electrode to narrow the gate electrode, and then implanting impurity ions. Also, FIG.
As shown in (c), even in the inverted staggered structure, the offset thin film semiconductor device can be obtained by making the width of the mask material 506 wider than the gate electrode 505. The present invention is effective for offset type thin film semiconductor devices manufactured by any of these manufacturing methods.

【００３９】（参考例４） 図８（ａ）〜（ｆ）はＭＩＳ型電界効果トランジスタを
形成するシリコン薄膜半導体装置の製造工程を断面で示
した図で有る。Reference Example 4 FIGS. 8A to 8F are sectional views showing a manufacturing process of a silicon thin film semiconductor device for forming a MIS field effect transistor.

【００４０】本参考例４では絶縁性基板８０１として２
３５mm□の石英ガラスを用いたが、６００℃の温度に耐
え得る基板又は下地物質で有るならば、その種類や大き
さは無論問われない。例えばシリコン・ウェハー上に形
成された三次元ＬＳＩなども下地基板として可能で有
る。まず有機洗浄及び酸洗浄した石英ガラス基板８０１
上面に下地ＳｉＯ₂膜８０２を常圧化学気相堆積法（Ａ
ＰＣＶＤ法）で堆積した。下地ＳｉＯ₂ 膜８０２の形成
は基板温度３００℃、シラン流量１２０SCCM、酸素８４
０SCCM、窒素約１４０ＳＬＭで堆積した。この時の堆積
速度は３．９Å／ｓｅｃで、堆積時間は８分３３秒で有
った。次にドナー又はアクセプターとなる不純物を含ん
だシリコン薄膜８０３を減圧気相化学堆積法（ＬＰＣＶ
Ｄ法）にて堆積した（図８（ａ））。本参考例４では不
純物としてリンを選び、フォスフィン（ＰＨ₃）０．０
３SCCM、シラン（ＳｉＨ₄）２００SCCMを原料ガスとし
て堆積温度６００℃で１５００Å堆積した。この時の堆
積速度は３０Å／ｍｉｎで成膜直後のシート抵抗値は１
９５１Ω／□で有った。次に前記シリコン薄膜８０３上
にレジストを形成し、四弗化炭素（ＣＦ₄）、酸素
（Ｏ₂）、窒素（Ｎ₂）等の混合プラズマでパターニング
を行い、ソース・ドレイン領域８０４を形成した。続い
て該領域８０４表面上の汚物・自然酸化膜を取り除いた
後、直ちにアモルファス・シリコン薄膜８０５を減圧Ｃ
ＶＤ法で堆積した。（図８（ｂ））本参考例４に於ける
減圧ＣＶＤ装置は１８４．５ｌで反応室は石英ガラスに
依り作成されている。反応室の外側には３ゾーンに分か
れたヒーターが設置されており、それら３つのヒーター
を独立に調整する事で反応室内中央部付近に所望の温度
で等温領域を形成する。基板はこの等温領域内に水平に
設置して、アモルファス・シリコン薄膜８０５を堆積し
た。アモルファス・シリコン薄膜８０５は原料ガスとし
てジシラン（Ｓｉ₂Ｈ₆）１００SCCMを用い、希釈ガスと
してヘリウム（Ｈｅ）１００SCCMを使用した。堆積温度
は４５０℃であった。本参考例４のアモルファス・シリ
コン薄膜８０５を堆積する為に用いた減圧ＣＶＤ炉の排
気はメカニカル・ブースター・ポンプとロータリー・ポ
ンプを直結して行っている。メカニカル・ブースター・
ポンプと反応炉の間にはコンダクタンス・バルブが取り
付けて有り、このバルブの開閉量を調整する事で、反応
室内の圧力を所望の値に調整・維持可能となる。本参考
例４ではアモルファス・シリコン薄膜８０５を堆積中、
反応室内の圧力を３０６mtorr に保った。堆積速度は１
８．０７Å／ｍｉｎで、３０７Åの膜厚にアモルファス
・シリコン薄膜８０５を堆積した。次にこの様にして作
成されたアモルファス・シリコン薄膜８０５上にレジス
トを形成し、四弗化炭素、酸素、窒素等の混合プラズマ
でパターニングを行い、いずれチャンネル部となる位置
に丈アモルファス・シリコン薄膜８０６を残した。In this reference example 4, the insulating substrate 801 is 2
35 mm square quartz glass was used, but of course the type and size are not limited as long as it is a substrate or base material that can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer is also possible as the base substrate. First, a quartz glass substrate 801 that has been subjected to organic cleaning and acid cleaning
A base SiO ₂ film 802 is formed on the upper surface by atmospheric pressure chemical vapor deposition (A
PCVD method). The base SiO ₂ film 802 is formed by a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, and oxygen of 84.
It was deposited at 0 SCCM and about 140 SLM nitrogen. At this time, the deposition rate was 3.9 Å / sec, and the deposition time was 8 minutes 33 seconds. Next, a silicon thin film 803 containing impurities serving as a donor or an acceptor is formed by low pressure chemical vapor deposition (LPCV).
(D method) (FIG. 8A). In Reference Example 4, phosphorus is selected as an impurity, and phosphine (PH ₃ ) 0.0
3 SCCM and 200 SCCM of silane (SiH ₄ ) were used as source gases, and 1500 Å was deposited at a deposition temperature of 600 ° C. The deposition rate at this time was 30Å / min, and the sheet resistance immediately after film formation was 1
It was 951 Ω / □. Next, a resist is formed on the silicon thin film 803, and patterning is performed with a mixed plasma of carbon tetrafluoride (CF ₄ ), oxygen (O ₂ ), nitrogen (N ₂ ) and the like to form source / drain regions 804. . Then, after removing the dirt and natural oxide film on the surface of the region 804, the amorphous silicon thin film 805 is immediately depressurized C
It was deposited by the VD method. (FIG. 8 (b)) The low pressure CVD apparatus in Reference Example 4 is 184.5 l, and the reaction chamber is made of quartz glass. Heaters divided into three zones are installed outside the reaction chamber, and by adjusting these three heaters independently, an isothermal region is formed near the center of the reaction chamber at a desired temperature. The substrate was placed horizontally in this isothermal region and an amorphous silicon thin film 805 was deposited. For the amorphous silicon thin film 805, disilane (Si ₂ H ₆ ) 100 SCCM was used as a source gas, and helium (He) 100 SCCM was used as a diluent gas. The deposition temperature was 450 ° C. Evacuation of the low pressure CVD furnace used for depositing the amorphous silicon thin film 805 of Reference Example 4 is performed by directly connecting a mechanical booster pump and a rotary pump. Mechanical booster
A conductance valve is installed between the pump and the reaction furnace, and the pressure inside the reaction chamber can be adjusted and maintained at a desired value by adjusting the opening / closing amount of this valve. In Reference Example 4, while depositing the amorphous silicon thin film 805,
The pressure in the reaction chamber was kept at 306 mtorr. Deposition rate is 1
An amorphous silicon thin film 805 was deposited at a thickness of 307Å at 8.07Å / min. Next, a resist is formed on the thus-formed amorphous silicon thin film 805, and patterning is performed with a mixed plasma of carbon tetrafluoride, oxygen, nitrogen, etc., and a strong amorphous silicon thin film is eventually formed at a position which becomes a channel part. Leaving 806.

【００４１】次に、この基板を沸騰している濃度６０％
の硝酸にて洗浄し、更に１．６７％弗化水素酸水溶液に
２０秒間浸してソース・ドレイン領域８０４といずれチ
ャンネル部となる位置に残されたアモルファス・シリコ
ン薄膜８０６上の自然酸化膜を取り除いて清浄なシリコ
ン膜が出現した後、直ちに電子サイクロトロン共鳴プラ
ズマＣＶＤ装置（ＥＣＲ−ＰＥＣＶＤ装置）にて酸素プ
ラズマ８０７を照射した。（図８（ｃ））本参考例４で
用いたＥＣＲーＰＥＣＶＤ装置の概要を図２に示す。酸
素プラズマは２．４５ＧＨｚのマイクロ波を導波間２０
１を通じて反応室２０２に導き、１００SCCMの酸素をガ
ス導入管２０３から導入して酸素プラズマを立てた。こ
の時反応室内の圧力は１．８４mtorr で、マイクロ波の
出力は２５００Ｗで有った。反応室の外側には外部コイ
ル２０４が設けられて居り、酸素プラズマに８７５Ｇａ
ｕｓｓの磁場を掛けてプラズマ中の電子にＥＣＲ条件を
満足せしめている。基板２０５はプラズマに対して垂直
に置かれ、ヒーター２０６に依り基板温度が３００℃と
なる様保たれている。この条件で酸素プラズマ８０７を
８分２０秒間照射して、いずれチャンネル部となる位置
に残されたアモルファス・シリコン薄膜８０６の酸化を
行い、ゲート絶縁層の一部位となるＳｉＯ₂膜８０８を
得た。この時、ゲート絶縁層の一部位となるＳｉＯ₂ 膜
８０８の下部には、いずれチャンネル部となるアモルフ
ァスシリコン薄膜８０９が残留している。（図８
（ｄ））更に真空を破る事なく連続してゲート絶縁層と
なるＳｉＯ₂膜８１０を堆積した。このＳｉＯ₂膜８１０
はマイクロ波出力が２２５０Ｗ、シラン流量６０SCCM、
酸素流量１００SCCM、基板温度３００℃で、１８．７５
秒間堆積した。堆積中に於ける反応室内圧力は２．６２
mtorrで有った。こうして形成した多層膜を多波長分散
型偏光解析法（多波長分光エリプソメトリー：ソープラ
社ＭＯＳＳ−ＥＳ４Ｇ）を用いて、いずれチャンネル部
となる残留しているアモルファス・シリコン膜８０９の
膜厚と、アモルファス・シリコン膜を酸化して形成した
ＳｉＯ₂膜８０８の膜厚、及びＥＣＲ−ＰＥＣＶＤ法で
堆積したＳｉＯ₂膜８１０の膜厚を測定した所、アモル
ファス・シリコン薄膜８０９が２０５Å、ＳｉＯ₂膜８
０８が１２０Å、ＳｉＯ₂膜８１０が１５００Åで有っ
た。又この時、波長が６３２．８ｎｍに於けるＳｉＯ₂
膜の屈折率は、ＳｉＯ₂膜８０８が１．４２、ＳｉＯ₂膜
８１０が１．４０で有った。Next, this substrate is boiled at a concentration of 60%.
The substrate is washed with nitric acid as described above and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the native oxide film on the source / drain region 804 and the amorphous silicon thin film 806 left at a position where a channel portion will be formed. Immediately after the appearance of a clean silicon film, oxygen plasma 807 was irradiated by an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). (FIG. 8 (c)) An outline of the ECR-PECVD apparatus used in Reference Example 4 is shown in FIG. Oxygen plasma uses microwave of 2.45 GHz between waveguides 20
1 was introduced into the reaction chamber 202, and 100 SCCM of oxygen was introduced from the gas introduction pipe 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.84 mtorr, and the microwave output was 2500 W. An external coil 204 is provided outside the reaction chamber, and the oxygen plasma is 875 Ga.
By applying a magnetic field of uss, the electrons in the plasma satisfy the ECR condition. The substrate 205 is placed perpendicular to the plasma, and the substrate temperature is kept at 300 ° C. by the heater 206. Oxygen plasma 807 was irradiated under this condition for 8 minutes and 20 seconds to oxidize the amorphous silicon thin film 806 left at a position which eventually becomes a channel part, and a SiO ₂ film 808 which becomes a part of the gate insulating layer was obtained. . At this time, the amorphous silicon thin film 809, which will eventually become the channel part, remains below the SiO ₂ film 808, which will become part of the gate insulating layer. (Fig. 8
(D)) Further, a SiO ₂ film 810 to be a gate insulating layer was continuously deposited without breaking the vacuum. This SiO ₂ film 810
Has a microwave output of 2250 W, a silane flow rate of 60 SCCM,
Oxygen flow rate 100 SCCM, substrate temperature 300 ° C, 18.75
Deposited for seconds. Pressure in the reaction chamber during deposition was 2.62
It was mtorr. The multi-layer film thus formed is subjected to a multi-wavelength dispersion ellipsometry (multi-wavelength spectroscopic ellipsometry: MOSPES MOSS-ES4G) to determine the film thickness of the remaining amorphous silicon film 809, which will eventually become the channel part, and the amorphous film. When the film thickness of the SiO ₂ film 808 formed by oxidizing the silicon film and the film thickness of the SiO ₂ film 810 deposited by the ECR-PECVD method were measured, the amorphous silicon thin film 809 was 205 Å, and the SiO ₂ film 8
08 was 120Å and the SiO ₂ film 810 was 1500Å. Also, at this time, SiO ₂ at a wavelength of 632.8 nm
The SiO ₂ film 808 had a refractive index of 1.42, and the SiO ₂ film 810 had a refractive index of 1.40.

【００４２】次にこうして得られた基板を６００℃に保
持された電熱炉に挿入し、４８時間の熱処理を施した。
この時電熱炉には純度９９．９９９％以上の窒素ガスを
２０ｌ／ｍｉｎ流し続け、不活性雰囲気を保持し続け
た。この不活性雰囲気６００℃の熱処理に依り、チャン
ネル部に残留していたアモルファス・シリコン薄膜は結
晶化し、チャンネル部を構成するシリコン薄膜８１１へ
と改変される。（図８（ｅ））続いてこの基板を再びＥ
ＣＲ−ＰＥＣＶＤ装置に入れ、該装置を用いて熱処理が
施された基板に水素プラズマを照射した。この時、基板
温度は３００℃、マイクロ波出力２０００Ｗで水素を１
００SCCM流して水素プラズマを立てた。この状態で反応
室内の圧力は１．９７mtorr で有った。水素プラズマ照
射は４５分間行った。Next, the substrate thus obtained was inserted into an electric heating furnace maintained at 600 ° C. and heat-treated for 48 hours.
At this time, nitrogen gas having a purity of 99.999% or more was continuously flowed in the electric heating furnace at 20 l / min to keep an inert atmosphere. By the heat treatment at 600 ° C. in the inert atmosphere, the amorphous silicon thin film remaining in the channel portion is crystallized and converted into the silicon thin film 811 forming the channel portion. (FIG. 8 (e)) Then, this substrate is again E
The substrate was placed in a CR-PECVD apparatus, and the substrate heat-treated using the apparatus was irradiated with hydrogen plasma. At this time, the substrate temperature is 300 ° C., the microwave output is 2000 W, and hydrogen is 1
Hydrogen plasma was established by flowing 00 SCCM. In this state, the pressure inside the reaction chamber was 1.97 mtorr. Hydrogen plasma irradiation was performed for 45 minutes.

【００４３】次にクロムをスパッター法で１５００Å堆
積し、パターニングに依りゲート電極８１２を形成し
た。この時シート抵抗値は１．３６Ω／□で有った。そ
の後、ゲート絶縁膜にコンタクトホールを開け、ソース
・ドレイン取り出し電極８１３をスパッター法などで形
成し、パターニングを行う事でトランジスタは完成す
る。（図８（ｆ））本参考例４ではソース・ドレイン取
り出し電極材料として、膜厚８０００Åのアルミニウム
を用いた。この時のアルミニウムのシート抵抗値は４２
ｍΩ／□で有った。Next, chromium was deposited by 1500 Å by a sputtering method, and a gate electrode 812 was formed by patterning. At this time, the sheet resistance value was 1.36 Ω / □. After that, a contact hole is formed in the gate insulating film, a source / drain extraction electrode 813 is formed by a sputtering method or the like, and patterning is performed, whereby the transistor is completed. (FIG. 8 (f)) In this reference example 4, aluminum having a film thickness of 8000Å was used as the source / drain extraction electrode material. The sheet resistance of aluminum at this time is 42
It was mΩ / □.

【００４４】この様にして試作した薄膜トランジスタ
（ＴＦＴ）の特性の一例Ｖｇｓ−Ｉｄｓ曲線を図９の９
−ａに示した。ここでＩｄｓはソース・ドレイン電圧、
Ｖｄｓ＝４Ｖ、温度２５℃で測定した。トランジスタ・
サイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１０
０μｍで有った。Ｖｄｓ＝４Ｖ，Ｖｇｓ＝１０Ｖでトラ
ンジスタをオンさせた時のオン電流はＩｄｓ＝３４．５
μＡと良好なトランジスタ特性を有する薄膜半導体装置
が得られた。又、このトランジスタの飽和電流領域より
求めた電界効果移動度は１２．５２cm² ／ｖ・ｓｅｃで
有った。図９の９−ｂには比較の為に従来技術に依って
作成した薄膜半導体装置のトランジスタ特性を図示し
た。即ち、従来技術では、チャンネル部シリコン薄膜を
減圧ＣＶＤ法にて６００℃で堆積し、酸素プラズマ照射
を施さぬ他は総て本参考例４と同一の工程で薄膜半導体
装置を作成したもので有る。この時、減圧ＣＶＤ法でチ
ャンネル部シリコン薄膜を堆積する装置は本参考例４で
アモルファス・シリコン薄膜を堆積した装置と同一で有
り、原料ガスのモノシランは２４SCCM流し、反応炉内圧
力は１３．８mtorr、堆積速度は１９．００Å／ｍｉｎ
で２５２Åの膜厚に堆積した。この従来のＴＦＴのオン
電流はＩｄｓ＝４．６μＡで電界効果移動度は４．４０
cm／ｖ・ｓｅｃで有った。この他に、チャンネル部シリ
コン薄膜を同様に減圧ＣＶＤ法で６００℃にて堆積した
後、ゲート絶縁膜堆積前に酸素プラズマ照射を施し、そ
れ以外の工程は総て本参考例４と同一の工程で薄膜半導
体装置を作成し、ＴＦＴ特性を測定した所、ＴＦＴ特性
は酸素プラズマ照射の有無でほとんど変化せず、酸素プ
ラズマ照射を施したＴＦＴのＶｇｓ−Ｉｄｓ曲線は図９
の９−ｂと一致した。この時ＴＦＴのオン電流はＩｄｓ
＝４．７μＡで、電界効果移動度は４．４４cm² ／ｖ・
ｓｅｃで有った。即ち、チャンネル部シリコン薄膜を６
００℃にて減圧ＣＶＤ法で堆積する従来技術では、酸素
プラズマ照射の効果は非常に小さい。図９の９−ｃには
別の従来技術に依り作成された薄膜半導体装置のＴＦＴ
特性を図示した。この従来技術では、本参考例４で酸素
プラズマ照射を施さぬ他は総て本実施例２と同一の工程
で薄膜半導体装置を作成した物で有る。即ち、チャンネ
ル部シリコン層として、まずアモルファス・シリコン薄
膜を堆積し、その後６００℃の熱処理をおこなうもの
の、ゲート絶縁層形成前に酸素プラズマ照射を施さなか
った工程で有る。この従来技術に依り、作成されたＴＦ
Ｔは−１０Ｖのデプレッションを呈しており、立ち上が
り特性も良くない。この薄膜半導体装置のオン電流はＶ
ｄｓ＝４Ｖ、Ｖｇｓ＝１０Ｖで１２．１μＡで有り、電
界効果移動度は９．９４cm²／ｖ・ｓｅｃで有った。An example of the characteristics of the thin film transistor (TFT) prototyped in this manner is shown by the Vgs-Ids curve in FIG.
-A. Where Ids is the source-drain voltage,
It was measured at Vds = 4V and a temperature of 25 ° C. Transistor
The size of the channel part is L = 10 μm, width W = 10
It was 0 μm. The on-current when the transistor is turned on at Vds = 4V and Vgs = 10V is Ids = 34.5.
A thin film semiconductor device having good transistor characteristics of μA was obtained. Further, the field effect mobility obtained from the saturation current region of this transistor was 12.52 cm ² / v · sec. For comparison, 9-b of FIG. 9 shows the transistor characteristics of the thin film semiconductor device manufactured by the conventional technique. That is, in the prior art, a thin film semiconductor device was produced by the same steps as those in Reference Example 4 except that the channel silicon thin film was deposited at 600 ° C. by the low pressure CVD method and the oxygen plasma irradiation was not performed. . At this time, the apparatus for depositing the channel silicon thin film by the low pressure CVD method is the same as the apparatus for depositing the amorphous silicon thin film in Reference Example 4, the raw material gas monosilane is made to flow 24 SCCM, and the pressure in the reaction furnace is 13.8 mtorr. , Deposition rate is 19.00 Å / min
Deposited to a film thickness of 252Å. The on-current of this conventional TFT is Ids = 4.6 μA and the field-effect mobility is 4.40.
It was cm / v · sec. In addition to this, a silicon thin film in the channel portion is similarly deposited at 600 ° C. by the low pressure CVD method, and then oxygen plasma irradiation is performed before the gate insulating film is deposited. All other steps are the same as those in Reference Example 4. A thin film semiconductor device was prepared by using the above, and the TFT characteristics were measured. The TFT characteristics hardly changed with or without oxygen plasma irradiation, and the Vgs-Ids curve of the TFT subjected to oxygen plasma irradiation is shown in FIG.
9-b. At this time, the ON current of the TFT is Ids
= 4.7 μA, field effect mobility is 4.44 cm ² / v
It was sec. That is, the channel silicon thin film is
The effect of oxygen plasma irradiation is very small in the conventional technique of depositing by low pressure CVD at 00 ° C. 9-c in FIG. 9 shows a TFT of a thin film semiconductor device manufactured by another conventional technique.
The characteristics are illustrated. In this conventional technique, a thin film semiconductor device is manufactured by the same steps as those in the second embodiment except that the oxygen plasma irradiation is not performed in the fourth reference example. That is, this is a step in which an amorphous silicon thin film is first deposited as a channel portion silicon layer and then heat treatment at 600 ° C. is performed, but oxygen plasma irradiation is not performed before the gate insulating layer is formed. TF created by this conventional technique
T exhibits a depletion of -10V and the rising characteristic is not good. The on-current of this thin film semiconductor device is V
It was 12.1 μA at ds = 4 V and Vgs = 10 V, and the field-effect mobility was 9.94 cm ² / v · sec.

【００４５】こうした結果から本参考例４が示した通
り、いずれチャンネル部となるアモルファス・シリコン
薄膜に酸素プラズマを照射し、その後熱処理を施してチ
ャンネル部シリコン薄膜の結晶化を進めた時のみ、薄膜
半導体装置のトランジスタ特性が大幅に向上する事が分
かる。これはまずアモルファス・シリコン薄膜の表面が
酸素プラズマで酸化される為、清浄なＭＩＳ界面が形成
され、その後、結晶化が進められた為で有る。これによ
り従来技術で作成した薄膜半導体装置に比べ、本発明の
実施例２が著しく良好な半導体特性を有する理由が分か
る。From these results, as shown in Reference Example 4, only when the amorphous silicon thin film to become the channel part is irradiated with oxygen plasma and then heat treatment is performed to crystallize the channel part silicon thin film, the thin film is formed. It can be seen that the transistor characteristics of the semiconductor device are significantly improved. This is because the surface of the amorphous silicon thin film was first oxidized by oxygen plasma, so that a clean MIS interface was formed and then crystallization proceeded. From this, it can be understood that the second embodiment of the present invention has remarkably good semiconductor characteristics as compared with the thin film semiconductor device manufactured by the conventional technique.

【００４６】（実施例２） 絶縁性物質上にシリコン膜及び酸化硅素膜を形成した
後、ドナー又はアクセプターとなる不純物をシリコン膜
に添加して、シリコン膜に依る導電層を作成した。Example 2 After forming a silicon film and a silicon oxide film on an insulating material, impurities serving as donors or acceptors were added to the silicon film to form a conductive layer based on the silicon film.

【００４７】本実施例２では基板として直径７５mmの溶
融石英基板を用いた。しかし、無論６００℃程度の熱処
理に耐え得る基板であるならば何で有っても構わない。
例えば加工されたシリコン基板なども可能で有る。まず
有機洗浄及び酸洗浄した基板上面に下地ＳｉＯ₂膜をＡ
ＰＣＶＤ法で堆積した。下地ＳｉＯ₂膜の形成は基板温
度３００℃、シラン流量１２０SCCM、酸素８４０SCCM、
窒素約１４０SLMで堆積した。この時の堆積速度は３．
９Å／ｓｅｃで堆積時間は１２分４９秒で有った。次に
参考例１にてチャンネル部シリコン膜を堆積するのに用
いたＬＰＣＶＤ装置を用いて参考例１と同様な方法でシ
リコン膜を堆積した。即ち堆積温度５５０℃、シラン流
量１００SCCM、反応室内圧力を４００ｍｔｏｒｒにて１
１分２０秒間シリコン膜を堆積した。こうして得られた
シリコン膜の膜厚は２５２Åで有った。In Example 2, a fused silica substrate having a diameter of 75 mm was used as the substrate. However, of course, any substrate may be used as long as it can withstand a heat treatment at about 600 ° C.
For example, a processed silicon substrate is also possible. First, a base SiO ₂ film is formed on the upper surface of the substrate which has been organically and acid-cleaned.
It was deposited by the PCVD method. The formation of the underlying SiO ₂ film is performed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM,
It was deposited with about 140 SLM of nitrogen. The deposition rate at this time is 3.
At 9Å / sec, the deposition time was 12 minutes 49 seconds. Next, a silicon film was deposited in the same manner as in Reference Example 1 by using the LPCVD apparatus used to deposit the channel portion silicon film in Reference Example 1. That is, the deposition temperature is 550 ° C., the silane flow rate is 100 SCCM, and the reaction chamber pressure is 400 mtorr.
A silicon film was deposited for 1 minute and 20 seconds. The film thickness of the silicon film thus obtained was 252Å.

【００４８】次にこうして得られた基板に熱処理を施し
て、シリコン膜の結晶性を高めた。この熱処理方法は参
考例１でシリコン膜１０４の結晶性を高める為に施した
熱処理と同一で有る。即ち、窒素雰囲気下６００℃で２
３時間の熱処理を行った。熱処理終了後、このシリコン
膜はレジストでパターニングされ、さらにＣＦ₄とＯ₂の
混合プラズマに依りエッチングされ、シリコン膜の配線
パターンが作成された。Next, the substrate thus obtained was subjected to a heat treatment to enhance the crystallinity of the silicon film. This heat treatment method is the same as the heat treatment performed to increase the crystallinity of the silicon film 104 in Reference Example 1. That is, under nitrogen atmosphere at 600 ° C for 2
Heat treatment was performed for 3 hours. After the heat treatment was completed, the silicon film was patterned with a resist and further etched by a mixed plasma of CF ₄ and O ₂ to form a wiring pattern of the silicon film.

【００４９】続いてこの基板を濃度６０％の沸騰硝酸に
て洗浄し、更に１．６７％弗化水素酸水溶液に２０秒間
浸して、シリコン膜上の自然酸化膜を取り除き、清浄シ
リコン表面を出現させた後、直ちにＥＣＲーＰＥＣＶＤ
装置にて酸化硅素膜を１５００Åの厚さに堆積した。こ
こで酸化硅素膜の堆積は参考例１にてゲート絶縁膜を形
成する方法と全く同一の方法で行った。次にイオン打ち
込み装置を用いてドナー又はアクセプターとなる不純物
をシリコン膜で作成した配線に添加した。本実施例２で
は不純物として燐を選びｎ型導電層の作成を目指した
が、無論他元素もその目的に応じて可能で有る。本実施
例２ではバケットタイプの質量非分離型のイオン注入装
置を用いて不純物イオンの添加を施した。原料ガスとし
て水素中に希釈された濃度５％のホスフィンを用い、加
速電圧１１０ＫＶで３×１０¹⁵１／cm² の濃度に酸化硅
素膜を通じて打ち込んだ。次にこの基板を窒素雰囲気下
で３００℃に保たれている炉に挿入して熱処理を施し
た。熱処理時間は丁度一時間で有った。３００℃、一時
間の熱処理終了後、酸化硅素膜にコンタクトホールを開
穴し、アルミニウムで取り出し電極を作成した。こうし
て作成された不純物添加シリコン膜配線の抵抗を測定し
た所、シート抵抗値として、９５％の信頼係数で（７１
±１５）ｋΩ／□が測定された。一般に数百Åの膜厚し
か持たぬ薄膜に不純物イオンを添加して、３００℃程度
の低温で添加イオンを活性化して導電層を得る事は不可
能と信じられていた。しかるに、本発明では熱処理を施
されたシリコン膜の膜質を、シリコン膜上をＥＣＲ−Ｐ
ＥＣＶＤ法で堆積した酸化硅素膜で被覆する事に依り、
シリコン膜表面の捕獲密度を低減させる等のシリコン膜
質改善に成功した為、電子散乱密度を低下させ、薄膜導
電層の作成が初めて可能となった。この事を従来技術に
依るシリコン膜と比較し、本発明の優位性を明らかにす
る。Subsequently, this substrate was washed with boiling nitric acid having a concentration of 60%, and further dipped in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film on the silicon film to reveal a clean silicon surface. And then ECR-PECVD immediately
A silicon oxide film was deposited with a device to a thickness of 1500 Å. Here, the deposition of the silicon oxide film was performed by the same method as the method of forming the gate insulating film in Reference Example 1. Next, using an ion implanter, impurities serving as a donor or an acceptor were added to the wiring formed of the silicon film. In the second embodiment, phosphorus was selected as an impurity to form the n-type conductive layer, but other elements can of course be used according to the purpose. In the second embodiment, impurity ions are added by using a bucket type non-separation type ion implanter. A phosphine having a concentration of 5% diluted in hydrogen was used as a source gas, and it was implanted at a accelerating voltage of 110 KV to a concentration of 3 × 10 ¹⁵ 1 / cm ² through a silicon oxide film. Next, this substrate was placed in a furnace kept at 300 ° C. in a nitrogen atmosphere and subjected to heat treatment. The heat treatment time was just one hour. After completion of heat treatment at 300 ° C. for one hour, contact holes were opened in the silicon oxide film, and an extraction electrode was formed from aluminum. When the resistance of the impurity-added silicon film wiring thus formed was measured, the sheet resistance value was 95% with a reliability coefficient of (71
± 15) kΩ / □ was measured. It was generally believed that it is impossible to add impurity ions to a thin film having a thickness of several hundred Å and activate the added ions at a low temperature of about 300 ° C. to obtain a conductive layer. However, in the present invention, the quality of the heat-treated silicon film is set to ECR-P on the silicon film.
By covering with a silicon oxide film deposited by the ECVD method,
Since we succeeded in improving the quality of the silicon film, such as reducing the capture density on the surface of the silicon film, the electron scattering density was lowered and it became possible for the first time to form a thin film conductive layer. By comparing this with the silicon film according to the conventional technique, the superiority of the present invention is clarified.

【００５０】まず第一にシリコン膜をＬＰＣＶＤ法にて
６００℃で堆積した後、ＥＣＲーＰＥＣＶＤ法で酸化硅
素膜を形成した従来技術のシリコン膜に不純物を添加
し、３００℃の低温活性化でシリコン膜導電層の作成を
試みた。ここではシリコン膜を６００℃で、モノシラン
を１２．５０SCCM流し、反応室内圧力を９．２ｍｔｏｒ
ｒで２６３Åの膜厚に堆積した他は、本実施例２の本発
明と全く同一の工程で不純物添加シリコン膜配線を作成
した。こうして得られた従来技術のシリコン膜のシート
抵抗は基板内５ヶ所を測定して総て１ＧΩ／□以上で事
実上電流は全く流れなかった。First, after depositing a silicon film at 600 ° C. by the LPCVD method, impurities are added to the silicon film of the prior art on which a silicon oxide film is formed by the ECR-PECVD method, and activation is performed at a low temperature of 300 ° C. An attempt was made to create a silicon film conductive layer. Here, the silicon film is made to flow at 600 ° C., the monosilane is made to flow at 12.50 SCCM, and the reaction chamber pressure is set to 9.2 mtor.
Impurity-added silicon film wiring was formed by the same process as in the present invention of Example 2 except that the film was deposited to a film thickness of 263Å by r. The sheet resistance of the silicon film of the prior art thus obtained was 1 GΩ / □ or more when measured at 5 points in the substrate, and virtually no current flowed.

【００５１】第二にシリコン膜は本実施例２の本発明と
全く同様に６００℃の熱処理を施して作成し、その後Ａ
ＰＣＶＤ法で酸化硅素膜を形成した従来技術のシリコン
膜に不純物を添加し、３００℃の低温活性化でシリコン
膜導電層の作成を試みた。ここで酸化硅素膜はＡＰＣＶ
Ｄ法で基板温度を３００℃に保ち、窒素中に２０％シラ
ンを含んだ窒素・シラン混合ガスを３００SCCM、酸素を
４２０SCCM流し、約１４０SLMの希釈用窒素をこれらの
原料ガスと共に流して、１５００Åの膜厚に堆積した。
これ以外は総て、本実施例２の本発明と全く同一の工程
で不純物添加シリコン膜配線を作成した。こうして得ら
れた従来技術のシリコン膜のシート抵抗値は９５％の信
頼係数で（１７５±５６）ｋΩ／□で有った。その後こ
の基板を再度ＥＣＲ−ＰＥＣＶＤ装置に装着し、水素プ
ラズマ処理を施した。水素プラズマ処理は基板温度３０
０℃で水素を１２５SCCM流し、マイクロ波出力２０００
Ｗで３０分間行った。水素プラズマ処理後、基板内５ヶ
所の抵抗値を測定した所、２ヶ所のシート抵抗は１ＧΩ
／□で以上で有り、残りの３ヶ所の平均値は１５８ｋΩ
／□で標準偏差値は６８ｋΩ／□で有った。Secondly, the silicon film is formed by heat treatment at 600 ° C. in the same manner as in the present invention of the second embodiment, and then A is formed.
An impurity was added to a conventional silicon film having a silicon oxide film formed by the PCVD method, and an attempt was made to form a silicon film conductive layer by activating the silicon film at a low temperature of 300 ° C. Here, the silicon oxide film is APCV
The substrate temperature was kept at 300 ° C by the D method, 300 SCCM of nitrogen / silane mixed gas containing 20% silane in nitrogen and 420 SCCM of oxygen were flowed, and about 140 SLM of diluting nitrogen was flowed together with these source gases to obtain 1500 Å. Deposited to a film thickness.
Except for this, the impurity-added silicon film wiring was formed by the same steps as those of the present invention of the second embodiment. The sheet resistance value of the conventional silicon film thus obtained was (175 ± 56) kΩ / □ with a 95% reliability coefficient. Then, this substrate was mounted on the ECR-PECVD apparatus again and subjected to hydrogen plasma treatment. Substrate temperature 30 for hydrogen plasma treatment
Flowing hydrogen 125SCCM at 0 ℃, microwave output 2000
W for 30 minutes. After the hydrogen plasma treatment, the resistance value at 5 points in the substrate was measured and the sheet resistance at 2 points was 1 GΩ.
It is above with / □, and the average value of the remaining 3 places is 158 kΩ
The standard deviation value was 68 kΩ / □.

【００５２】この様に６００℃以下で熱処理されたシリ
コン膜上をＥＣＲーＰＥＣＶＤ装置で形成された酸化硅
素膜で被覆する事に依り、高膜質なシリコン膜が得られ
る事が分かる。この為、参考例１で示した様に本発明の
シリコン膜を薄膜半導体装置のチャンネル部に用い、Ｅ
ＣＲーＰＥＣＶＤ装置で形成された酸化硅素膜をゲート
絶縁層に用いると特性の良い薄膜半導体装置が得られ、
又本実施例２で示した様に本発明のシリコン膜に不純物
イオンを添加すると、低温で低抵抗のシリコン膜導電層
を得る事が可能となる。従って本発明のシリコン膜は単
に薄膜半導体装置に有効のみならず、電荷結合装置（Ｃ
ＣＤ）のゲート電極や配線など、あらゆる電子装置に使
用される非単結晶シリコン膜に取って極めて有効に利用
し得る。It is understood that a high-quality silicon film can be obtained by coating the silicon film thus heat-treated at 600 ° C. or lower with the silicon oxide film formed by the ECR-PECVD apparatus. Therefore, as shown in Reference Example 1, the silicon film of the present invention is used for the channel portion of the thin film semiconductor device, and E
When a silicon oxide film formed by a CR-PECVD device is used as a gate insulating layer, a thin film semiconductor device having excellent characteristics can be obtained.
Further, as shown in the second embodiment, by adding impurity ions to the silicon film of the present invention, it becomes possible to obtain a silicon film conductive layer having a low resistance at a low temperature. Therefore, the silicon film of the present invention is not only effective for a thin film semiconductor device but also for a charge coupled device (C
It can be used very effectively as a non-single-crystal silicon film used in various electronic devices such as a gate electrode of CD) and wiring.

【００５３】（参考例５） 実施例２の本発明でバケット型質量非分離型のイオン注
入装置を用いて不純物イオンをシリコン膜に添加した工
程を、質量分離型イオン注入装置に変えて質量数３１の
燐の一価イオンを打ち込む事に変更した他は、総て実施
例２の本発明と全く同一工程で、不純物添加シリコン膜
導電層の作成を試みた。本参考例５では燐イオンを９０
KVで３×１０¹⁵１／cm² 打ち込んだ。こうして得られた
不純物添加シリコン膜の抵抗を測定した所、基板内５ヶ
所で総て１ＧΩ／□で実質的には全く電流は流れなかっ
た。これは実施例２の本発明では、不純物の添加を質量
非分離型のイオン注入装置を用い、原料ガスとして水素
・ホスフィン混合ガスを使用した為、シリコン膜に燐元
素添加時には必然的に水素イオンの添加が同時に行わ
れ、イオン添加の際生じた欠陥が水素イオンで修復され
る為、本発明の良質なシリコン膜に限って、低温で低抵
抗シリコン導電層が作成されたので有る。Reference Example 5 The mass number is changed by changing the step of adding impurity ions to the silicon film using the bucket type mass non-separation type ion implantation apparatus of the present invention in Example 2 to the mass separation type ion implantation apparatus. An attempt was made to form an impurity-doped silicon film conductive layer in exactly the same steps as in the present invention of Example 2 except that implantation of 31 monovalent ions of phosphorus was performed. In Reference Example 5, phosphorus ion is 90
I hit 3 × 10 ¹⁵ 1 / cm ^{2 with} KV. When the resistance of the thus-obtained impurity-added silicon film was measured, it was found that all 5 G locations in the substrate were 1 GΩ / □ and substantially no current flowed. This is because in the present invention of the second embodiment, impurities are added by using a mass non-separation type ion implanter and a hydrogen / phosphine mixed gas is used as a source gas, so that hydrogen ions are inevitably added when a phosphorus element is added to a silicon film. Is added simultaneously, and the defects generated during the ion addition are repaired by hydrogen ions. Therefore, the low resistance silicon conductive layer was formed at a low temperature only in the good quality silicon film of the present invention.

【００５４】（実施例３） 図１０（ａ）〜（ｄ）は本実施例３に於けるセルフ・ア
ライン型スタガード構造のＭＩＳ型電界効果トランジス
タを構成するシリコン薄膜半導体装置の製造工程を断面
で示した図で有る。まず参考例１と同様基板１００１を
洗浄した後、下地保護膜１００２としてＳｉＯ₂ 膜を２
０００Å程度堆積する。続いて第一のシリコン膜を１５
００Å程度堆積し、パターニングを行う事でパッドとな
るシリコン膜１００３を形成する（図１０（ａ））。こ
の第一のシリコン膜として本実施例３では参考例１でチ
ャンネル部シリコン膜を堆積したＬＰＣＶＤ装置を用い
て堆積温度６００℃シラン流量１２．５SCCMで１５００
Åに堆積したが、これ以外にも同じＬＰＣＶＤ装置を用
いて堆積温度５５０℃程度でシリコン膜を堆積する事
も、原料ガスとしてジシラン（Ｓｉ₂Ｈ₆）を用いて堆積
温度４５０℃程度で堆積する事も、ＰＥＣＶＤ法にて２
５０℃程度でシリコン膜を堆積する事も可能で有る。工
程最高温度６００℃を越えぬ膜形成温度で有るならば、
如何なる方法であっても構わない。次に第二のシリコン
膜１００４を堆積するが、この第二のシリコン膜の膜厚
が３００Å程度以上有り、不純物注入後のソース・ドレ
イン領域の抵抗値がトランジスタを動作させた時のチャ
ンネル領域の抵抗値に比べて充分低ければ、第一のシリ
コン膜又はパッドとなるシリコン膜１００３は必要とさ
れない。本実施例３では第二のシリコン膜１００４を参
考例１でチャンネル部となるシリコン薄膜と同じ方法で
堆積した。即ちＬＰＣＶＤ法にてモノシランを原料ガス
とし、堆積温度５５０℃、シラン流量１００SCCM堆積速
度２１．２Å／ｍｉｎで２５０Åの膜厚に堆積した。そ
の後参考例１でシリコン膜の結晶性を高める為に行った
のと全く同一の熱処理を施した。即ち窒素雰囲気下６０
０℃で２３時間の熱処理を行った。（図１０（ｂ））。
次に第二のシリコン膜のパターニングを行った後、参考
例１と同様の方法でゲート絶縁層１００５を形成した。
即ち、ＥＣＲ−ＰＥＣＶＤ法でＳｉＯ₂ 膜を１５００Å
堆積した。次にゲート電極となる金属膜などを形成す
る。本実施例３ではゲート電極材料として、２０００Å
の膜厚を有するクロム膜を用いた。クロム膜は基板温度
１８０℃でスパッター法に依り形成された。成膜直後の
クロムのシート抵抗値は９９４ｍΩ／□で有った。引き
続いてＡＰＣＶＤ法でクロム上に３００℃の基板温度で
ＳｉＯ₂ 膜を３０００Å堆積した。その後レジストでパ
ターニングを行い、ゲート電極１００６とＳｉＯ₂ 膜に
依る保護キャップ層１００７を形成し、不純物イオンを
添加した。本実施例３では不純物として燐を選びｎ型薄
膜半導体装置の作成を目指したが、無論他元素もその目
的に応じて可能で有る。本実施例３では質量分析装置が
付いていないイオン打ち込み装置を用いて不純物イオン
添加を施した。原料ガスとして水素中に希釈された濃度
５％のホスフィンを用い、加速電圧１１０ｋＶで５×１
０¹⁵１／cm² の濃度に打ち込んだ。この様にして、第一
のシリコン膜と第二のシリコン膜の一部はソース・ドレ
イン領域１００８となり、又ＳｉＯ₂ 膜に依る保護キャ
ップ層１００７が有るため、この下に位置する第二のシ
リコン膜はイオン添加されず、チャンネル部１００９を
構成するに至る（図１０（ｃ））。次に該基板を窒素雰
囲気下３５０℃で２時間の熱処理を施し、添加不純物イ
オンの活性化を行った。その後層間絶縁膜としてＳｉＯ
₂ 膜１０１０を５０００Å堆積し、続いてコンタクト・
ホールを開穴し、アルミニウムなどで配線１０１１を
し、セルフ・アライン型薄膜半導体装置が完成する（図
１０（ｄ））。(Embodiment 3) FIGS. 10A to 10D are sectional views showing a process of manufacturing a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-aligned staggered structure according to the third embodiment. It is the figure shown. First, after cleaning the substrate 1001 in the same manner as in Reference Example 1, a SiO ₂ film was used as the base protective film 1002.
Accumulate about 000Å. Then, the first silicon film 15
A silicon film 1003 to be a pad is formed by depositing about 00Å and patterning (FIG. 10A). In Example 3, as the first silicon film, the LPCVD apparatus in which the channel portion silicon film was deposited in Reference Example 1 was used to deposit 1500 at a deposition temperature of 600 ° C. and a silane flow rate of 12.5 SCCM.
The same LPCVD equipment was used to deposit a silicon film at a deposition temperature of about 550 ° C, but disilane (Si ₂ H ₆ ) was used as a source gas at a deposition temperature of about 450 ° C. It can be done by PECVD method 2
It is also possible to deposit a silicon film at about 50 ° C. If the film forming temperature does not exceed the process maximum temperature of 600 ° C,
Any method may be used. Next, a second silicon film 1004 is deposited. The thickness of the second silicon film is about 300 Å or more, and the resistance value of the source / drain region after the impurity implantation is in the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 1003 to be the pad is not required. In the third embodiment, the second silicon film 1004 is deposited by the same method as that of the silicon thin film which becomes the channel portion in the first reference example. That is, monosilane was used as a source gas by the LPCVD method, and the film was deposited at a film thickness of 250 Å at a deposition temperature of 550 ° C and a silane flow rate of 100 SCCM at a deposition rate of 21.2 Å / min. Then, the same heat treatment was performed as in Reference Example 1 to enhance the crystallinity of the silicon film. That is, under a nitrogen atmosphere 60
Heat treatment was performed at 0 ° C. for 23 hours. (FIG.10 (b)).
Next, after patterning the second silicon film, a gate insulating layer 1005 was formed by the same method as in Reference Example 1.
That is, the SiO ₂ film was deposited to 1500 Å by ECR-PECVD method.
Deposited. Next, a metal film or the like to be the gate electrode is formed. In Example 3, as the gate electrode material, 2000 Å
A chromium film having a film thickness of was used. The chromium film was formed by the sputtering method at a substrate temperature of 180 ° C. The sheet resistance value of chromium immediately after film formation was 994 mΩ / □. Subsequently, a SiO ₂ film of 3000 Å was deposited on the chromium by the APCVD method at a substrate temperature of 300 ° C. After that, patterning was performed with a resist to form a protective cap layer 1007 consisting of the gate electrode 1006 and the SiO ₂ film, and impurity ions were added. In the third embodiment, phosphorus was selected as the impurity to form the n-type thin film semiconductor device, but other elements can of course be used according to the purpose. In Example 3, impurity ion addition was performed by using an ion implanter without a mass spectrometer. Using phosphine having a concentration of 5% diluted in hydrogen as a raw material gas, 5 × 1 at an acceleration voltage of 110 kV
Implanted to a density of 0 ¹⁵ 1 / cm ² . In this manner, the first silicon film and a part of the second silicon film become the source / drain regions 1008, and the protective cap layer 1007 made of the SiO ₂ film is present. The film is not ion-added and reaches the channel portion 1009 (FIG. 10C). Next, the substrate was heat-treated at 350 ° C. for 2 hours in a nitrogen atmosphere to activate the added impurity ions. After that, as an interlayer insulating film, SiO
₂ Film 1010 is deposited 5000 Å, then contact
A hole is opened and wiring 1011 is made of aluminum or the like to complete a self-aligned thin film semiconductor device (FIG. 10D).

【００５５】こうして作成したセルフ・アライン型薄膜
半導体装置のトランジスタ特性を測定した所、Ｌ＝Ｗ＝
１０μｍ、Ｖｄｓ＝４Ｖ、Ｖｇｓ＝１０Ｖでオン電流は
４．８９μＡ、ソース・ドレイン電流の最小値はＶｇｓ
＝−３．５Ｖの時０．２１ｐＡ、又Ｖｇｓ＝−１０Ｖで
定義したオフ電流は２．６５ｐＡ、電界効果移動度μｏ
＝２６．１cm² ／ｖ・ｓｅｃと極めて良好なセルフ・ア
ライン型薄膜半導体装置が出来上がった。When the transistor characteristics of the self-aligned thin film semiconductor device thus produced were measured, L = W =
10 μm, Vds = 4 V, Vgs = 10 V, ON current is 4.89 μA, minimum source / drain current is Vgs
= -3.5 V, 0.21 pA, and Vgs = -10 V, the off-current defined is 2.65 pA, and the field effect mobility μo.
= 26.1 cm ² / v · sec, which is a very good self-aligned thin film semiconductor device.

【００５６】比較の為にチャンネル部シリコン膜をＬＰ
ＣＶＤ法で６００℃で作成した他は本実施例３の本発明
と全く同一の工程でセルフ・アライン型薄膜半導体装置
を作成した。しかしながら実施例２で詳述した様に、従
来のシリコン膜では薄膜部の添加不純物元素の活性化が
なされず、薄膜部の不純物添加シリコン膜の抵抗が高過
ぎ、それ故トランジスタのオン電流は４７．９ｐＡと非
実用的となった。これに対し、本実施例３の本発明では
特性変動の主因となる水素化プラズマ処理を排除し、且
つ低温工程で窮めて良好なセルフ・アライン型薄膜半導
体装置の作成に成功した。これは参考例２で示した如く
チャンネル部シリコン膜半導体層の膜厚を５００Å以下
の薄膜化をして、基本的な半導体特性を向上せしめても
尚実施例２の本発明に依る薄膜導伝性シリコン膜の作成
に依り、薄膜部のソース・ドレイン領域の形成が低温で
容易になされた賜物で有る。即ち、ドナー又はアクセプ
ターとなる不純物の活性化は従来膜厚が１０００Å程度
以上有るシリコン膜に５５０℃程度以上の熱処理を加え
ねば達成し得なかった。この為、セルフ・アライン型薄
膜半導体装置ではチャンネル部の膜厚も必然的に１００
０Å程度以上となり、特性も悪かった。その上、ゲート
絶縁層とゲート電極が出来上がった後、添加不純物イオ
ン活性化の目的で５５０℃程度以上の熱処理が施される
為、ゲート絶縁膜の膜質劣化が生じ、水素化処理が必要
不可欠で有った。又、ゲート電極として金属材の使用が
困難であった為、ゲート線の抵抗が高かったり、ゲート
電極とゲート線を別々に作成する必要が有った。ところ
が本発明に依り、金属材料をゲート電極として使用出
来、同時にばらつきの主因で有る水素処理を排除し、よ
り簡昜な製造方法で高特性の薄膜半導体装置を安定的に
製造し得る事に成功した。For comparison, the channel silicon film is LP
A self-aligned thin film semiconductor device was manufactured by the same steps as those of the present invention of Example 3 except that the self-aligned thin film semiconductor device was manufactured by the CVD method at 600 ° C. However, as described in detail in Example 2, the conventional silicon film does not activate the doped impurity element in the thin film portion, and the resistance of the doped silicon film in the thin film portion is too high. Therefore, the on-current of the transistor is 47. It became unpractical as 0.9 pA. On the other hand, in the present invention of the third embodiment, the hydrogenated plasma treatment which is the main cause of the characteristic fluctuation is eliminated, and the good self-aligned thin film semiconductor device is successfully produced because the hydrogenated plasma treatment is limited in the low temperature process. As shown in Reference Example 2, this is because even if the film thickness of the channel portion silicon film semiconductor layer is reduced to 500 Å or less to improve the basic semiconductor characteristics, the thin film transmission according to the present invention of Example 2 is still possible. This is a result of forming the source / drain regions of the thin film portion at a low temperature easily by forming the conductive silicon film. In other words, activation of impurities serving as donors or acceptors cannot be achieved unless a silicon film having a film thickness of about 1000 Å or more is heat-treated at about 550 ° C. or more. Therefore, in the self-aligned thin film semiconductor device, the film thickness of the channel portion is necessarily 100.
It was about 0Å or more, and the characteristics were poor. In addition, after the gate insulating layer and the gate electrode are completed, heat treatment at about 550 ° C. or more is performed for the purpose of activating the additive impurity ions, so that the film quality of the gate insulating film deteriorates and hydrogenation treatment is indispensable. There was Further, since it was difficult to use a metal material as the gate electrode, the resistance of the gate line was high, and it was necessary to separately prepare the gate electrode and the gate line. However, according to the present invention, a metal material can be used as a gate electrode, and at the same time, hydrogen treatment, which is a main cause of variations, can be eliminated, and a thin film semiconductor device with high characteristics can be stably manufactured by a simpler manufacturing method. did.

【００５７】[0057]

【発明の効果】以上述べて来た様に、本発明に依れば、
基板上にシリコン膜を形成し、前記シリコン膜上に酸化
珪素膜を形成し、ドナー又はアクセプターとなる不純物
を、前記不純物元素の水素化物気体と水素気体との混合
物を原料ガスとして、質量非分離型のイオン注入装置を
用いて、前記不純物元素のイオンおよび前記不純物元素
の水素化物のイオンおよび水素イオンを所定のエネルギ
ーに加速し前記酸化珪素膜を介して前記シリコン膜に打
ち込むことにより、シリコン膜の膜質を高め得、半導体
装置の導電性特性などを大幅に改善することができる。
こうした優良な特性を有する薄膜半導体装置を大面積に
均一に簡便な手法にて形成することが可能となり、ＬＳ
Ｉの多層化や薄膜トランジスタを用いたアクティブマト
リックス液晶ディスプレイの高性能化や低価格化を実現
することができる。As described above, according to the present invention,
A silicon film is formed on a substrate, a silicon oxide film is formed on the silicon film, and impurities serving as donors or acceptors are mass-separated using a mixture of a hydride gas of the impurity element and a hydrogen gas as a source gas. Type ion implanter, the ions of the impurity element and the ions and hydrogen ions of the hydride of the impurity element are accelerated to a predetermined energy and implanted into the silicon film through the silicon oxide film to obtain a silicon film. The film quality can be improved, and the conductivity characteristics of the semiconductor device can be greatly improved.
It becomes possible to form a thin film semiconductor device having such excellent characteristics uniformly over a large area by a simple method.
It is possible to realize the multi-layered structure of I and the high performance and the low cost of the active matrix liquid crystal display using the thin film transistor.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の一実施例を示すシリコン薄膜半導体
装置製造の各工程に於ける素子断面図。FIG. 1 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

【図２】 本発明の実施例で用いた電子サイクロトロン
共鳴プラズマＣＶＤ装置の概要を示す図。FIG. 2 is a diagram showing an outline of an electron cyclotron resonance plasma CVD apparatus used in an example of the present invention.

【図３】 本発明の効果を示す図。FIG. 3 is a diagram showing the effect of the present invention.

【図４】 本発明の効果を示す図。FIG. 4 is a diagram showing an effect of the present invention.

【図５】 本発明の一実施例を示すシリコン薄膜半導体
装置の素子断面図。FIG. 5 is an element cross-sectional view of a silicon thin film semiconductor device showing an embodiment of the present invention.

【図６】 本発明の効果を示す図。FIG. 6 is a diagram showing the effect of the present invention.

【図７】 本発明の一実施例を示すシリコン薄膜半導体
装置製造の各工程に於ける素子断面図。FIG. 7 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

【図８】 本発明の一実施例を示すシリコン薄膜半導体
装置製造の各工程に於ける素子断面図。FIG. 8 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

【図９】 本発明の効果を示す図。FIG. 9 is a diagram showing the effect of the present invention.

【図１０】 本発明の一実施例を示すシリコン薄膜半導
体装置製造の各工程に於ける素子断面図。FIG. 10 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０１…下地基板 １０２…下地保護膜 １０３…ソース・ドレイン領域 １０４…シリコン薄膜 １０５…チャンネル部シリコン薄膜 １０６…ゲート絶縁膜 １０７…ゲート電極 １０８…層間絶縁膜 １０９…ソース・ドレイン取り出し電極 ２０１…導波管 ２０２…反応室 ２０３…ガス導入管 ２０４…外部コイル ２０５…基板 ２０６…ヒータ ２０７…ガス導入管 ５０１…ソース・ドレイン領域 ５０２…ゲート電極 ５０３…ソース・ドレイン領域 ５０４…ゲート電極 ５０５…ゲート電極 ５０６…マスク材 ５０７…ソース・ドレイン領域 ７０１…基板 ７０２…下地保護膜 ７０３…パッドとなるシリコン膜 ７０４…第二のシリコン膜 ７０５…ゲート絶縁層 ７０６…ゲート電極 ７０７…レジスト ７０８…ソース・ドレイン領域 ７０９…チャンネル部シリコン膜 ７１０…層間絶縁膜 ７１１…配線 ８０１…絶縁基板 ８０２…下地ＳｉＯ₂膜 ８０３…不純物を含んだシリコン薄膜 ８０４…ソース・ドレイン領域 ８０５…アモルファス・シリコン薄膜 ８０６…いずれチャンネル部になる位置に丈残されたア
モルファス・シリコン薄膜 ８０７…酸素プラズマ ８０８…アモルファス・シリコン薄膜を酸化して形成し
たＳｉＯ₂膜 ８０９…いずれチャンネル部となる残留しているアモル
ファス・シリコン薄膜 ８１０…ＥＣＲ−ＰＥＣＶＤ法で堆積したＳｉＯ₂膜 ８１１…チャンネル部を構成するシリコン薄膜 ８１２…ゲート電極 ８１３…ソース・ドレイン取り出し電極 １００１…基板 １００２…下地保護膜 １００３…パッドとなるシリコン膜 １００４…第二のシリコン膜 １００５…ゲート絶縁層 １００６…ゲート電極 １００７…保護キャップ層 １００８…ソース・ドレイン領域 １００９…チャンネル部シリコン膜 １０１０…層間絶縁膜 １０１１…配線Reference numeral 101 ... Base substrate 102 ... Base protection film 103 ... Source / drain region 104 ... Silicon thin film 105 ... Channel silicon thin film 106 ... Gate insulating film 107 ... Gate electrode 108 ... Interlayer insulating film 109 ... Source / drain extraction electrode 201 ... Waveguide Tube 202 ... Reaction chamber 203 ... Gas introduction tube 204 ... External coil 205 ... Substrate 206 ... Heater 207 ... Gas introduction tube 501 ... Source / drain region 502 ... Gate electrode 503 ... Source / drain region 504 ... Gate electrode 505 ... Gate electrode 506 Mask material 507 Source / drain region 701 Substrate 702 Base protection film 703 Pad silicon film 704 Second silicon film 705 Gate insulating layer 706 Gate electrode 707 Resist 708 Source / drain region 709 ... Channel silicon film 7 0 ... left length in the interlayer insulating film 711 ... wiring 801: insulating substrate 802 ... base SiO ₂ film 803 ... it becomes silicon thin film 804 ... source-drain regions 805 ... amorphous silicon thin film 806 ... one channel unit containing impurities position amorphous silicon thin film 807 ... oxygen plasma 808 ... SiO ₂ deposited with amorphous silicon thin SiO ₂ film 809 ... one channel unit to become remaining to have amorphous silicon thin film 810 ... ECR-PECVD method was formed by oxidizing a Film 811 ... Silicon thin film 812 constituting channel section ... Gate electrode 813 ... Source / drain extraction electrode 1001 ... Substrate 1002 ... Base protective film 1003 ... Silicon film 1004 serving as pad ... Second silicon film 1005 ... Gate insulating layer 1006 ... Gate electrode 1 07 ... protective cap layer 1008 ... source and drain regions 1009 ... channel portion silicon film 1010 ... interlayer insulating film 1011 ... wire

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−194620（ＪＰ，Ａ) 特開 平１−22027（ＪＰ，Ａ) 特開 昭59−218728（ＪＰ，Ａ) 特開 昭59−218727（ＪＰ，Ａ)   ─────────────────────────────────────────────────── ─── Continued front page       (56) Reference JP-A-2-194620 (JP, A)                 JP-A 1-22027 (JP, A)                 JP 59-218728 (JP, A)                 JP-A-59-218727 (JP, A)

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ６００℃以下で基板上にシリコン膜を形
成する工程と、 ６００℃以下の熱処理によって前記シリコン膜の結晶性
を高める工程と、 プラズマを照射して前記シリコン膜上に酸化珪素膜を堆
積する工程と、 ドナー又はアクセプターとなる不純物の水素化物気体と
水素気体との混合物を原料ガスとして、質量非分離型の
イオン注入装置により、前記不純物元素のイオンおよび
前記不純物元素の水素化物のイオンおよび水素イオンを
所定のエネルギーに加速し前記酸化珪素膜を介して前記
シリコン膜に打ち込む工程とを有することを特徴とする
薄膜半導体装置の製造方法。1. A step of forming a silicon film on a substrate at 600 ° C. or lower, a step of increasing crystallinity of the silicon film by heat treatment at 600 ° C. or lower, and a plasma irradiation to irradiate the silicon film on the silicon film. And a mixture of an hydride gas of an impurity serving as a donor or an acceptor and a hydrogen gas as a source gas, by a mass non-separation type ion implanter, the ion of the impurity element and the hydride of the impurity element are And a step of accelerating ions and hydrogen ions to a predetermined energy and implanting them into the silicon film through the silicon oxide film. 【請求項２】 前記酸化珪素膜を電子サイクロトロン共
鳴プラズマＣＶＤ法により形成することを特徴とする請
求項１記載の薄膜半導体装置の製造方法。2. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the silicon oxide film is formed by an electron cyclotron resonance plasma CVD method.