JP3038898B2 - Method for manufacturing thin film semiconductor device - Google Patents
Method for manufacturing thin film semiconductor deviceInfo
- Publication number
- JP3038898B2 JP3038898B2 JP2310475A JP31047590A JP3038898B2 JP 3038898 B2 JP3038898 B2 JP 3038898B2 JP 2310475 A JP2310475 A JP 2310475A JP 31047590 A JP31047590 A JP 31047590A JP 3038898 B2 JP3038898 B2 JP 3038898B2
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- Japan
- Prior art keywords
- film
- thin film
- silicon
- semiconductor device
- substrate
- Prior art date
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアクティブマトリックス液晶ディスプレイ等
に応用される薄膜トランジスタや三次元LSIデバイスな
ど、絶縁性物質上に作成される薄膜半導体装置の製造方
法に関するもので有り、詳しくは製造工程の最高温度が
600℃程度以下の低温プロセスで形成する薄膜半導体装
置の製造方法に関する。The present invention relates to a method for manufacturing a thin film semiconductor device formed on an insulating material such as a thin film transistor and a three-dimensional LSI device applied to an active matrix liquid crystal display and the like. In detail, the maximum temperature of the manufacturing process
The present invention relates to a method for manufacturing a thin film semiconductor device formed by a low-temperature process of about 600 ° C. or less.
近年液晶ディスプレイの大画面化、高解像度化に伴
い、その駆動方式は単純マトリックス方式からアクティ
ブマトリックス方式へと移行し、大容量の情報を表示出
来る様になりつつ有る。アクティブマトリックス方式は
数十万を超える画素を有する液晶ディスプレイが可能で
あり、各画素毎にスイッチングトランジスタを形成する
もので有る。各種液晶ディスプレイの基板としては、透
過型ディスプレイを可能ならしめる溶融石英板やガラス
などの透明絶縁基板が使用されている。In recent years, with the increase in screen size and resolution of liquid crystal displays, the driving system has shifted from a simple matrix system to an active matrix system, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmission type display is used.
しかしながら、表示画面の拡大化や低価格化を進める
場合には絶縁基板として安価な通常ガラスを使用するの
が必要不可欠で有る。従って、この経済性を維持して
尚、アクティブマトリックス方式の液晶ディスプレイを
動作させる薄膜トランジスタを安価なガラス基板上に安
定した性能で形成する事が可能な技術が望まれていた。However, in order to increase the size of the display screen and reduce the cost, it is essential to use inexpensive ordinary glass as the insulating substrate. Accordingly, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining this economic efficiency.
従来この様な薄膜トランジスタを作成する場合、チャ
ンネル部シリコン層を形成した後、ゲート絶縁層を形成
するには、基板を酸素（O2）、笑気ガス（N2O）、水蒸
気（H2O）などを含む酸化性雰囲気下に***し、その温
度を800℃から1100℃程度の高温として、チャンネル部
シリコン層の一部を酸化し、ゲート絶縁層を形成する熱
酸化法が用いられていた。或いは、チャンネル部シリコ
ン層形成後、モノシラン（SiH4）、酸素（O2）などを原
料ガスとして常圧気相化学堆積法（APCVD法）等の気相
成長法で二酸化硅素膜（SiO2膜）を堆積し、ゲート絶縁
層としていた。Conventionally, when such a thin film transistor is formed, after forming a channel portion silicon layer and then forming a gate insulating layer, the substrate is formed of oxygen (O 2 ), laughing gas (N 2 O), water vapor (H 2 O). The thermal oxidation method was used in which the gate insulating layer was formed by oxidizing a part of the silicon layer in the channel section by inserting the film in an oxidizing atmosphere containing) and raising the temperature to about 800 ° C to 1100 ° C. . Alternatively, after the silicon layer in the channel is formed, a silicon dioxide film (SiO 2 film) is formed by a vapor phase growth method such as atmospheric pressure chemical vapor deposition (APCVD) using monosilane (SiH 4 ), oxygen (O 2 ) or the like as a source gas. Was deposited to form a gate insulating layer.
しかしながら、先に述べた従来の方法に於いては、数
多くの問題が指摘されている。まず第一に熱酸化法に依
るSiO2膜の形成では、その形成に少なくとも800℃以上
の高温熱処理が伴う為、酸化膜より下部に位置する薄膜
層や基板などの耐熱性が問題となる。例えば大面積液晶
ディスプレイのスイッチング・トランジスタを作成する
場合、基板としては非常に高価な溶融石英板以外は斯様
な高温に耐え得ない。又、三次元LSI素子に於いても下
層部トランジスタが高温で劣化する為、この熱酸化法は
事実上使用不可能となっている。However, a number of problems have been pointed out in the conventional method described above. First, in the formation of a SiO 2 film by a thermal oxidation method, a high-temperature heat treatment of at least 800 ° C. or more is involved in the formation, and thus the heat resistance of the thin film layer and the substrate located below the oxide film becomes a problem. For example, when producing a switching transistor for a large-area liquid crystal display, a substrate other than a very expensive fused silica plate cannot withstand such high temperatures. Further, even in a three-dimensional LSI element, since the lower layer transistor deteriorates at high temperature, this thermal oxidation method is practically unusable.
一方APCVD法など気相反応を利用した絶縁膜堆積方法
では基板温度が750℃程度以下とした低温に依る絶縁膜
堆積が可能である。これに依り酸化膜下の薄膜層の保護
や耐熱性の低い安価なガラス基板の使用が可能となる。
しかしながら、気相成長方に依り形成された絶縁層は一
般に膜質が悪く、しかもチャンネル部シリコン半導体層
と絶縁層との界面を清掃に保つ事が困難な為、動作特性
の優れたMIS型薄膜半導体装置を低温で形成するのは困
難であった。On the other hand, an insulating film deposition method using a gas phase reaction such as the APCVD method can deposit an insulating film at a low temperature of about 750 ° C. or less. This makes it possible to protect the thin film layer below the oxide film and use an inexpensive glass substrate with low heat resistance.
However, the insulating layer formed by vapor phase growth generally has poor film quality, and it is difficult to keep the interface between the channel silicon semiconductor layer and the insulating layer clean. It was difficult to form the device at low temperatures.
従って高温熱処理と同等もしくはそれ以上の効果をも
たらし得る良質なSiO2膜の低温製造方法の開発が期待さ
れていた。Therefore, development of a low-temperature manufacturing method of a high-quality SiO 2 film that can provide an effect equal to or higher than the high-temperature heat treatment has been expected.
本発明は上記の事情に鑑みてなされたもので、その目
的とする所はシリコン層をチャンネル部とするMIS型薄
膜半導体装置に於いて、低温工程で良好な半導体装置特
性を有する界面及び絶縁層を形成することに有る。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an interface and an insulating layer having good semiconductor device characteristics in a low-temperature process in an MIS type thin film semiconductor device having a silicon layer as a channel portion. Is formed.
本発明の薄膜半導体装置の製造方法は、基板上にチャ
ネルとなる第１シリコン膜を形成する工程と、前記第１
シリコン膜上にアモルファスシリコンからなる第２シリ
コン膜を形成する工程と、前記第２シリコン膜上に酸素
プラズマを照射する工程と、前記酸素プラズマを照射す
る工程に連続して前記第２シリコン膜上にゲート絶縁膜
となる酸化シリコン膜を形成する工程と、前記酸化シリ
コン膜上にゲート電極を形成する工程とを有することを
特徴とする。In the method of manufacturing a thin film semiconductor device according to the present invention, a step of forming a first silicon film serving as a channel on a substrate;
Forming a second silicon film made of amorphous silicon on the silicon film; irradiating the second silicon film with oxygen plasma; and irradiating the oxygen plasma with the second silicon film. Forming a silicon oxide film to be a gate insulating film, and forming a gate electrode on the silicon oxide film.
本発明は表層部がアモルファス・シリコンから成るチ
ャンネル部シリコン層に酸素プラズマを照射する事に依
り、前記アモルファス・シリコンを酸化し、ゲート絶縁
層の一部位を低温で形成し、しかも半導体層と絶縁層と
の界面を浄化化させる事に依り薄膜半導体装置の特性を
向上させた物で有る。The present invention oxidizes the amorphous silicon by irradiating oxygen plasma to a channel silicon layer having a surface layer made of amorphous silicon, thereby forming one part of a gate insulating layer at a low temperature, and furthermore, insulating the semiconductor layer from the semiconductor layer. This is one in which the characteristics of the thin film semiconductor device are improved by purifying the interface with the layer.
〔実施例１〕 以下本発明の実施例を図面を用いて詳述するが、本発
明が以下の実施例に限定されるものではない。Example 1 Hereinafter, an example of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following example.
第１図ａ〜ｈはMIS型電界効果トランジスタを形成す
るシリコン薄膜半導体装置の製造工程を断面で示した図
である。1a to 1h are cross-sectional views showing the steps of manufacturing a silicon thin film semiconductor device for forming an MIS field effect transistor.
本実施例では絶縁基板101として235mm□の石英ガラス
を用いたが、600℃の温度に耐え得る基板又は下地物水
で有るならば、その種類や大きさは無論問われない。例
えばシリコンウェハー上に形成された三次元LSIなども
下地基板として可能で有る。まず有機洗浄及び酸洗浄し
た石英ガラス基板101上面に下地SiO2膜102をAPCVD法で
堆積する。下地SiO2膜102の形成は基板温度300℃シラン
流量120SCCM、酸素840SCCM、窒素約140SLM堆積速度3.9
Å/Secの条件で行ない、堆積された膜厚は2000Åで有
る。次にドナー又はアクセプターとなる不純物を含んだ
シリコン薄膜103を減圧気相化学堆積法（LPCVD法）にて
堆積した。（第１図ａ）本実施例１では不純物としてリ
ンを選び、フォスフィン（PH3）0.03SCC、モノシラン
（SiH4）200SCCMを原料ガスとして堆積温度600℃で1500
Å堆積した。この時の堆積速度は30Å/minで成膜直後の
シート抵抗値は1951Ω／□で有った。次に前記シリコン
薄膜103上にレジストを形成し、四弗化炭素（CF4）、酸
素（O2）、窒素（N2）等の混合プラズマやパターニング
を行ない、ソース・ドレイン領域104を形成した。続い
て該領域104表面上の汚物・自然酸化膜を取り除いた
後、直ちに、いずれチャンネル部を構成する事になるシ
リコン薄膜105といずれプラズマ照射されるアモルファ
ス・シリコン薄膜106を減圧CVD法で連続して堆積した。
（第１図ｂ）本実施例に於ける減圧CVD装置は容積184.5
で反応室側壁及び天井は石英ガラスから成っている。
石英ガラスで作成された反応室の外側には３ゾーンに分
かれたヒーターが設置されており、それらを独立に調整
する事で反応室内中央部付近に所望の温度で等温領域を
形成する。基板はこの等温領域内に水平に設置して、シ
リコン薄膜105及びアモルファス・シリコン薄膜106を堆
積した。シリコン薄膜105は原料ガスとしてモノシラン
（SiH4）11.25SCCMを用い堆積温度600℃で、20分39秒間
堆積した。希釈ガスは用いず、この時の反応室内圧力は
7.90mTorrで有った。予備実験に依ると、この条件での
堆積速度は、12.105Å/minでシリコン薄膜105は約250Å
堆積されたはずで有る。続いて、基板を減圧CVD装置か
ら取り出す事なく連続してアモルファス・シリコン薄膜
106を堆積した。アモルファス・シリコン薄膜106の堆積
温度は550℃で有った。シリコン薄膜105は600℃で堆積
された為、アモルファス・シリコン膜106を堆積するの
に約１時間程度の降温期間が必要で有る。この降温期間
中、本実施例ではメカニカル・ブースター・ポンプとロ
ータリー・ポンプを運転状態に保ち、反応室には97％ア
ルゴンと３％水素の混合ガスを1SLM流し続けた。この時
の反応室の圧力は186.5mTorrで有った。本実施例１では
シリコン薄膜105とアモルファス・シリコン薄膜106との
間に酸化膜が介さず、連続したシリコン界面が形成され
る様、還元性減圧雰囲気で降温を行ったが、充分純度の
高い不活性ガスで、この条件を満たし得るならば不活性
減圧雰囲気でも可能で有る。この様にしてシリコン薄膜
105の表面を清浄に維持したまま反応室温度を550℃迄下
げて、連続してアモルファス・シリコン薄膜106を堆積
した。原料ガスとしてモノシラン（SiH4）30SCCMを用
い、５分22秒間堆積した。希釈ガスは用いなかったが、
排気系に付属しているコンダクタンス・バルブの開閉を
調整する事で反応室内の圧力を282mTorrに保った。予備
実験に依ると、この同じ条件で堆積速度は、14.907Å/m
inで、アモルファス・シリコン薄膜106は約80Å堆積さ
れたはずで有る。次にこうして作成されたシリコン薄膜
105とアモルファス・シリコン薄膜106上にレジストを形
成し、四弗化炭素（CF4）、酸素（O2）、窒素（N2）等
の混合プラズマでパターニングを行った。（第１図
ｃ）。この時、チャンネル部シリコン薄膜107とアモル
ファス・シリコン薄膜108の合算膜厚を表面粗さ計で測
った所310Åで有った。In the present embodiment, quartz glass of 235 mm square is used as the insulating substrate 101, but the type and size of the substrate or the substrate water is not limited as long as the substrate or the substrate water can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer can be used as a base substrate. First, a base SiO 2 film 102 is deposited on an upper surface of a quartz glass substrate 101 that has been subjected to organic cleaning and acid cleaning by an APCVD method. The base SiO 2 film 102 is formed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM, and nitrogen of about 140 SLM.
Performed under the condition of Å / Sec, the deposited film thickness is 2000 Å. Next, a silicon thin film 103 containing an impurity serving as a donor or an acceptor was deposited by a low pressure chemical vapor deposition (LPCVD) method. (FIG. 1a) In Example 1, phosphorus was selected as an impurity, and phosphine (PH 3 ) 0.03 SCC and monosilane (SiH 4 ) 200 SCCM were used as source gases at a deposition temperature of 600 ° C. and 1500 ° C.
Å Deposited. At this time, the deposition rate was 30 ° / min, and the sheet resistance immediately after film formation was 1951 Ω / □. Next, a resist was formed on the silicon thin film 103, and mixed plasma or patterning of carbon tetrafluoride (CF 4 ), oxygen (O 2 ), nitrogen (N 2 ), etc. was performed to form a source / drain region 104. . Subsequently, immediately after removing the contaminant / natural oxide film on the surface of the region 104, the silicon thin film 105 which will eventually constitute the channel portion and the amorphous silicon thin film 106 which will be irradiated with plasma will be continuously formed by the low pressure CVD method. Deposited.
(FIG. 1b) The reduced pressure CVD apparatus in this embodiment has a capacity of 184.5
The reaction chamber side walls and ceiling are made of quartz glass.
Outside the reaction chamber made of quartz glass, heaters divided into three zones are installed, and by independently adjusting them, an isothermal region is formed at a desired temperature near the center of the reaction chamber. The substrate was placed horizontally in this isothermal region, and a silicon thin film 105 and an amorphous silicon thin film 106 were deposited. The silicon thin film 105 was deposited at a deposition temperature of 600 ° C. for 20 minutes and 39 seconds using monosilane (SiH 4 ) 11.25 SCCM as a source gas. No diluent gas was used, and the reaction chamber pressure at this time was
7.90mTorr. According to preliminary experiments, the deposition rate under these conditions is 12.105Å / min, and the silicon thin film 105 is about 250Å
Should have been deposited. Subsequently, the amorphous silicon thin film is continuously taken out without taking out the substrate from the low pressure CVD equipment.
106 deposited. The deposition temperature of the amorphous silicon thin film 106 was 550 ° C. Since the silicon thin film 105 was deposited at 600 ° C., a temperature reduction period of about one hour is required to deposit the amorphous silicon film 106. During this cooling period, in this embodiment, the mechanical booster pump and the rotary pump were kept in operation, and a mixed gas of 97% argon and 3% hydrogen was continuously supplied to the reaction chamber by 1 SLM. At this time, the pressure in the reaction chamber was 186.5 mTorr. In the first embodiment, the temperature was reduced in a reducing pressure-reducing atmosphere so that an oxide film was not interposed between the silicon thin film 105 and the amorphous silicon thin film 106 so that a continuous silicon interface was formed. As long as this condition can be satisfied with an active gas, an inert reduced pressure atmosphere is also possible. In this way, a silicon thin film
The temperature of the reaction chamber was lowered to 550 ° C. while the surface of 105 was kept clean, and an amorphous silicon thin film 106 was continuously deposited. Monosilane (SiH 4 ) 30 SCCM was used as a source gas, and deposition was performed for 5 minutes and 22 seconds. No diluent gas was used,
The pressure inside the reaction chamber was maintained at 282 mTorr by adjusting the opening and closing of the conductance valve attached to the exhaust system. According to preliminary experiments, the deposition rate under these same conditions was 14.907Å / m
In, the amorphous silicon thin film 106 should have been deposited at about 80 °. Next, the silicon thin film thus created
A resist was formed on 105 and the amorphous silicon thin film 106, and was patterned by a mixed plasma of carbon tetrafluoride (CF 4 ), oxygen (O 2 ), nitrogen (N 2 ), and the like. (FIG. 1c). At this time, the total film thickness of the channel portion silicon thin film 107 and the amorphous silicon thin film 108 was 310 ° when measured by a surface roughness meter.
次に、この基板を沸騰している60％濃度の消散にて洗
浄し、更に1.67％弗化水素酸水溶液に20秒間浸してソー
ス・ドレイン領域104上とアモルファス・シリコン薄膜1
08上の自然酸化膜を取り除いて洗浄なシリコン表面が現
われた後、直ちに電子サイクロトロン共鳴プラズマCVD
装置（ECR−PECVD装置）にて酸素プラズマ109を照射し
た。（第１図ｄ）本実施例１で用いたECR−PECVD装置の
概要を第２図に示す。酸素プラズマは2.45GHzのマイク
ロ波を導波管201を通じて反応室202に導き、100SCCMの
酸素をガス導入管203から導入して酸素プラズマを立て
た。この時、反応室内の圧力は1.80mTorrで、マイクロ
波の出力は2500Wで有った。反応室の外側には外部コイ
ル204が設けられて居り、酸素プラズマに875Gaussの磁
場を掛けてプラズマ中の電子にECR条件を満足せしめて
いる。基板205はプラズマに対して垂直に置かれ、ヒー
ター206に依り基板温度が300℃となる様保たれている。
この条件で酸素プラズマ109を８分20秒間照射して、ア
モルファス・シリコン薄膜108の酸化を行ない、ゲート
絶縁層の一部位となるSiO2膜110を得た。（第１図ｅ）
更に真空を破る事なく連続して、ゲート絶縁層となるSi
O2膜111を該基板上に堆積した。（第１図ｆ）このSiO2
膜はマイクロ波出力2,250W、シラン流量60SCCM、酸素流
量100SCCM、基板温度300℃で18.75秒間堆積した。堆積
中に於ける反応室内圧力は2.65mTorrで有った。こうし
て形成した多層膜を多波長分散型偏光解析法（多波長分
光エリプソメトリー：ソープラ社MOSS−ES4G）を用い
て、残留しているチャンネル部シリコン膜112の膜厚
と、アモルファス・シリコン膜を酸化して形成したSiO2
膜110及びECR−PECVD法で堆積したSiO2膜111の合算SiO2
膜の膜厚を測定した所、其々219Åと1480Åで有った。Next, the substrate is washed by dissipating in a boiling 60% concentration, and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to form a film on the source / drain region 104 and the amorphous silicon thin film 1.
Immediately after the natural silicon oxide film was removed and a clean silicon surface appeared, electron cyclotron resonance plasma CVD was performed.
The apparatus was irradiated with oxygen plasma 109 using an apparatus (ECR-PECVD apparatus). (FIG. 1d) The outline of the ECR-PECVD apparatus used in the first embodiment is shown in FIG. As the oxygen plasma, a microwave of 2.45 GHz was guided to the reaction chamber 202 through the waveguide 201, and 100 SCCM of oxygen was introduced from the gas introduction tube 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.80 mTorr, and the microwave output was 2500 W. An external coil 204 is provided outside the reaction chamber, and a magnetic field of 875 Gauss is applied to the oxygen plasma to satisfy the ECR condition for the electrons in the plasma. The substrate 205 is placed perpendicular to the plasma, and the temperature of the substrate is kept at 300 ° C. by the heater 206.
Under this condition, the amorphous silicon thin film 108 was oxidized by irradiating oxygen plasma 109 for 8 minutes and 20 seconds to obtain an SiO 2 film 110 as one portion of the gate insulating layer. (Fig. 1e)
In addition, without breaking the vacuum, Si
An O 2 film 111 was deposited on the substrate. (FIG. 1f) This SiO 2
The film was deposited at a microwave output of 2,250 W, a silane flow rate of 60 SCCM, an oxygen flow rate of 100 SCCM, and a substrate temperature of 300 ° C. for 18.75 seconds. The pressure in the reaction chamber during deposition was 2.65 mTorr. Using the multi-wavelength dispersion ellipsometry (multi-wavelength spectroscopic ellipsometry: MOSS-ES4G by Sopra), the film thickness of the remaining channel silicon film 112 and the amorphous silicon film are oxidized. SiO 2 formed by
The sum of SiO 2 film 111 was deposited in film 110 and ECR-PECVD method SiO 2
When the film thickness was measured, they were 219Å and 1480Å, respectively.
次にクロムをスパッター法で1500Å堆積し、パターニ
ングに依りゲート電極113を形成した。（第１図ｇ）こ
の時シート抵抗値は1.36Ω／□で有った。その後、ゲー
ト絶縁膜にコンタクトホールを開け、ソース・ドレイン
取り出し電極114をスパッター法などで形成し、パター
ニングを行なう事でトランジスタは完成する（第１図
ｈ）。本実施例１では、ソース・ドレイン取り出し電極
材料として、膜厚8,000Åのアルミニウムを用いた。こ
の時のアルミニウムのシート抵抗値は42mΩ／□で有っ
た。Next, chromium was deposited at 1500 ° by a sputtering method, and a gate electrode 113 was formed by patterning. (FIG. 1g) At this time, the sheet resistance was 1.36 Ω / □. Thereafter, a contact hole is opened in the gate insulating film, a source / drain extraction electrode 114 is formed by a sputtering method or the like, and patterning is performed to complete the transistor (FIG. 1H). In Example 1, aluminum having a thickness of 8,000 mm was used as a source / drain extraction electrode material. At this time, the sheet resistance value of aluminum was 42 mΩ / □.
この様にして試作した薄膜トランジスタ（TFT）の特
性の一例Vgs−Ids曲線を第３図３−ａに示した。ここで
Idsはソース・ドレイン電流、Vgsはゲート電圧で、ソー
ス・ドレイン電圧Vds＝4V、温度25℃で測定した。トラ
ンジスタ・サイズはチャンネル部の長さＬ＝10μｍ、幅
Ｗ＝100μｍで有った。Vds＝4V、Vgs＝10Vでトランジス
タをオンさせた時のオン電流はIds＝7.1μＡ、Idsが最
小となるオフ電流はVds＝4V、Vgs＝0VでIds＝0.33PAと
なり、オン・オフ比は７桁以上の良好なトランジスタ特
性を有する薄膜トランジスタが得られた。又、このトラ
ンジスタの飽和電流領域より求めた電界効果易動度は5.
07cm2/V・Secで有った。第３図３−ｂには比較の為に、
アモルファス・シリコン薄膜を堆積せず、かつ酸素プラ
ズマ照射も行なわない他は総て前記工程と同一で作成し
たと云う、従来のTFTの特性を示した。この従来のTFTの
オン電流はIds＝4.5μＡ、オフ電流Ids＝0.87PAで、電
界効果易動度は、4.34cm2/V・Secで有った。An example V gs -I ds curve characteristics of the thin film transistor was fabricated in this way (TFT) as shown in FIG. 3 3-a. here
I ds is a source / drain current, V gs is a gate voltage, and measured at a source / drain voltage V ds = 4 V and a temperature of 25 ° C. The transistor size was such that the length L of the channel portion was 10 μm and the width W was 100 μm. V ds = 4V, V gs = 10V ON current when turn on the transistor in the I ds = 7.1μA, off-current is V ds = 4V which I ds is minimized, V gs = at 0V I ds = 0.33 Pa As a result, a thin film transistor having good transistor characteristics with an on / off ratio of 7 digits or more was obtained. The field effect mobility calculated from the saturation current region of this transistor is 5.
It was 07cm 2 / V · Sec. FIG. 3B shows, for comparison,
The characteristics of the conventional TFT were shown in that all the steps were the same as those described above except that no amorphous silicon thin film was deposited and oxygen plasma irradiation was not performed. The on current of this conventional TFT was I ds = 4.5 μA, the off current I ds = 0.87 PA, and the field effect mobility was 4.34 cm 2 / V · Sec.
こうした結果から、従来例に比べて、本発明に依って
薄膜半導体装置の特性が向上している事が分かる。From these results, it can be seen that the characteristics of the thin film semiconductor device are improved according to the present invention as compared with the conventional example.
これはMIS型電界効果トランジスタでそのトランジス
タ特性に多大な影響を及ぼす半導体層と絶縁層の界面を
アモルファス・シリコン薄膜の酸素プラズマ照射酸化と
云う方法で形成した為、清浄な半導体層絶縁層界面が得
られた結果で有る。この事は第３図に於いて本発明の実
施例３−ａが従来例３−ｂよりも、ゲート電圧0V付近で
の立上がりが急峻になっている事からも裏付けられる。This is an MIS type field effect transistor. Since the interface between the semiconductor layer and the insulating layer, which greatly affects the transistor characteristics, is formed by a method called oxygen plasma irradiation oxidation of an amorphous silicon thin film, a clean semiconductor layer insulating layer interface is formed. This is the result obtained. This is supported by the fact that the embodiment 3-a of the present invention has a steeper rise near the gate voltage 0V than the conventional example 3-b in FIG.
〔実施例２〕 ECR−PECVD装置にて酸素プラズマを照射する時間を除
いて、その他の工程は総て実施例１と同じ工程で薄膜ト
ランジスタを作成した。本実施例２では、アモルファス
・シリコン薄膜をECR−プラズマ酸化させる為の酸素プ
ラズマ照射時間は４分10秒間で有った。これ以外は総て
実施例１と全く同じ条件で工程を進めた所、本実施例２
では残留しているチャンネル部シリコン膜の膜厚は249
Åで有り、アモルファス・シリコン膜を酸化して形成し
たSiO2膜及びECR・PECVD法で堆積したSiO2膜の合算SiO2
膜の膜厚は1,431Åで有った。こうして作成したTFTのオ
ン電流はIds＝7.6μＡ、オフ電流Ids＝0.32PAで電界効
果易動度は5.15cm2/V・Secで有った。Example 2 A thin film transistor was formed in the same manner as in Example 1 except for the time for irradiating oxygen plasma with an ECR-PECVD apparatus. In Example 2, the oxygen plasma irradiation time for the ECR-plasma oxidation of the amorphous silicon thin film was 4 minutes and 10 seconds. Except for this point, the process was carried out under exactly the same conditions as in Example 1;
The remaining channel silicon film thickness is 249
There in Å, sum of SiO 2 SiO 2 film an amorphous silicon film deposited by the SiO 2 film and the ECR-PECVD method formed by oxidizing
The thickness of the film was 1,431 mm. TFT of the on-current that was created in this way there was in I ds = 7.6μA, the off-state current I ds = field-effect mobility in 0.32PA 5.15cm 2 / V · Sec.
本実施例２に於いても、本発明に依り薄膜半導体装置
の特性が向上する事が分る。Also in the second embodiment, it can be seen that the characteristics of the thin film semiconductor device are improved according to the present invention.
以上述べて来た様に、本発明に依れば、表面が絶縁性
物質で有る基板上への薄膜半導体装置の形成に於いて、
チャンネル部シリコン膜堆積後不活性又は還元性減圧雰
囲気を破る事なく連続して該チャネル部シリコン膜上に
アモルファス・シリコン膜を堆積し、更に前記アモルフ
ァス・シリコン膜上にゲート絶縁層を形成する前に、前
記アモルファス・シリコン膜上に酸素プラズマを照射す
る事により、良好なトランジスタ特性を有する薄膜半導
体装置を製造する事が可能となり、LSIの多層化や薄膜
トランジスタを用いたアクティブマトリックス液晶ディ
スプレイの高性能化を実現すると云う多大な効果を有す
る。As described above, according to the present invention, in forming a thin-film semiconductor device on a substrate whose surface is an insulating material,
After depositing an amorphous silicon film on the channel silicon film continuously without breaking the inert or reducing reduced pressure atmosphere after depositing the channel silicon film, and before forming a gate insulating layer on the amorphous silicon film, In addition, by irradiating the amorphous silicon film with oxygen plasma, it is possible to manufacture a thin film semiconductor device having good transistor characteristics, thereby realizing high performance of an active matrix liquid crystal display using multilayer LSIs and thin film transistors. This has a great effect of realizing the structure.
第１図（ａ）〜（ｈ）は本発明の一実施例を示すシリコ
ン薄膜半導体装置製造の各工程に於ける素子断面図。 第２図は本発明の実施例に於いて酸素プラズマ照射及び
ゲート絶縁層の一部位となるSiO2膜堆積に用いた電子サ
イクロトロン共鳴プラズマCVD装置の概要を示す図。 第３図は本発明の効果を示す図。 101……絶縁基板 102……下地SiO2膜 103……不純物を含んだシリコン薄膜 104……ソース・ドレイン領域 105……シリコン薄膜 106……アモルファス・シリコン薄膜 107……チャンネル部シリコン薄膜 108……アモルファス・シリコン薄膜 109……酸素プラズマ 110……アモルファス・シリコン薄膜を酸化して形成し
たSiO2膜 111……ECR・PECVD法で堆積したSiO2膜 112……残留しているチャンネル部シリコン膜 113……ゲート電極 114……ソース・ドレイン取り出し電極 201……導波管 202……反応室 203……ガス導入管 204……外部コイル 205……基板 206……ヒーター1 (a) to 1 (h) are cross-sectional views of an element in each step of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention. FIG. 2 is a view showing an outline of an electron cyclotron resonance plasma CVD apparatus used for oxygen plasma irradiation and deposition of a SiO 2 film which is a part of a gate insulating layer in an embodiment of the present invention. FIG. 3 is a view showing the effect of the present invention. 101: insulating substrate 102: base SiO 2 film 103: silicon thin film containing impurities 104: source / drain region 105: silicon thin film 106: amorphous silicon thin film 107: channel silicon thin film 108: amorphous silicon thin film 109 ...... oxygen plasma 110 ...... SiO 2 film 111 ...... SiO was deposited by ECR-PECVD method 2 film 112 ...... residue to which the channel portion silicon film 113 of amorphous silicon thin film was formed by oxidizing ... gate electrode 114 ... source / drain extraction electrode 201 ... waveguide 202 ... reaction chamber 203 ... gas introduction tube 204 ... external coil 205 ... substrate 206 ... heater
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/786 H01L 21/336 H01L 21/205 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/786 H01L 21/336 H01L 21/205
Claims (2)
形成する工程と、前記第１シリコン膜上にアモルファス
シリコンからなる第２シリコン膜を形成する工程と、前
記第２シリコン膜上に酸素プラズマを照射する工程と、
前記酸素プラズマを照射する工程に連続して前記第２シ
リコン膜上にゲート絶縁膜となる酸化シリコン膜を形成
する工程と、前記酸化シリコン膜上にゲート電極を形成
する工程とを有することを特徴とする薄膜半導体装置の
製造方法。A step of forming a first silicon film serving as a channel on a substrate; a step of forming a second silicon film made of amorphous silicon on the first silicon film; and a step of forming oxygen on the second silicon film. Irradiating plasma;
A step of forming a silicon oxide film serving as a gate insulating film on the second silicon film following the step of irradiating the oxygen plasma; and a step of forming a gate electrode on the silicon oxide film. Of manufacturing a thin film semiconductor device.
元性減圧雰囲気を破ることなく連続して前記第１シリコ
ン膜上に前記第２シリコン膜を形成することを特徴とす
る請求項１に記載の薄膜半導体装置の製造方法。2. The method according to claim 1, wherein after forming the first silicon film, the second silicon film is continuously formed on the first silicon film without breaking an inert or reducing reduced pressure atmosphere. 3. The method for manufacturing a thin film semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2310475A JP3038898B2 (en) | 1990-11-16 | 1990-11-16 | Method for manufacturing thin film semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2310475A JP3038898B2 (en) | 1990-11-16 | 1990-11-16 | Method for manufacturing thin film semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11235804A Division JP3055555B2 (en) | 1999-08-23 | 1999-08-23 | Method for manufacturing thin film semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04181739A JPH04181739A (en) | 1992-06-29 |
| JP3038898B2 true JP3038898B2 (en) | 2000-05-08 |
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ID=18005693
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|---|---|---|---|
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| Country | Link |
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