JP3443909B2 - Semiconductor film forming method, semiconductor device manufacturing method, and semiconductor device - Google Patents

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はアクティブマトリックス
液晶ディスプレイ等に応用される薄膜トランジスタや三
次元ＬＳＩデバイスなどで使用されている絶縁性物質上
に形成される半導体膜の形成方法、或いは薄膜半導体装
置の製造方法に関するもので有り、詳しくは製造工程の
最高温度が６００℃程度以下の低温プロセスで形成する
薄膜半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor film formed on an insulating material used in a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display or a thin film semiconductor device. The present invention relates to a manufacturing method, and more particularly, to a manufacturing method of a thin film semiconductor device formed by a low temperature process in which the maximum temperature of the manufacturing process is about 600 ° C. or less.

【０００２】又、本発明は非酸化性雰囲気下にて行われ
る基板熱処理方法及び化学気相堆積法に関する。The present invention also relates to a substrate heat treatment method and a chemical vapor deposition method performed in a non-oxidizing atmosphere.

【０００３】[0003]

【従来の技術】近年、液晶ディスプレイの大画面化、高
解像度化に伴い、その駆動方式は単純マトリックス方式
からアクティブマトリックス方式へ移行し、大容量の情
報を表示出来るように成りつつ有る。アクティブマトリ
ックス方式は数十万を越える画素を有する液晶ディスプ
レイが可能で有り、各画素毎にスイッチングトランジス
タを形成するもので有る。各種液晶ディスプレイの基板
としては、透過型ディスプレイを可能ならしめる溶融石
英板やガラスなどの透明絶縁基板が使用されている。2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays, the drive system is shifting from the simple matrix system to the active matrix system, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused silica plate or glass that enables a transmissive display is used.

【０００４】しかしながら、表示画面の拡大化や低価格
化を進める場合には絶縁基板として安価な通常ガラスを
使用するのが必要不可欠で有る。従って、この経済性を
維持して尚、アクティブマトリックス方式の液晶ディス
プレイを動作させる薄膜トランジスタを安価なガラス基
板上に安定した性能で容易に形成する事が可能な技術が
望まれていた。However, in order to expand the display screen and reduce the price, it is essential to use inexpensive ordinary glass as an insulating substrate. Therefore, there is a demand for a technique capable of easily forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining the economical efficiency.

【０００５】薄膜トランジスタのチャンネル部半導体膜
としては、通常非晶質シリコンや多結晶シリコンが用い
られているが、駆動回路迄一体化して薄膜トランジスタ
で形成しようとする場合には動作速度の速い多結晶シリ
コンが有利である。Amorphous silicon or polycrystalline silicon is usually used as a channel semiconductor film of a thin film transistor. However, when a driving circuit is integrated into a thin film transistor, the operating speed of polycrystalline silicon is high. Is advantageous.

【０００６】従来この様な薄膜トランジスタやそれらに
用いられる半導体膜を安価なガラスを基板として使用し
得る低温プロセスで作成する場合、非晶質半導体膜形成
後窒素雰囲気下にて６００℃で８時間から２４時間程度
以上の時間熱処理を施していた。（Ｊｐｎ．Ｊ．Ａｐｐ
ｌ．Ｐｈｙｓ．３０，Ｐ３７２４，１９９１やＩＥＥＥ
Ｅｌｅｃｔｒｏｎ Ｄｅｖ．Ｌｅｔｔ．１２，Ｐ５８
４，１９９１， Ｊ．Ｅｌｅｃｔｒｏｃｈｅｍ．Ｓｏ
ｃ．１３６，Ｐ１１６９，１９８９など。）或いは半導
体膜形成後レ−ザ−照射を施していた。（Ｅｘｔ．Ａｂ
ｓ．ＳｏｌｉｄＳｔａｔｅ Ｄｅｖｉｃｅｓ ａｎｄ
Ｍａｔｅｒｉａｌｓ １９９１ Ｐ．６３８やＪａｐ．
Ｊ．Ａｐｐｌ．Ｐｈｙｓ．３０，３７００（１９９１）
など。）又、従来非酸化性雰囲気下にて基板を熱処理し
たり、或いは化学気相堆積する際は基板挿入の為にロー
ドロック室を設けて炉内に混入する空気等の不純物気体
量を少なくしていた。Conventionally, when such thin film transistors and semiconductor films used for them are formed by a low-temperature process in which inexpensive glass can be used as a substrate, after forming an amorphous semiconductor film, it is performed at 600 ° C. for 8 hours in a nitrogen atmosphere. The heat treatment was performed for about 24 hours or more. (Jpn. J. App
l. Phys. 30 , P3724, 1991 and IEEE
Electron Dev. Lett. 12 , P58
4, 1991, J. Electrochem. So
c. 136 , P1169, 1989 and the like. Alternatively, laser irradiation was performed after the semiconductor film was formed. (Ext. Ab
s. SolidState Devices and
Materials 1991 P.M. 638 and Jap.
J. Appl. Phys. 30 , 3700 (1991)
Such. ) In addition, when heat-treating a substrate in the conventional non-oxidizing atmosphere or when performing chemical vapor deposition, a load lock chamber is provided for inserting the substrate to reduce the amount of impurities such as air mixed in the furnace. Was there.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、先に述
べた従来の方法に於いては、以下の如き問題が指摘され
ている。まずレ−ザ−照射による薄膜半導体装置の作成
に関しては装置が窮めて高価で非実用的で有る事に加
え、レーザーショット毎の変動が大きく、大面積に均一
に薄膜半導体装置を作成し得ない。又基板加熱をし、一
枚一枚レ−ザ−照射する等の生産性の悪さも指摘されて
いる。一方熱処理を施す方法では次の様な問題が指摘さ
れている。即ち、熱処理に依り結晶化された多結晶半導
体膜（以後これを固相成長膜、或いはＳＰＣ膜と略記す
る。）はその結晶粒内部におびただしき数の欠陥が存在
している為、そのままでは半導体膜品質が悪く使用し得
ない。例えばＳＰＣ膜を薄膜トランジスタの能動層半導
体膜として用いる場合、ゲート絶縁膜の形成を電子サイ
クロトロン共鳴プラズマＣＶＤ法（ＥＣＲ−ＰＥＣＶ
Ｄ）法にて作成するか、又は他の方法でゲート絶縁膜を
形成して薄膜トランジスタを完成させた後に水素プラズ
マ照射等の水素化処理を施さねばならなかった。しかる
にＥＣＲ−ＰＥＣＶＤ装置は非常に高価で有る上、定期
的に分解して反応炉内の清掃を行わなければならず、薄
膜トランジスタを用いた液晶ディスプレイやＬＳＩ装置
の製品価格の高騰を招いたり、生産性の低下をもたらし
ていた。又、他の方法でゲート絶縁膜を形成し、最後に
水素化処理を施す製法は工程が煩雑と化し、しかも水素
化処理条件の調整が困難で、数十万個に及ぶ薄膜トラン
ジスタの性能を均一に整えるのが非常に難しいとの問題
が有る。However, in the above-mentioned conventional method, the following problems have been pointed out. First, regarding the production of a thin film semiconductor device by laser irradiation, in addition to the fact that the device is cumbersome, expensive and impractical, the variation between laser shots is large, and it is possible to produce a thin film semiconductor device uniformly over a large area. Absent. It is also pointed out that the productivity is poor such that the substrate is heated and the laser is irradiated one by one. On the other hand, the following problems have been pointed out in the heat treatment method. That is, since a polycrystalline semiconductor film crystallized by heat treatment (hereinafter abbreviated as a solid phase growth film or SPC film) has a large number of defects inside its crystal grains, it remains as it is. Therefore, the quality of the semiconductor film is poor and it cannot be used. For example, when the SPC film is used as an active layer semiconductor film of a thin film transistor, the gate insulating film is formed by electron cyclotron resonance plasma CVD method (ECR-PECV).
D) had to be formed or a gate insulating film was formed by another method to complete a thin film transistor, and then hydrogenation treatment such as hydrogen plasma irradiation had to be performed. However, the ECR-PECVD apparatus is very expensive, and it is necessary to periodically disassemble and clean the inside of the reaction furnace, which may lead to soaring product prices of liquid crystal displays and LSI devices using thin film transistors, and production. It caused a decrease in sex. In addition, the method of forming the gate insulating film by another method and finally performing the hydrogenation process complicates the process, and it is difficult to adjust the hydrogenation condition, and the performance of several hundred thousand thin film transistors is uniform. There is a problem that it is very difficult to arrange.

【０００８】したがってＥＣＲ−ＰＥＣＶＤ装置を使用
せず、しかも水素化処理も施さない簡単な製造方法で高
品質な半導体膜を形成する方法、或いは薄膜半導体装置
を製造する方法が求められていた。更に駆動回路まで一
体化して薄膜トランジスタで形成する場合、高解像度化
に伴う画素数の増加は駆動回路の高速動作を要求してい
る。或いは液晶ディスプレイの消費電力を下げたり、液
晶ディスプレイの外部回路等を廉価な汎用ＩＣで構成す
る為に、駆動回路の電源電圧を下げる事が求められてい
る。これらの課題はより低い電圧でより高いオン電流を
有する薄膜トランジスタに依り解決される。即ち、従来
よりも少しでも優れた薄膜トランジスタが常に求められ
ている訳である。Therefore, there has been a demand for a method of forming a high-quality semiconductor film or a method of manufacturing a thin film semiconductor device by a simple manufacturing method which does not use an ECR-PECVD apparatus and does not carry out hydrogenation treatment. Further, when the driving circuit is integrally formed with a thin film transistor, the increase in the number of pixels accompanying the higher resolution requires a high-speed operation of the driving circuit. Alternatively, in order to reduce the power consumption of the liquid crystal display and to configure the external circuit of the liquid crystal display with an inexpensive general-purpose IC, it is required to lower the power supply voltage of the drive circuit. These problems are solved by a thin film transistor having a higher on-current at a lower voltage. That is, there is always a demand for a thin film transistor that is even better than before.

【０００９】本発明は上記の事情に鑑みてなされた物で
その目的とするところは、結晶性半導体膜の形成、及び
良好な特性を有する薄膜半導体装置を大面積に均一にし
かも簡便に製造する方法を提供する事にある。或いは本
発明はオン状態の電圧が同じ場合により高いオン電流を
有する薄膜半導体装置を大面積に均一に製造する方法を
提供する事にある。The present invention has been made in view of the above circumstances, and it is an object of the present invention to form a crystalline semiconductor film and to uniformly and easily manufacture a thin film semiconductor device having good characteristics in a large area. To provide a way. Alternatively, the present invention provides a method for uniformly manufacturing a large area thin film semiconductor device having a higher on-current when the on-state voltage is the same.

【００１０】又、従来は熱処理炉や反応炉にロードロッ
ク室を設けて真空引きを行った後基板挿入していた為、
熱処理炉や反応炉が大きくなったり価格高騰する上、１
バッチごと真空引きするとの煩雑な工程を要していた。Further, conventionally, since the load lock chamber is provided in the heat treatment furnace or the reaction furnace and the substrate is inserted after vacuuming is performed,
Larger heat treatment furnaces and reactors and higher prices, 1
A complicated process of vacuuming each batch was required.

【００１１】本発明は上記の事情に鑑みてなされた物で
その目的とするところは、不純物気体の混入が無く簡単
な熱処理方法や化学気相堆積方法を提供する事に有る。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a simple heat treatment method or chemical vapor deposition method in which an impurity gas is not mixed.

【００１２】[0012]

【課題を解決するための手段】本発明の第１の半導体膜
形成方法は、少なくとも表面が絶縁性物質で有る基板上
に結晶性半導体膜を形成する半導体膜形成方法であっ
て、前記基板上に非晶質半導体膜を形成する第一の工程
と、前記非晶質半導体膜が形成された基板を不活性雰囲
気下にて熱処理し、連続して酸化性雰囲気下において熱
処理することにより、前記非晶質半導体膜を結晶化して
前記結晶性半導体膜とする第二の工程と、を含む事を特
徴とする。A first method for forming a semiconductor film according to the present invention is a method for forming a crystalline semiconductor film on a substrate, at least the surface of which is an insulating material. In the first step of forming an amorphous semiconductor film on the substrate, the substrate on which the amorphous semiconductor film is formed is heat-treated in an inert atmosphere, and continuously heat-treated in an oxidizing atmosphere. A second step of crystallizing the amorphous semiconductor film to obtain the crystalline semiconductor film.

【００１３】本発明の第２の半導体膜形成方法は、少な
くとも表面が絶縁性物質で有る基板上に結晶性半導体膜
を形成する半導体膜形成方法であって、前記絶縁性物質
上に非晶質半導体膜を形成する第一の工程と、前記非晶
質半導体膜が形成された基板を還元性雰囲気下にて熱処
理した後、連続して酸化性雰囲気下において熱処理する
ことにより、前記非晶質半導体膜を結晶化して前記結晶
性半導体膜とする第二の工程と、を含む事を特徴とす
る。A second semiconductor film forming method of the present invention is a semiconductor film forming method of forming a crystalline semiconductor film on a substrate having an insulating material at least on the surface thereof, wherein the crystalline semiconductor film is amorphous on the insulating material. The first step of forming a semiconductor film, the substrate on which the amorphous semiconductor film is formed is heat-treated in a reducing atmosphere, and then continuously heat-treated in an oxidizing atmosphere to form the amorphous film. A second step of crystallizing the semiconductor film to obtain the crystalline semiconductor film.

【００１４】上記の第２の半導体膜形成方法において、
前記還元性雰囲気は水素に依り作り出され、前記還元
性雰囲気における水素分圧は０．１ mtorrから１０気圧
の範囲である事が好ましく、前記酸化性雰囲気は酸素に
依り作り出され、前記酸化性雰囲気における酸素分圧は
０．１気圧から１０気圧の範囲である事が好ましい。In the above second semiconductor film forming method,
The reducing atmosphere is created by hydrogen, the hydrogen partial pressure in the reducing atmosphere is preferably in the range of 0.1 mtorr to 10 atm, and the oxidizing atmosphere is created by oxygen, and the oxidizing atmosphere is The oxygen partial pressure in is preferably in the range of 0.1 atm to 10 atm.

【００１５】上記の半導体膜形成方法において、前記結
晶性半導体膜を構成する元素にシリコンを含んでいる事
が好ましい。In the above semiconductor film forming method, it is preferable that the element forming the crystalline semiconductor film contains silicon.

【００１６】本発明の第３の半導体膜形成方法は、少な
くとも表面が絶縁性物質で有る基板上にシリコン膜を形
成する半導体膜形成方法であって、前記絶縁性物質上に
非晶質シリコン膜を形成する第一の工程と、前記非晶質
シリコン膜が形成された基板を不活性雰囲気下にて熱処
理した後、連続して酸化性雰囲気下にて熱処理する第二
の工程と、を含む事を特徴とする。本発明の第４の半導
体膜形成方法は、少なくとも表面が絶縁性物質で有る基
板上にシリコン膜を形成する半導体膜形成方法であっ
て、前記絶縁性物質上に非晶質シリコン膜を形成する第
一の工程と、前記非晶質シリコン膜が形成された基板を
還元性雰囲気下にて熱処理した後、連続して酸化性雰囲
気下にて熱処理する第二の工程と、を含む事を特徴とす
る。本発明の半導体装置は、上記の半導体膜形成方法を
用いて製造された事を特徴とする。A third semiconductor film forming method of the present invention is a semiconductor film forming method of forming a silicon film on a substrate having at least a surface made of an insulating material, the amorphous silicon film being formed on the insulating material. And a second step in which the substrate on which the amorphous silicon film is formed is heat-treated in an inert atmosphere, and then continuously heat-treated in an oxidizing atmosphere. Characterize things. A fourth semiconductor film forming method of the present invention is a semiconductor film forming method of forming a silicon film on a substrate at least the surface of which is an insulating material, wherein an amorphous silicon film is formed on the insulating material. It is characterized by including a first step and a second step in which the substrate on which the amorphous silicon film is formed is heat-treated in a reducing atmosphere and then continuously heat-treated in an oxidizing atmosphere. And The semiconductor device of the present invention is characterized by being manufactured using the above-described semiconductor film forming method.

【００１７】本発明の第１の半導体装置の製造方法は、
絶縁性物質上に非晶質半導体膜を形成する第一の工程
と、 前記非晶質半導体膜が形成された基板を不活性雰
囲気下にて熱処理した後、連続して酸化性雰囲気下にお
いて熱処理することにより、前記非晶質半導体膜を結晶
化して結晶性半導体膜を形成する第二の工程と、を含む
事を特徴とする。本発明の第２の半導体装置の製造方法
は、絶縁性物質上に非晶質半導体膜を形成する第一の工
程と、 前記非晶質半導体膜が形成された基板を還元性
雰囲気下にて熱処理した後、連続して酸化性雰囲気下に
おいて熱処理することにより、前記非晶質半導体膜を結
晶化して結晶性半導体膜を形成する第二の工程と、を含
む事を特徴とする。The first semiconductor device manufacturing method of the present invention is
A first step of forming an amorphous semiconductor film on an insulating material; and a heat treatment of the substrate on which the amorphous semiconductor film is formed in an inert atmosphere, followed by a heat treatment in an oxidizing atmosphere. By so doing, a second step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film is included. A second method for manufacturing a semiconductor device of the present invention comprises: a first step of forming an amorphous semiconductor film on an insulating material; and a substrate on which the amorphous semiconductor film is formed in a reducing atmosphere. After the heat treatment, a second step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film by continuously performing heat treatment in an oxidizing atmosphere is included.

【００１８】上記の半導体装置の製造方法において、前
記結晶性半導体膜をパターニングする第三の工程をさら
に行うようにしてもよい。上記の半導体装置の製造方法
において、前記結晶性半導体膜を構成する元素にシリコ
ンを含む事が好ましい。In the above method of manufacturing a semiconductor device, a third step of patterning the crystalline semiconductor film may be further performed. In the method for manufacturing a semiconductor device described above, it is preferable that the element forming the crystalline semiconductor film contains silicon.

【００１９】本発明の第３の半導体装置の製造方法は、
絶縁性物質上に非晶質シリコン膜を形成する第一の工程
と、 前記非晶質シリコン膜が形成された基板を不活性
雰囲気下にて熱処理した後、連続して酸化性雰囲気下に
おいて熱処理する第二の工程と、を含む事を特徴とす
る。本発明の第４の半導体装置の製造方法は、絶縁性物
質上に非晶質シリコン膜を形成する第一の工程と、 前
記非晶質シリコン膜が形成された基板を還元性雰囲気下
にて熱処理した後、連続して酸化性雰囲気下において熱
処理する第二の工程と、を含む事を特徴とする。本発明
の第５の半導体装置の製造方法は、絶縁性物質上に非晶
質シリコン膜を堆積する第一の工程と、 前記非晶質シ
リコン膜を島状にパターニング加工した後、酸化膜を堆
積する第二の工程と、続いて酸化性雰囲気下において熱
処理する第三の工程と、を含む事を特徴とする。本発明
の第６の半導体装置の製造方法は、絶縁性物質上に非晶
質シリコン膜を堆積する第一の工程と、前記非晶質シリ
コン膜を島状にパターニング加工した後、窒化膜を堆積
する第二の工程と、前記非晶質シリコン膜と前記窒化膜
の界面に酸素イオンを打ち込む第三の工程と、続いて熱
処理を施す第四の工程と、を含む事を特徴とする。A third method of manufacturing a semiconductor device according to the present invention is
A first step of forming an amorphous silicon film on an insulating material; and a heat treatment of the substrate on which the amorphous silicon film is formed in an inert atmosphere, followed by a continuous heat treatment in an oxidizing atmosphere. And a second step of performing. A fourth method for manufacturing a semiconductor device according to the present invention comprises: a first step of forming an amorphous silicon film on an insulating material; and a substrate on which the amorphous silicon film is formed in a reducing atmosphere. After the heat treatment, a second step of continuously performing heat treatment in an oxidizing atmosphere is included. A fifth method for manufacturing a semiconductor device according to the present invention comprises: a first step of depositing an amorphous silicon film on an insulating material; patterning the amorphous silicon film into island shapes; It is characterized by including a second step of depositing and a third step of subsequently performing heat treatment in an oxidizing atmosphere. A sixth method for manufacturing a semiconductor device according to the present invention comprises: a first step of depositing an amorphous silicon film on an insulating material; patterning the amorphous silicon film into island shapes; The method is characterized by including a second step of depositing, a third step of implanting oxygen ions into the interface between the amorphous silicon film and the nitride film, and a fourth step of subsequently performing heat treatment.

【００２０】本発明の第７の半導体装置の製造方法は、
絶縁性物質上に非晶質半導体膜を堆積する第一の工程
と、 前記非晶質半導体膜を島状にパターニング加工し
た後、酸化膜を堆積する第二の工程と、続いて酸化性雰
囲気下において熱処理することにより前記非晶質半導体
膜を結晶化する第三の工程と、を含む事を特徴とする。
上記の半導体装置の製造方法において、前記半導体膜を
構成する元素にシリコンが含まれており、且つ前記酸化
膜に酸化珪素が含まれている事が好ましい。A seventh semiconductor device manufacturing method of the present invention is
A first step of depositing an amorphous semiconductor film on an insulating material, a second step of patterning the amorphous semiconductor film into islands, and then depositing an oxide film, and subsequently an oxidizing atmosphere And a third step of crystallizing the amorphous semiconductor film by heat treatment below.
In the method for manufacturing a semiconductor device described above, it is preferable that the element forming the semiconductor film contains silicon, and the oxide film contains silicon oxide.

【００２１】本発明の第８の半導体装置の製造方法は、
絶縁性物質上に非晶質半導体膜を堆積する第一の工程
と、 前記非晶質半導体膜を島状にパターニング加工し
た後、酸化膜を堆積する第二の工程と、続いて窒化膜を
堆積する第三の工程と、 前記酸化膜中に酸素イオンを
打ち込む第四の工程と、 続いて熱処理することにより
前記非晶質半導体膜を結晶化する第五の工程と、を含む
事を特徴とする。本発明の第９の半導体装置の製造方法
は、絶縁性物質上に非晶質半導体膜を堆積する第一の工
程と、 前記非晶質半導体膜を島状にパターニング加工
した後、窒化膜を堆積する第二の工程と、 前記非晶質
半導体膜と前記窒化膜の界面に酸素イオンを打ち込む第
三の工程と、続いて熱処理を施すことにより前記非晶質
半導体膜を結晶化する第四の工程と、含む事を特徴とす
る。上記半導体装置の製造方法において、前記半導体膜
を構成する元素にシリコンが含まれており、且つ前記窒
化膜が窒化珪素膜である事が好ましい。An eighth semiconductor device manufacturing method of the present invention comprises:
A first step of depositing an amorphous semiconductor film on an insulating material, a second step of patterning the amorphous semiconductor film into islands, and then depositing an oxide film, and then a nitride film. It is characterized by including a third step of depositing, a fourth step of implanting oxygen ions into the oxide film, and a fifth step of subsequently crystallizing the amorphous semiconductor film by heat treatment. And A ninth method for manufacturing a semiconductor device according to the present invention comprises: a first step of depositing an amorphous semiconductor film on an insulating material; A second step of depositing, a third step of implanting oxygen ions into the interface between the amorphous semiconductor film and the nitride film, and a fourth step of crystallizing the amorphous semiconductor film by performing heat treatment subsequently. The process is characterized by including. In the method of manufacturing a semiconductor device described above, it is preferable that the element forming the semiconductor film contains silicon, and the nitride film is a silicon nitride film.

【００２２】本発明の第１０の半導体装置の製造方法
は、絶縁性物質上に非晶質シリコン膜を堆積する第一の
工程と、前記非晶質シリコン膜を島状にパターニング加
工した後、酸化膜を堆積する第二の工程と、続いて窒化
膜を堆積する第三の工程と、前記酸化膜中に酸素イオン
を打ち込む第四の工程と、続いて熱処理する第五の工程
と、を含む事を特徴とする。According to a tenth method of manufacturing a semiconductor device of the present invention, a first step of depositing an amorphous silicon film on an insulating material, and patterning the amorphous silicon film into islands, A second step of depositing an oxide film, a third step of subsequently depositing a nitride film, a fourth step of implanting oxygen ions into the oxide film, and a fifth step of heat treatment. It is characterized by including.

【００２３】[0023]

【実施例】（実施例１）以下本発明の実施例を詳述する
が、本発明が以下の実施例に限定されるものでは無い。EXAMPLES (Example 1) Examples of the present invention will be described in detail below, but the present invention is not limited to the following examples.

【００２４】図２ａ〜ｄは本実施例１に於ける自己整合
型スタガード構造のＭＩＳ型電界効果トランジスタを構
成するシリコン薄膜半導体装置の製造工程を断面で示し
た図で有る。2A to 2D are cross-sectional views showing the manufacturing process of the silicon thin film semiconductor device which constitutes the MIS field effect transistor having the self-aligned staggered structure according to the first embodiment.

【００２５】本実施例１では、下地基板２０１として２
３５ｍｍ□の溶融石英ガラスを用いたが、６００℃の工
程最高温度に耐え得る基板又は下地物質で有るならば、
その種類や大きさは無論問われない。例えば通常ガラス
基板の他にシリコンウェハーなどの半導体基板及びそれ
らを加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン
・カーバイト、アルミナ、窒化アルミニウムなどのセラ
ミックス基板なども下地基板として可能で有る。In the first embodiment, 2 is used as the base substrate 201.
35mm □ fused silica glass was used, but if it is a substrate or base material that can withstand the maximum process temperature of 600 ° C,
Of course, its kind and size are not questioned. For example, in addition to a glass substrate, a semiconductor substrate such as a silicon wafer, an LSI obtained by processing them, a three-dimensional LSI, or a ceramics substrate such as silicon carbide, alumina, or aluminum nitride can be used as the base substrate.

【００２６】まずアセトン又はメチル・エチル・ケト
ン，メチル・イソ・ブチル・ケトンやシクロヘキサノン
などの有機溶剤中に下地基板２０１を浸し、超音波洗浄
を行う。洗浄後窒素中又は減圧下にて乾燥を施し、更に
エタノールによる超音波洗浄を行った後窒素バブリング
されている純水にて水洗を施す。次に下地基板２０１を
沸騰している濃度６０％の硝酸中に５分間浸し、更に窒
素バブリングされている純水中で洗浄した。基板として
金属など酸に依り腐食されたり、変質して仕舞う物質を
用いる場合、この硝酸に依る洗浄は必要とされない。又
この強酸に依る洗浄では酸として硝酸の他に硫酸なども
可能で有る。First, the base substrate 201 is immersed in an organic solvent such as acetone or methyl-ethyl-ketone, methyl-iso-butyl-ketone or cyclohexanone, and ultrasonic cleaning is performed. After cleaning, the product is dried in nitrogen or under reduced pressure, further ultrasonically cleaned with ethanol, and then rinsed with pure water with nitrogen bubbling. Next, the base substrate 201 was immersed in boiling nitric acid having a concentration of 60% for 5 minutes, and further washed in pure water with nitrogen bubbling. When a substance such as a metal that is corroded by acid or deteriorates and is used as a substrate is used, the cleaning by nitric acid is not required. In addition, in washing with this strong acid, sulfuric acid as well as nitric acid can be used as the acid.

【００２７】こうして洗浄された石英基板上に常圧気相
化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化
硅素膜（ＳｉＯ₂膜）２０２を２０００Å堆積した。こ
の下地ＳｉＯ₂膜２０２は前述の如き種々多様な物質を
基板として用いる際、後に堆積される半導体膜の膜質、
及びそれを用いて構成される薄膜トランジスタの性能を
安定化する為に必要で有る。と同時に、例えば基板２０
１として通常ガラスを用いた場合、ガラス中に含まれて
いるナトリウムなどの可動イオンが、又基板２０１とし
て各種セラミック板を用いた際には基板中に添加されて
いる焼結助材原料などがトランジスタ部に拡散混入する
のを防ぐ役割をも演じている。又金属板を基板２０１と
して用いる場合は、絶縁性を確保する為に下地ＳｉＯ₂
は必要不可欠で有る。又、三次元ＬＳＩ素子では、トラ
ンジスタ間や配線間の層間絶縁膜に相当している。下地
ＳｉＯ₂膜２０２堆積時の基板温度は３００℃で、窒素
に依り２０％に希釈されたシラン６００SCCMを８４０SC
CMの酸素と共にＡＰＣＶＤ法で堆積した。この時のＳｉ
Ｏ₂膜の堆積速度は３．９Å／ｓｅｃで有った。2000 Å of silicon dioxide film (SiO ₂ film) 202 to be a base protection film was deposited on the thus cleaned quartz substrate by atmospheric pressure chemical vapor deposition (APCVD method). This underlying SiO ₂ film 202 is a film quality of a semiconductor film to be deposited later when various substances as described above are used as a substrate,
Also, it is necessary to stabilize the performance of the thin film transistor configured using the same. At the same time, for example, the substrate 20
When ordinary glass is used as 1, the mobile ions such as sodium contained in the glass are used, and when various ceramic plates are used as the substrate 201, the sintering aid raw material added to the substrate is It also plays a role in preventing diffusion and mixing in the transistor section. When a metal plate is used as the substrate 201, the underlying SiO ₂ film is used to ensure insulation.
Is indispensable. Also, in a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors and between wirings. The substrate temperature at the time of depositing the underlying SiO ₂ film 202 is 300 ° C., and silane 600 SCCM diluted to 20% with nitrogen is 840 SC.
It was deposited by the APCVD method together with CM oxygen. Si at this time
The deposition rate of the O ₂ film was 3.9 Å / sec.

【００２８】次に減圧ＣＶＤ法でいずれ能動層となる非
晶質半導体膜を堆積した。本実施例１では半導体膜とし
てシリコンを用いたが、シリコン・ゲルマニウムやガリ
ウム・ヒ素、シリコン・カーバイト、ダイヤモンド等他
の半導体も可能で有る。Next, an amorphous semiconductor film which will eventually become an active layer is deposited by the low pressure CVD method. Although silicon is used as the semiconductor film in the first embodiment, other semiconductors such as silicon-germanium, gallium-arsenic, silicon-carbite, and diamond are also possible.

【００２９】半導体膜堆積に用いた減圧ＣＶＤ反応炉の
容積は１８４．５ｌで、基板は反応炉中央付近に水平に
置かれる。原料ガス及びヘリウム・窒素・アルゴン・水
素等の希釈ガスは必要に応じて反応炉下部より炉内に導
入され、反応炉上部から排気される。石英ガラスで作ら
れた反応炉の外側には３ゾーンに分かれたヒーターが設
置されて居り、それらを独立に調整する事で反応炉内中
央部付近に所望の温度で均熱帯を形成する。この均熱帯
は約３５０ｍｍの高さで広がり、その範囲内での温度の
ずれは、例えば６００℃に設定した時０．２℃以内であ
る。従って挿入基板間の間隔を１０ｍｍとすれば１バッ
チで３５枚の基板の処理が可能で有る。本実施例１では
２０ｍｍ間隔で１７枚の基板を均熱帯内に設置した。The volume of the low pressure CVD reactor used for semiconductor film deposition is 184.5 l, and the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, hydrogen, etc. are introduced into the furnace from the lower part of the reaction furnace and exhausted from the upper part of the reaction furnace as needed. Outside the reactor made of quartz glass, there are heaters divided into three zones, and by adjusting them independently, a soaking zone is formed near the center of the reactor at a desired temperature. This soaking zone spreads at a height of about 350 mm, and the temperature shift within that range is within 0.2 ° C. when set at 600 ° C., for example. Therefore, if the distance between the inserted substrates is 10 mm, it is possible to process 35 substrates in one batch. In Example 1, 17 substrates were installed in the soaking zone at intervals of 20 mm.

【００３０】排気はロータリーポンプとメカニカル・ブ
ースターポンプを直結して行い、反応炉内の圧力は測定
値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バ
ラトロン・マノメーター）に依り測定した。反応炉を５
５０℃に保って、ガス導入用のバルブを閉じて両ポンプ
にて真空引きを行った場合、反応炉内圧は０mtorrで有
る為、背景真空度は悪くとも１０^-4torr程度以下で有
る。Exhaust was carried out by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reaction furnace was measured by a diaphragm pressure gauge (MKS Co., Baratron Manometer) whose measured value did not depend on the type of gas. 5 reactors
When the temperature is kept at 50 ° C., the gas introduction valve is closed, and both pumps are evacuated, the internal pressure of the reaction furnace is 0 mtorr, and therefore the background vacuum degree is at most 10 ⁻⁴ torr or less.

【００３１】半導体膜を堆積すべき基板は、表側を下向
きとして減圧ＣＶＤ炉内に挿入された。挿入時の反応炉
内温度は３９５℃から４００℃程度で有った。基板挿入
時に反応炉内には上部より純度が９９・９９９９％以上
のヘリウムと水素の混合気体が３０ＳＬＭ導入され、こ
れらの混合気体は反応炉下部に設けられた基板挿入口よ
り排出されて居る。基板挿入口の直径は５４０ｍｍでそ
の断面積は２２９０ｃｍ²で有る。混合気体が４００℃
に熱せられていると、基板挿入口からの混合気体の排出
速度は２９．６ｃｍ／ｍｉｎとなる。又、本実施例１の
如く２３５ｍｍ□の基板を水平に設置する場合、基板面
積は５５２ｃｍ²で有るから基板が基板挿入口より反応
炉内に入っていく時に基板挿入口と基板の隙間から排出
される混合気体の排出速度は３９．０ｃｍ／ｍｉｎで有
る。本実施例１では１０ｃｍ／ｍｉｎの上昇速度で基板
を反応炉に挿入したが、混合気体の排出速度の方が速い
為、基板挿入に伴う空気等の反応室への混入を防ぐ事が
出来る。又、混合気体の密度は空気密度よりも小さく、
しかも熱せられているので重い空気がこれらの軽い気体
を押し退けて下から上へ入る可能性は殆ど無い。本実施
例１で反応炉上部より導入した混合気体の濃度はヘリウ
ム９７％に水素３％で有った。水素の爆発下限界は４．
０％なので、これ以下の濃度で有れば基板挿入口より室
内に排出されても安全で有る。こうした基板挿入方法を
用いる事に依り、ロードロック室を用いて１バッチ毎に
真空引きを行うといった煩雑な過程を経る事無くして、
反応炉内を清浄な非酸化性雰囲気下に保てられるので有
る。基板挿入時に空気や水等の不純物気体が反応炉内に
流れ込むと、これらは反応炉内壁の半導体層に吸着し、
又は半導体元素と反応して反応炉内に残留し、半導体膜
堆積の際脱ガスとして現れ、堆積膜の膜品質を低下させ
る原因となる。従って本発明の基板挿入を用いたＣＶＤ
方法では容易に高品質半導体膜が堆積されるので有る。The substrate on which the semiconductor film was to be deposited was inserted into a low pressure CVD furnace with the front side facing downward. The temperature inside the reaction furnace at the time of insertion was about 395 ° C to 400 ° C. When the substrate was inserted, 30 SLM of a mixed gas of helium and hydrogen having a purity of 99.9999% or more was introduced into the reaction furnace from above, and the mixed gas was discharged from the substrate insertion port provided in the lower part of the reaction furnace. The diameter of the substrate insertion port is 540 mm and its cross-sectional area is 2290 cm ² . Mixed gas is 400 ° C
When heated to, the discharge rate of the mixed gas from the substrate insertion port becomes 29.6 cm / min. When a 235 mm square substrate is installed horizontally as in the first embodiment, since the substrate area is 552 cm ² , the substrate is discharged from the gap between the substrate insertion port and the substrate when entering the reaction furnace from the substrate insertion port. The discharge rate of the mixed gas is 39.0 cm / min. In Example 1, the substrate was inserted into the reaction furnace at a rising rate of 10 cm / min. However, since the mixed gas is discharged at a higher rate, it is possible to prevent air and the like from entering the reaction chamber when the substrate is inserted. Also, the density of the mixed gas is smaller than the air density,
Moreover, since it is heated, there is little possibility that heavy air will push these light gases away and enter from the bottom to the top. The concentration of the mixed gas introduced from the upper portion of the reaction furnace in Example 1 was 97% helium and 3% hydrogen. The lower limit of hydrogen explosion is 4.
Since it is 0%, if the concentration is less than this, it is safe to be discharged into the room from the substrate insertion port. By using such a board insertion method, it is possible to perform a vacuum process for each batch by using a load lock chamber without a complicated process.
The inside of the reaction furnace can be kept in a clean non-oxidizing atmosphere. When impurity gas such as air or water flows into the reaction furnace when inserting the substrate, these are adsorbed to the semiconductor layer on the inner wall of the reaction furnace,
Alternatively, it reacts with the semiconductor element and remains in the reaction furnace, and appears as degas when the semiconductor film is deposited, which causes deterioration of the film quality of the deposited film. Accordingly, CVD using the substrate insert of the present invention
This is because the method easily deposits a high quality semiconductor film.

【００３２】基板挿入後、真空引き、漏洩検査を施し
た。漏洩検査では反応炉に通ずる全バルブを閉じて反応
炉を完全に孤立させて、反応炉内圧力の変化を調べた。
本実施例１では反応炉内温度が４００℃で２分間の完全
孤立後、反応炉内圧力は１mtorr以下で有った。漏洩検
査にて異常が無い事を確認した後、反応炉内温度を挿入
温度の４００℃から堆積温度まで昇温する。本実施例１
では５５０℃でチャンネル部となる半導体膜を堆積した
為、昇温するのに一時間費やした。炉内温度が堆積温度
の５５０℃に達するには３５分間程度で済むが、反応炉
壁からの脱ガスを充分放出する為にも、最短一時間以
上、好ましくは二時間から三時間程度の昇温期間が望ま
しい。この昇温期間中、二つのポンプは運転状態に有
り、少なくとも純度が９９．９９５％以上の不活性又は
還元性ガスを流し続ける。これらのガス種は水素・ヘリ
ウム・窒素・ネオン・アルゴン・キセノン・クリプトン
等の純ガスの他、これらのガスの混合ガスも可能で有
る。本実施例１では純度９９．９９９９％以上のヘリウ
ムを３５０SCCM流し続け、反応炉内圧力は８１±１．２
mtorrで有った。After the substrate was inserted, a vacuum was drawn and a leak test was conducted. In the leak test, all the valves leading to the reactor were closed to completely isolate the reactor, and the change in pressure inside the reactor was examined.
In this Example 1, the temperature inside the reaction furnace was 1 mtorr or less after completely isolating at 400 ° C. for 2 minutes. After confirming that there is no abnormality in the leakage inspection, the temperature inside the reaction furnace is raised from the insertion temperature of 400 ° C. to the deposition temperature. Example 1
Since the semiconductor film to be the channel portion was deposited at 550 ° C., it took 1 hour to raise the temperature. It takes about 35 minutes for the temperature in the furnace to reach the deposition temperature of 550 ° C, but in order to sufficiently release the degas from the reaction furnace wall, it is necessary to raise the temperature for at least 1 hour or more, preferably about 2 to 3 hours. A warm period is desirable. During this temperature rising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995%. These gas species can be pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton, and also mixed gases of these gases. In Example 1, helium having a purity of 99.9999% or more was continuously flowed at 350 SCCM, and the pressure in the reaction furnace was 81 ± 1.2.
It was mtorr.

【００３３】堆積温度到達後、原料ガスで有る所定量の
シラン又はシランと希釈ガスの混合ガスを反応炉内に導
入し、非晶質半導体膜を堆積する。希釈ガスとしては、
先の昇温期間に流したガスと同種の組み合わせが可能で
有るが、望ましくは各ガスの純度はそれぞれが９９．９
９９％以上が良い。本実施例１では希釈ガスを用いず、
純度９９．９９９％以上のシランを１００SCCM流して非
晶質半導体膜を堆積した。堆積時に於ける反応炉内の圧
力は反応炉とメカニカル・ブースターポンプの間に設置
されたコンダクタンスバルヴの開閉度を調整して４００
mtorrに保った。本実施例１では非晶質半導体膜は２２
Å／ｍｉｎの堆積速度で２５０Åの膜厚に堆積した。After reaching the deposition temperature, a predetermined amount of silane, which is a source gas, or a mixed gas of silane and a diluent gas is introduced into the reaction furnace to deposit an amorphous semiconductor film. As a diluent gas,
It is possible to use the same kind of combination as the gas that was made to flow in the previous heating period, but it is desirable that the purity of each gas is 99.9.
99% or more is good. In Example 1, no diluent gas was used,
Amorphous semiconductor film was deposited by flowing 100 SCCM of silane having a purity of 99.999% or more. The pressure inside the reactor during deposition was adjusted to 400 by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump.
kept on mtorr. In Example 1, the amorphous semiconductor film is 22
It was deposited to a film thickness of 250 Å at a deposition rate of Å / min.

【００３４】本実施例１では非晶質半導体膜の堆積をＬ
ＰＣＶＤ法で行い、原料ガスもモノシランを用いたが、
これ以外にもプラズマＣＶＤ法や光ＣＶＤ法、ＡＰＣＶ
Ｄ等の各種ＣＶＤ法やスパッター法、蒸着法等各種ＰＶ
Ｄ法等で堆積する事も可能で有る。又原料ガスもモノシ
ランに限らず、ジシランやトリシランなどの高次シラン
やジクロールシラン或いはゲルマンやメタンなども可能
で有る。又、無論上記種々のＣＶＤ法と上記種々の原料
の組み合わせに依って非晶質半導体膜を堆積する事も可
能で有る。In Example 1, the deposition of the amorphous semiconductor film was performed by L
Although the PCVD method was used and monosilane was used as the source gas,
Other than this, plasma CVD method, optical CVD method, APCV
Various PV such as various CVD methods such as D, sputtering method, vapor deposition method, etc.
It is also possible to deposit by the D method or the like. Further, the source gas is not limited to monosilane, but higher order silanes such as disilane and trisilane, dichlorsilane, germane, methane, etc. are also possible. Of course, it is also possible to deposit an amorphous semiconductor film by combining the various CVD methods described above and the various raw materials described above.

【００３５】次にこうして得られた基板を１．６７％弗
化水素酸水溶液に２０秒間浸して非晶質半導体膜表面か
ら自然酸化膜を取り除いた。その後基板は直ちに弱酸化
性雰囲気下に設置され、熱処理を施された。Next, the substrate thus obtained was immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film from the surface of the amorphous semiconductor film. After that, the substrate was immediately placed in a weakly oxidizing atmosphere and subjected to heat treatment.

【００３６】熱処理炉は縦型炉で通常４００℃に保たれ
て居り、純度９９．９９９％以上の窒素を３０SLMと純
度９９．９９９％以上の酸素を３００SCCM流し続けて熱
処理炉内部を弱酸化性雰囲気としている。従って熱処理
炉内の酸素分圧はおよそ０．０１気圧となる。熱処理炉
の容積は１８４．５ｌで有る。基板は縦型炉下部より熱
処理炉内に挿入されるが、窒素と酸素は熱処理炉上部よ
り炉内に導入され下部の挿入口より流出している。室温
と温度平衡に達している基板は弱酸化性雰囲気で４００
℃の炉に挿入された。基板挿入後熱処理炉の温度を一時
間かけて６００℃まで上げ、その後６００℃にて１５時
間維持した。この熱処理に依り非晶質半導体膜は結晶化
して多結晶半導体膜へと固体状態を変える。非晶質膜を
構成していた半導体元素が多結晶状態へと移動すると原
子密度の減少及び空間移動に関する自由度の低さに起因
して、出来上がった多結晶粒内部には必然的におびただ
しき数の欠陥や不対電子が発生する。ところが本発明が
示す所に依ると、この様な欠陥及び不対電子は酸素と結
合して、終端されるので有る。熱処理時の酸素分圧が高
過ぎると、欠陥等を終端すべき酸素原子が半導体膜内部
に迄取り込まれて半導体膜品質を劣化させてしまう。同
時に非晶質から多結晶へと半導体膜が状態変化を起こす
前に非晶質表面に数十Å程度の酸化膜が形成されてしま
い、結晶成長が行われて欠陥や不対電子が沢山生じた後
では、表面酸化膜の存在に依り欠陥終端する酸素が十分
供給されないので有る。反対に熱処理時の酸素分圧が低
過ぎるとやはり欠陥終端すべき酸素数が不足し、効果は
十分現れない。弱酸化性雰囲気を酸素に依り作り出す場
合、酸素分圧は５mtorrから５０torr程度が好ましい。
最適酸素分圧は熱処理温度や時間に依っても変化する
が、５００℃〜７００℃の処理温度で１００時間以内の
処理時間に対しては１０mtorrから１０torr程度がより
好ましく、更に好ましくは２０mtorrから５torr程度で
ある。最適分圧は半導体膜材質に依っても決定される。
シリコン・ゲルマニウムの様にシリコンに比べて酸化が
速い半導体膜材料では最適酸素分圧範囲は低圧側にシフ
トされる。例えば純粋なゲルマニウム膜では酸素分圧は
０．５mtorrから５torr程度が好ましく、より好ましく
は１mtorrから1torr、更に好ましくは２mtorrから５０
０mtorr程度である。この最適酸素分圧はシリコン・ゲ
ルマニウム（Ｓｉ_xＧｅ_1-x）中のシリコン原子の割合
（ｘ値）比例して定まる。例えばＳｉ_0.5Ｇｅ_0.5（ｘ＝
０．５）に対しては酸素分圧は２．７５mtorrから２
７．５torr程度が好ましく、より好ましくは５．５mtor
rから５．５torr、更に好ましくは１１mtorrから２．７
５torr程度となる。又、笑気ガス（Ｎ₂Ｏ）や水（Ｈ
₂Ｏ）二酸化炭素（ＣＯ₂）を用いる場合は反応が速いの
で、それらの気体分圧は酸素分圧の値の１／５程度とな
る。例えば、シリコンに対する酸素分圧が５mtorrから
５０torrの範囲に相当するそれらの気体分圧はおよそ１
mtorrから１０torr程度が好ましい。熱処理温度は５０
０℃から７００℃程度の間が使用される。結晶成長をゆ
っくり大きくさせるとの観点からは低温の方が好ましい
が、結晶化に長時間費やす。本実施例１の様に６００℃
にて熱処理を施す場合は１０時間で結晶化はほぼ完了す
るが、５５０℃とすると熱処理時間は１００時間以上と
なり、又７００℃とすると１時間程度で済む。熱処理温
度はこうした長短より決められるが、好ましくは５３０
℃程度から６７０℃程度、更に好ましくは５５０℃から
６５０℃程度、より好ましくは５７０℃程度から６３０
℃程度で有る。The heat treatment furnace is a vertical furnace which is normally kept at 400 ° C., and nitrogen in the purity of 99.999% or more is flowed at 30 SLM and oxygen in the purity of 99.999% or more at 300 SCCM is continuously supplied to weakly oxidize the inside of the heat treatment furnace. It has an atmosphere. Therefore, the oxygen partial pressure in the heat treatment furnace is about 0.01 atm. The volume of the heat treatment furnace is 184.5 l. The substrate is inserted into the heat treatment furnace from the lower part of the vertical furnace, but nitrogen and oxygen are introduced into the furnace from the upper part of the heat treatment furnace and flow out from the lower insertion port. Substrate that has reached temperature equilibrium with room temperature is 400 times in a weak oxidizing atmosphere.
It was inserted into the furnace at ℃. After inserting the substrate, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained at 600 ° C. for 15 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change its solid state into a polycrystalline semiconductor film. When the semiconductor element that made up the amorphous film moves to the polycrystalline state, it is inevitable that the inside of the finished polycrystalline grain will be affected by the decrease in atomic density and the low degree of freedom in space movement. Frequency defects and unpaired electrons are generated. However, according to the present invention, such defects and unpaired electrons are bound with oxygen and terminated. If the oxygen partial pressure at the time of heat treatment is too high, oxygen atoms for terminating defects and the like are taken into the inside of the semiconductor film, deteriorating the quality of the semiconductor film. At the same time, an oxide film of several tens of liters is formed on the amorphous surface before the semiconductor film changes its state from amorphous to polycrystalline, which causes crystal growth and many defects and unpaired electrons. After that, due to the presence of the surface oxide film, oxygen terminating the defects is not sufficiently supplied. On the other hand, if the oxygen partial pressure during the heat treatment is too low, the number of oxygen for terminating the defects is also insufficient and the effect is not sufficiently exhibited. When a weakly oxidizing atmosphere is created by oxygen, the oxygen partial pressure is preferably about 5 mtorr to 50 torr.
The optimum oxygen partial pressure varies depending on the heat treatment temperature and time, but it is more preferably about 10 mtorr to 10 torr, and more preferably 20 mtorr to 5 torr for a treatment time of 100 hours or less at a treatment temperature of 500 ° C to 700 ° C. It is a degree. The optimum partial pressure is also determined depending on the material of the semiconductor film.
The optimum oxygen partial pressure range is shifted to the low pressure side in a semiconductor film material such as silicon / germanium, which is oxidized faster than silicon. For example, in a pure germanium film, the oxygen partial pressure is preferably about 0.5 mtorr to 5 torr, more preferably 1 mtorr to 1 torr, still more preferably 2 mtorr to 50 torr.
It is about 0 mtorr. The optimum oxygen partial pressure ratio (x value) of silicon atoms in the silicon in germanium (Si _x Ge _1-x) determined in proportion. For example Si _0.5 Ge _0.5 (x =
For 0.5), the oxygen partial pressure is 2.75 mtorr to 2
It is preferably about 7.5 torr, more preferably 5.5 mtor.
r to 5.5 torr, more preferably 11 mtorr to 2.7
It will be about 5 torr. Also, laughing gas (N ₂ O) and water (H
₂ O) When carbon dioxide (CO ₂ ) is used, the reaction is fast, so the partial pressure of these gases is about ⅕ of the partial pressure of oxygen. For example, those gas partial pressures corresponding to the oxygen partial pressure for silicon ranging from 5 mtorr to 50 torr are about 1.
About mtorr to 10 torr is preferable. Heat treatment temperature is 50
A temperature between 0 ° C. and 700 ° C. is used. From the viewpoint of slowly increasing the crystal growth, a low temperature is preferable, but it takes a long time for crystallization. 600 ° C as in Example 1
When the heat treatment is performed at 10 ° C., crystallization is almost completed in 10 hours, but the heat treatment time is 100 hours or more at 550 ° C., and about 1 hour at 700 ° C. The heat treatment temperature is determined depending on the length, but is preferably 530
C. to 670.degree. C., further preferably 550.degree. C. to 650.degree. C., more preferably 570.degree. C. to 630.
It is about ℃.

【００３７】こうして得られた半導体膜は、レジストで
パターニングされた後、四弗化炭素（ＣＦ₄）と酸素
（Ｏ₂）の混合プラズマに依りエッチングされ、能動層
半導体膜２０３を形成した（図２ａ）。本実施例１で形
成した半導体膜はＣＦ₄とＯ₂の比が５０SCCM対１００SC
CMで有る１５Ｐａの真空プラズマ放電で、その出力が７
００Ｗの時のエッチングでは２．０Å／ｓｅｃのエッチ
ング速度を有していた。The semiconductor film thus obtained is patterned with a resist and then etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form an active layer semiconductor film 203 (see FIG. 2a). The semiconductor film formed in Example 1 has a CF ₄ to O ₂ ratio of 50 SCCM to 100 SC.
The output is 7 by the vacuum plasma discharge of 15Pa which is CM.
The etching rate at 00 W had an etching rate of 2.0 Å / sec.

【００３８】次にこの基板を沸騰している濃度６０％の
硝酸にて洗浄しＡＰＣＶＤ法にてゲート絶縁膜となるＳ
ｉＯ₂膜２０４を１５００Å堆積した（図２ｂ）。ＡＰ
ＣＶＤ法にてゲート絶縁膜を堆積する時の基板温度は３
００℃で、窒素に依り２０％に希釈されたシラン３００
SCCMと３００SCCMの酸素を流してＳｉＯ₂膜を堆積し
た。本実施例１ではＡＰＣＶＤ法を用いたが、これ以外
にもプラズマＣＶＤ法、光ＣＶＤ法、ＬＰＣＶＤ法等の
各種ＣＶＤ法やスパッタ法等のＰＶＤ法も有効で有る。
又、原材料もシランに限らずＴＥＯＳ｛Ｓｉ−（ＣＨ₃
−ＣＨ₂−Ｏ−）₄｝等の有機シリコン化合物も利用し得
る。無論ＥＣＲ−ＰＥＣＶＤ法を用いても良い。Next, this substrate is washed with boiling nitric acid having a concentration of 60%, and S which becomes a gate insulating film is formed by the APCVD method.
An iO ₂ film 204 was deposited 1500 Å (Fig. 2b). AP
The substrate temperature is 3 when the gate insulating film is deposited by the CVD method.
Silane 300 diluted to 20% with nitrogen at 00 ° C
A SiO ₂ film was deposited by flowing oxygen of SCCM and 300 SCCM. Although the APCVD method is used in the first embodiment, other than this, various CVD methods such as the plasma CVD method, the photo CVD method, the LPCVD method and the PVD method such as the sputtering method are also effective.
The raw material is not limited to silane, but TEOS {Si- (CH ₃
Organosilicon compounds such as —CH ₂ —O—) ₄ } can also be used. Of course, the ECR-PECVD method may be used.

【００３９】次にタンタルをスパッター法で堆積し、パ
ターニングに依り、ゲート電極２０５を形成した。本実
施例１ではゲート電極材料としてタンタルを用いたが、
無論これ以外の導電性物質も可能で有るし、又その形成
方法もスパッター法に限らず蒸着法やＣＶＤ法なども可
能で有る。ゲート電極作成後、ゲート電極をマスクとし
てドナー又はアクセプターとなる元素をイオン注入２０
６し、ソース・ドレイン領域２０７及びチャンネル領域
２０８を作成した（図２Ｃ）。本実施例１ではＮＭＯＳ
トランジスタ作成を目指し、水素希釈された５％フォス
フィンを質量非分離型イオン注入装置にて打ち込んだ。
加速電圧は１１０ｋｖで水素原子を含む総イオン打ち込
み量は１．０×１０¹⁶ｃｍ^-2で有った。続いてＡＰＣＶ
Ｄ法で層間絶縁膜２０９となるＳｉＯ₂膜を５０００Å
堆積した。この堆積は本実施例１で下地ＳｉＯ₂膜２０
２を堆積した条件と全く同一で唯一堆積時間のみを変え
て行った。層間絶縁膜形成後、注入イオンの活性化と層
間絶縁膜の焼き締めを兼ねて、窒素中で３００℃１時間
の熱処理を施した。熱処理後のソース・ドレイン領域の
シート抵抗値は９５％の信頼係数で（９３±２２）ｋΩ
／□で有った。本実施例１ではイオン注入を質量非分離
型イオン注入装置で行い、３００℃の低温熱処理に依り
注入イオンの活性化を行ったが、これに限らず例えば通
常の質量分離型イオン注入装置にてイオン注入し、レー
ザー照射に依り活性化しても良い。その後コンタクトホ
ールを開け、ソース・ドレイン取り出し電極２１０をス
パッター法などで形成し、トランジスタが完成する（図
２ｄ）。本実施例１ではソース・ドレイン取り出し電極
材料としてアルミニウムを用いスパッター法で８０００
Åの膜厚に堆積して、ソース・ドレイン取り出し電極を
形成した。この時堆積アルミニウム膜のシート抵抗は４
２．５±２．０ｍΩ／□で有った。Next, tantalum was deposited by the sputtering method, and the gate electrode 205 was formed by patterning. In Example 1, tantalum was used as the gate electrode material,
Of course, other conductive materials are also possible, and the forming method is not limited to the sputtering method, and the vapor deposition method or the CVD method is also possible. After the gate electrode is formed, an element serving as a donor or an acceptor is ion-implanted using the gate electrode as a mask.
Then, the source / drain region 207 and the channel region 208 were formed (FIG. 2C). In the first embodiment, the NMOS
5% phosphine diluted with hydrogen was implanted with a mass non-separation type ion implanter for the purpose of forming a transistor.
The acceleration voltage was 110 kv, and the total ion implantation amount including hydrogen atoms was 1.0 × 10 ¹⁶ cm ^-2 . Then APCV
The SiO ₂ film to be the interlayer insulating film 209 is formed by the D method at 5000 Å
Deposited. This deposition is the base SiO ₂ film 20 in the first embodiment.
The same conditions as those for depositing No. 2 were used, and only the deposition time was changed. After the formation of the interlayer insulating film, heat treatment was performed in nitrogen at 300 ° C. for 1 hour in order to activate the implanted ions and harden the interlayer insulating film. The sheet resistance value of the source / drain region after heat treatment is (93 ± 22) kΩ with 95% reliability coefficient.
It was / □. In the first embodiment, the ion implantation is performed by the mass non-separation type ion implantation apparatus, and the implanted ions are activated by the low temperature heat treatment at 300 ° C. However, the present invention is not limited to this. Ions may be implanted and activated by laser irradiation. After that, contact holes are opened and source / drain extraction electrodes 210 are formed by a sputtering method or the like to complete the transistor (FIG. 2d). In the first embodiment, aluminum is used as the source / drain take-out electrode material and the sputtering method is performed at 8000.
The source / drain extraction electrodes were formed by depositing to a thickness of Å. At this time, the sheet resistance of the deposited aluminum film is 4
It was 2.5 ± 2.0 mΩ / □.

【００４０】この様にして試作した薄膜トランジスタ
（ＴＦＴ）の特性を温度２５℃で測定した。トランジス
タサイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１
０μｍで有った。Ｖｄｓ＝４ｖで得られた結果を図１の
Ａに示す。ＳＰＣ膜中の欠陥や不対電子が終端された事
実を反映して、オフ状態（Ｖｇｓ＜−５ｖ）からオン状
態（Ｖｇｓ＞０ｖ）への立ち上がりが急峻となり、最小
電流値（Ｖｇｓ＝−４ｖ）も小さい良好な薄膜半導体装
置が得られた。又、水素化処理が一切行われていない分
だけ工程は簡略化し、しかも大型基板内及び基板間で均
質な薄膜半導体装置が製造された。The characteristics of the thin film transistor (TFT) manufactured as described above were measured at a temperature of 25 ° C. Transistor size is channel length L = 10μm, width W = 1
It was 0 μm. The results obtained with Vds = 4v are shown in FIG. Reflecting the fact that defects and unpaired electrons in the SPC film are terminated, the rise from the off state (Vgs <-5v) to the on state (Vgs> 0v) becomes steep, and the minimum current value (Vgs = -4v). ) Was obtained, and a good thin film semiconductor device was obtained. Further, the process was simplified by the amount that no hydrogenation treatment was performed, and a thin film semiconductor device that was homogeneous in and between large substrates was manufactured.

【００４１】これに対して従来技術ではその様な良好な
薄膜半導体装置を作成し得ない。以下本発明の優位性を
明瞭と化す為に従来技術との比較を行う。従来技術と本
発明の違いは非晶質半導体膜の熱処理方法で有る。従来
技術では非晶質半導体膜形成後、大気圧窒素雰囲気下で
熱処理を行っていた。即ち純窒素雰囲気下４００℃の熱
処理炉に基板を挿入した後１時間費やして６００℃まで
温度を上げ、その後６００℃にて１５時間維持した。従
来技術で熱処理を施された基板は以下本実施例１の本発
明と同一の工程を経て薄膜トランジスタを完成せられ
た。こうして従来技術で製造された薄膜半導体装置のト
ランジスタ特性を図１のｄに示す。この比較例が示す様
に従来技術の熱処理で、ゲート絶縁膜をＥＣＲ−ＰＥＣ
ＶＤ法以外の方法（例えばこの比較例が用いたＡＰＣＶ
Ｄ法）で形成し、水素化処理を施さないと、オフ電流が
高く、スイッチング特性の優れぬ薄膜半導体装置と化し
てしまう。又、比較例のソース・ドレイン領域のシート
抵抗は９５％の信頼係数で（１８２±６２）ｋΩ／□で
有った。本発明が従来技術に比してソース・ドレイン領
域のシート抵抗を下げる原因も、優良な薄膜半導体装置
を製造し得る理由も、本発明に依り半導体膜中の欠陥が
補修されたり、不対電子が酸素で終端された為、電子等
のキャリアの欠陥及び不対電子等との非弾性散乱が減っ
た事や、結晶粒界及び結晶粒内での捕獲準位数が減った
が故で有る。この様に本発明に依り良質な半導体膜が得
られ、これらにドナー又はアクセプターとなる不純物を
添加すると低抵抗の電気伝導膜が得られ、又これらを能
動層半導体膜として用いると優良な薄膜半導体装置が得
られるので有る。On the other hand, the prior art cannot produce such a good thin film semiconductor device. Hereinafter, in order to clarify the superiority of the present invention, a comparison with the prior art will be made. The difference between the prior art and the present invention lies in the heat treatment method for the amorphous semiconductor film. In the prior art, after forming the amorphous semiconductor film, heat treatment was performed in an atmosphere of nitrogen. That is, after the substrate was inserted into a heat treatment furnace at 400 ° C. in a pure nitrogen atmosphere, the temperature was raised to 600 ° C. by spending 1 hour and then maintained at 600 ° C. for 15 hours. The substrate which has been heat-treated by the conventional technique was completed as a thin film transistor through the same steps as those of the present invention of the first embodiment. The transistor characteristics of the thin film semiconductor device manufactured by the conventional technique in this manner are shown in FIG. As shown in this comparative example, the gate insulating film is subjected to ECR-PEC by the conventional heat treatment.
Methods other than the VD method (for example, the APCV used in this comparative example)
If it is formed by the D method) and is not subjected to a hydrogenation treatment, a thin film semiconductor device having a high off current and excellent switching characteristics will be obtained. The sheet resistance of the source / drain region of the comparative example was (182 ± 62) kΩ / □ with a 95% reliability coefficient. The reason why the present invention lowers the sheet resistance of the source / drain regions as compared with the prior art, and the reason why an excellent thin film semiconductor device can be manufactured, the defect in the semiconductor film is repaired by the present invention, and the unpaired electron Is terminated by oxygen, which is because carrier defects such as electrons and inelastic scattering with unpaired electrons are reduced, and the number of trap levels at the grain boundaries and grains is reduced. . Thus, according to the present invention, a good-quality semiconductor film can be obtained. By adding an impurity serving as a donor or an acceptor to these, an electrically conductive film having a low resistance can be obtained. That is because a device can be obtained.

【００４２】（実施例２）非晶質半導体膜の結晶化を進
める熱処理方法を除いて、その他の工程は総て実施例１
に記載した本発明と同一の製造方法で薄膜半導体装置を
作成した。本実施例２では減圧下不活性雰囲気にて非晶
質半導体膜の結晶化を進めた後、連続して酸化性雰囲気
に熱処理炉内環境を変えて良質な結晶性半導体膜を得
た。Example 2 Except for the heat treatment method for promoting the crystallization of the amorphous semiconductor film, all other steps were performed in Example 1.
A thin film semiconductor device was produced by the same manufacturing method as that of the present invention described in 1. In Example 2, after the crystallization of the amorphous semiconductor film proceeded in an inert atmosphere under reduced pressure, the environment in the heat treatment furnace was continuously changed to an oxidizing atmosphere to obtain a good quality crystalline semiconductor film.

【００４３】実施例１に詳述した手法で非晶質半導体膜
を堆積された基板は１．６７％弗化水素酸水溶液に２０
秒間浸され、非晶質半導体膜表面から自然酸化膜を取り
除いた。その後基板は直ちに不活性雰囲気下に設置さ
れ、熱処理を施された。The substrate on which the amorphous semiconductor film was deposited by the method described in detail in Example 1 was immersed in a 1.67% hydrofluoric acid aqueous solution for 20 minutes.
It was immersed for 2 seconds to remove the natural oxide film from the surface of the amorphous semiconductor film. The substrate was then immediately placed in an inert atmosphere and heat treated.

【００４４】熱処理炉は縦型炉で４００℃に保たれてお
り、純度９９．９９９％以上の窒素２０ＳＬＭと純度９
９．９９９９％以上のヘリウム１０ＳＬＭが熱処理炉上
部より熱処理炉に導入され、下部基板挿入口より排出さ
れて居る。本実施例２の様に縦型炉で下側より基板挿入
する場合、空気よりも軽い不活性気体を上方から下方に
流す事に依り、空気や水等の不純物気体の混入を防ぐ事
が出来、熱処理炉内を完全な不活性雰囲気に保つ事が出
来る。The heat treatment furnace was a vertical furnace maintained at 400 ° C., and nitrogen 20 SLM with a purity of 99.999% or more and a purity of 9
9.9999% or more of helium 10 SLM is introduced into the heat treatment furnace from the upper portion of the heat treatment furnace and discharged from the lower substrate insertion port. When the substrate is inserted from the lower side in the vertical furnace as in the second embodiment, it is possible to prevent the mixture of the impurity gas such as air and water by flowing the inert gas lighter than the air from the upper side to the lower side. , It is possible to keep the inside of the heat treatment furnace in a completely inert atmosphere.

【００４５】基板挿入後、真空引きを行い、熱処理炉内
に純度９９．９９９％以上の窒素２００SCCMと純度９
９．９９９％以上のヘリウム１００SCCMを流し続け、熱
処理炉内の圧力を１０torrに保った。基板挿入時の酸素
等の混入は殆ど無く、常時不活性ガスが流れ続けている
ので、窒素中の不純物が総て酸素で有ると厳しく仮定し
ても熱処理炉内の酸素分圧は０．１mtorr以下で有る。
窒素の純度９９．９９９％以上とは簡易測定の測定限界
を示す物で、通常は純度はもっと高い。従って熱処理炉
内の酸素分圧はどんなに高くとも０．１mtorrを超える
事は有り得ず、０．０５mtorr以下で有る。After inserting the substrate, vacuuming is performed, and 200 SCCM of nitrogen having a purity of 99.999% or more and a purity of 9
The pressure in the heat treatment furnace was maintained at 10 torr by continuously flowing 100 SCCM of helium of 9.999% or more. There is almost no mixing of oxygen when inserting the substrate, and since the inert gas is constantly flowing, even if it is strictly assumed that all the impurities in nitrogen are oxygen, the oxygen partial pressure in the heat treatment furnace is 0.1 mtorr. It is below.
Nitrogen purity of 99.999% or more indicates the measurement limit of simple measurement, and the purity is usually higher. Therefore, the oxygen partial pressure in the heat treatment furnace can never exceed 0.1 mtorr, but is 0.05 mtorr or less.

【００４６】熱処理炉内の酸素分圧を０．１mtorr以
下、好ましくは０．０５mtorr以下、より好ましくは
０．０１mtorr以下にした後、熱酸化炉の温度を１時間
掛けて６００℃まで上げ、その後その状態で１２時間維
持した。この熱処理に依り非晶質半導体膜は結晶化して
多結晶状態へと固体状態を変えるが、半導体原子の移動
等に伴う欠陥や不対電子が結晶粒界や膜表面に多数存在
して居る。１２時間の熱処理後、６００℃の温度に維持
したまま、不活性気体の供給を止め反応炉内に純度９
９．９９９％以上の酸素を導入し、１気圧とした。この
６００℃、１気圧純酸素雰囲気下で更に連続して３時間
の熱処理を施した。この酸素雰囲気化での熱処理時間に
於ける酸素分圧は０．１気圧から１０気圧が好ましい。
圧力が高くなると安全上の問題が生じ、逆に低いと酸素
による欠陥終端が遅くなり生産性の妨げとなる。従って
より好ましくは０．３気圧から７気圧が酸素分圧として
適しており、更に好ましくは０．７気圧から３気圧で有
る。熱処理温度は５００℃から７００℃程度の間が使用
される。結晶成長をゆっくり大きくさせるとの観点から
は低温の方が好ましいが、結晶化に長時間費やす。本実
施例２の様に６００℃にて熱処理を施す場合は１０時間
で結晶化はほぼ完了するが、５５０℃とすると熱処理時
間は１００時間以上となり、又７００℃とすると１時間
程度で済む。熱処理温度はこうした長短より決められる
が、好ましくは５３０℃程度から６７０℃程度、更に好
ましくは５５０℃から６５０℃程度、より好ましくは５
７０℃程度から６３０℃程度で有る。After setting the oxygen partial pressure in the heat treatment furnace to 0.1 mtorr or less, preferably 0.05 mtorr or less, more preferably 0.01 mtorr or less, the temperature of the thermal oxidation furnace is increased to 600 ° C. over 1 hour, and then The state was maintained for 12 hours. By this heat treatment, the amorphous semiconductor film is crystallized and changes its solid state into a polycrystalline state, but many defects and unpaired electrons due to the movement of semiconductor atoms are present at the crystal grain boundaries and the film surface. After the heat treatment for 12 hours, the inert gas supply was stopped while keeping the temperature at 600 ° C.
9.999% or more of oxygen was introduced to 1 atm. In this atmosphere of pure oxygen at 600 ° C. and 1 atmosphere, heat treatment was further continued for 3 hours. The oxygen partial pressure during the heat treatment in the oxygen atmosphere is preferably 0.1 atm to 10 atm.
Higher pressures pose a safety concern, while lower pressures slow oxygen defect termination and impede productivity. Therefore, the oxygen partial pressure is more preferably 0.3 atm to 7 atm, and further preferably 0.7 atm to 3 atm. The heat treatment temperature is about 500 to 700 ° C. From the viewpoint of slowly increasing the crystal growth, a low temperature is preferable, but it takes a long time for crystallization. When heat treatment is performed at 600 ° C. as in Example 2, crystallization is almost completed in 10 hours, but when 550 ° C., the heat treatment time is 100 hours or more, and when 700 ° C., it takes about 1 hour. The heat treatment temperature is determined depending on the length, but is preferably about 530 ° C to 670 ° C, more preferably about 550 ° C to 650 ° C, and more preferably 5 ° C.
It is about 70 to 630 ° C.

【００４７】こうして得られた多結晶半導体膜を用いて
以下実施例１の本発明と全く同じ工程にて薄膜半導体装
置を作成した。得られたトランジスタ特性を図１−ｂに
示す。従来技術と比較する迄も無く、実施例１の発明に
比べても更に優良な特性となっている事が分かる。又、
本実施例２で作成された薄膜半導体装置のソース・ドレ
イン領域のシート抵抗は９５％の信頼係数で（８５±２
０）ｋΩ／□で有った。本実施例２で実施例１の発明よ
りも良質な半導体膜が得られたのは、実施例１が弱酸化
性雰囲気下で結晶成長と酸化皮膜の形成が競争過程で有
ったのに対し、本実施例２では酸素分圧を０．１mtorr
以下として酸化皮膜の成長を完全に押さえ、結晶成長し
た後に酸素に依る欠陥等を終端した為、実施例１の発明
に比べてより効果的に欠陥補修がなされたので有る。本
実施例２では熱処理中の酸素分圧を低くする為に１０to
rrの減圧下で熱処理を施し、その後酸素分圧１気圧で熱
処理したが、熱処理温度が６００℃程度で有れば酸素分
圧は１０mtorr程度以下で有れば殆ど酸化は進まないか
ら、大気圧不活性雰囲気下で第一の熱処理をした後、酸
化性雰囲気で第二の熱処理を施しても良い。この場合、
第一の熱処理時の窒素純度は９９．９９９％以上で有れ
ば十分で有る。又、第一の不活性雰囲気下での熱処理時
に流す気体も窒素・ヘリウムに限られず、ネオン・アル
ゴン・クリプトン・キセノン等の希ガス単体又はこれら
の混合気体で有っても良い。更に第二の酸化性雰囲気下
での熱処理時に流す気体も酸素に限られず、笑気ガス・
水・二酸化炭素等の酸化性気体やこれらの混合気体、更
には酸化性気体と不活性気体の混合気体で有っても良
い。Using the thus obtained polycrystalline semiconductor film, a thin film semiconductor device was manufactured by the same steps as in the present invention of Example 1. The obtained transistor characteristics are shown in FIG. 1-b. It goes without saying that the characteristics are even better than those of the invention of Example 1, not to mention comparison with the conventional technology. or,
The sheet resistance of the source / drain regions of the thin film semiconductor device manufactured in the second embodiment has a reliability coefficient of 95% (85 ± 2).
0) It was kΩ / □. In this second embodiment, a semiconductor film of better quality than that of the first embodiment is obtained, whereas in the first embodiment, crystal growth and oxide film formation are in a competitive process in a weakly oxidizing atmosphere. In the second embodiment, the oxygen partial pressure is 0.1 mtorr.
As described below, since the growth of the oxide film was completely suppressed, and the defects and the like due to oxygen were terminated after the crystal growth, the defect repair was performed more effectively than the invention of Example 1. In the second embodiment, 10 to 10 is used to reduce the oxygen partial pressure during the heat treatment.
The heat treatment was performed under a reduced pressure of rr and then the oxygen partial pressure was 1 atm. However, if the heat treatment temperature is about 600 ° C., the oxygen partial pressure is about 10 mtorr or less, and the oxidation hardly progresses. After the first heat treatment is performed in an inert atmosphere, the second heat treatment may be performed in an oxidizing atmosphere. in this case,
It is sufficient that the nitrogen purity during the first heat treatment is 99.999% or more. Further, the gas flown during the heat treatment in the first inert atmosphere is not limited to nitrogen / helium, but may be a rare gas simple substance such as neon / argon / krypton / xenon or a mixed gas thereof. Furthermore, the gas that flows during the heat treatment in the second oxidizing atmosphere is not limited to oxygen,
It may be an oxidizing gas such as water and carbon dioxide, a mixed gas thereof, or a mixed gas of an oxidizing gas and an inert gas.

【００４８】（実施例３）非晶質半導体膜の結晶化を進
める熱処理方法を除いて、その他の工程は全て実施例１
に記載した本発明と同一の製造方法で薄膜半導体装置を
作成した。本実施例３では減圧下還元性雰囲気にて非晶
質半導体膜の結晶化を進めた後、連続して酸化性雰囲気
に熱処理炉内環境を変えて良質な結晶性半導体膜を得
た。Example 3 Except for the heat treatment method for promoting the crystallization of the amorphous semiconductor film, all other steps were performed in Example 1.
A thin film semiconductor device was produced by the same manufacturing method as that of the present invention described in 1. In Example 3, after crystallization of the amorphous semiconductor film in a reducing atmosphere under reduced pressure, the environment in the heat treatment furnace was continuously changed to an oxidizing atmosphere to obtain a good quality crystalline semiconductor film.

【００４９】実施例１に詳述した手法で非晶質半導体膜
を堆積された基板は１．６７％弗化水素酸水溶液に２０
秒間浸され、非晶質半導体膜表面から自然酸化膜を取り
除いた。その後基板は直ちに還元性雰囲気下に設置さ
れ、熱処理を施された。The substrate on which the amorphous semiconductor film was deposited by the method described in detail in Example 1 was immersed in a 1.67% hydrofluoric acid aqueous solution for 20 minutes.
It was immersed for 2 seconds to remove the natural oxide film from the surface of the amorphous semiconductor film. Then, the substrate was immediately placed in a reducing atmosphere and subjected to heat treatment.

【００５０】熱処理炉は縦型炉で４００℃に保たれて居
り、純度９９．９９９９％以上の水素５００SCCMと純度
９９．９９９９％以上のヘリウム２０ＳＬＭが熱処理炉
上部より熱処理炉に導入され、下部基板挿入口より排出
されて居る。本実施例３の様に縦型炉で下側より基板挿
入する場合、空気よりも軽い還元性気体を上方から下方
に流す事に依り、空気や水等の不純物気体の混入を防ぐ
事が出来、熱処理炉内を完全な還元性雰囲気に保つ事が
出来る。The heat treatment furnace was a vertical furnace kept at 400 ° C., 500 SCCM of hydrogen with a purity of 99.9999% or more and helium 20 SLM with a purity of 99.9999% or more were introduced into the heat treatment furnace from the upper part of the heat treatment furnace, and the lower substrate. It is discharged from the insertion slot. When the substrate is inserted from the lower side in the vertical furnace as in the third embodiment, it is possible to prevent the mixing of the impurity gas such as air or water by flowing the reducing gas lighter than the air from the upper side to the lower side. , It is possible to maintain a complete reducing atmosphere inside the heat treatment furnace.

【００５１】基板挿入後、真空引きを行い、熱処理炉内
に純度９９．９９９９％以上の水素２００SCCMと純度９
９．９９９９％以上のヘリウム１００SCCMを流し続け、
熱処理炉内の圧力を１０torrに保った。従って水素分圧
は６．７torrで有る。その後熱処理炉の温度を１時間掛
けて６００℃に上げ、続いてその状態で１２時間維持し
た。次に熱処理炉の温度を６００℃に保ったまま熱処理
炉内を３分間真空引きし、更に純度９９．９９９９％以
上のヘリウムを３００SCCM３分間流した後、再度３分間
の真空引きを行い、その後熱処理炉に純度９９．９９９
％以上の酸素を導入して１気圧とした。この６００℃、
純酸素１気圧の雰囲気下で更に連続して３時間の熱処理
を施した。還元性雰囲気に於ける熱処理の場合、水素分
圧は０．１mtorrから１０気圧程度が好ましいが、実用
的には０．１torrから１気圧程度が好ましく、更には１
torrから０．１気圧が最適で有る。連続して行われる酸
化性雰囲気下での熱処理時に於ける酸素分圧は０．１気
圧から１０気圧が好ましい。圧力が高くなると安全上の
問題が生じ、逆に低いと酸素に依る欠陥終端が遅くなり
生産性の妨げとなる。従ってより好ましくは０．３気圧
から７気圧が酸素分圧として適しており、更に好ましく
は０．７気圧から３気圧で有る。熱処理温度は５００℃
から７００℃程度の間が使用される。結晶成長をゆっく
り大きくさせるとの観点からは低温の方が好ましいが、
結晶化に長時間費やす。本実施例３の様に６００℃にて
熱処理を施す場合は１０時間で結晶化はほぼ完了する
が、５５０℃とすると熱処理時間は１００時間以上とな
り、又７００℃とすると１時間程度で済む。熱処理温度
はこうした長短より決められるが、好ましくは５３０℃
程度から６７０℃程度、更に好ましくは５５０℃から６
５０℃程度、より好ましくは５７０℃程度から６３０℃
程度で有る。After inserting the substrate, vacuuming is performed, and 200 SCCM of hydrogen having a purity of 99.9999% or more and a purity of 9
Continue flowing helium 100SCCM of 9.9999% or more,
The pressure in the heat treatment furnace was kept at 10 torr. Therefore, the hydrogen partial pressure is 6.7 torr. After that, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained in that state for 12 hours. Next, the inside of the heat treatment furnace is evacuated for 3 minutes while keeping the temperature of the heat treatment furnace at 600 ° C., helium having a purity of 99.9999% or more is flown for 300 SCCM for 3 minutes, and then evacuated for 3 minutes again. Purity 99.999 in the furnace
% Or more of oxygen was introduced to 1 atm. This 600 ℃,
Heat treatment was further continuously performed for 3 hours in an atmosphere of pure oxygen at 1 atm. In the case of heat treatment in a reducing atmosphere, the hydrogen partial pressure is preferably about 0.1 mtorr to 10 atm, but practically about 0.1 torr to 1 atm, and further 1
The optimum value is 0.1 atm from torr. The oxygen partial pressure during heat treatment under an oxidizing atmosphere that is continuously performed is preferably 0.1 atm to 10 atm. Higher pressures pose safety concerns, while lower pressures slow oxygen-based defect termination and hinder productivity. Therefore, the oxygen partial pressure is more preferably 0.3 atm to 7 atm, and further preferably 0.7 atm to 3 atm. Heat treatment temperature is 500 ℃
It is used at temperatures between about 700 ° C and 700 ° C. From the viewpoint of slowly increasing the crystal growth, low temperature is preferable,
It takes a long time to crystallize. When heat treatment is performed at 600 ° C. as in Example 3, crystallization is almost completed in 10 hours, but at 550 ° C., the heat treatment time is 100 hours or more, and at 700 ° C., it takes about 1 hour. The heat treatment temperature is determined depending on the length, but is preferably 530 ° C.
To 670 ° C, more preferably 550 ° C to 6
50 ° C, more preferably 570 ° C to 630 ° C
There is a degree.

【００５２】こうして得られた多結晶半導体膜を用いて
以下実施例１の本発明と全く同じ工程にて薄膜半導体装
置を作成した。得られたトランジスタ特性を図１のＣに
示す。実施例２と同様、優良な特性を有する薄膜半導体
装置が得られた。本実施例３で作成された薄膜半導体装
置のソース・ドレイン領域のシート抵抗値は９５％の信
頼係数で（８４±１７）ｋΩ／□で有った。本実施例３
でも還元性雰囲気下で結晶成長を行い、酸化皮膜の形成
を完全に押さえ、結晶成長終了後酸素に依る欠陥補修を
効果的に行い得た事に基づき、良質な半導体膜が得られ
た。尚、本実施例３での還元性雰囲気下での熱処理は減
圧下で行われたが、これは常圧で有っても構わない。又
還元性気体も水素に限られず、アンモニア等も可能で有
る。無論酸化性気体も酸素に限られず、実施例２に述べ
た酸化性気体も有効で有る。Using the polycrystalline semiconductor film thus obtained, a thin film semiconductor device was prepared by the same steps as those of the present invention of Example 1 below. The obtained transistor characteristics are shown in C of FIG. Similar to Example 2, a thin film semiconductor device having excellent characteristics was obtained. The sheet resistance value of the source / drain region of the thin film semiconductor device manufactured in Example 3 was (84 ± 17) kΩ / □ with a 95% reliability coefficient. Example 3
However, a good quality semiconductor film was obtained based on the fact that the crystal growth was performed in a reducing atmosphere, the formation of the oxide film was completely suppressed, and the defect repair due to oxygen could be effectively performed after the crystal growth was completed. Although the heat treatment in the reducing atmosphere in Example 3 was performed under reduced pressure, this may be performed under normal pressure. Also, the reducing gas is not limited to hydrogen, and ammonia or the like is also possible. Of course, the oxidizing gas is not limited to oxygen, and the oxidizing gas described in Example 2 is also effective.

【００５３】（実施例４）図３ａ〜ｄは本実施例４に於
ける自己整合型スタガード構造のＭＩＳ型電界効果トラ
ンジスタを構成するシリコン薄膜半導体装置の製造工程
を断面で示した図で有る。(Embodiment 4) FIGS. 3A to 3D are sectional views showing a manufacturing process of a silicon thin film semiconductor device which constitutes a MIS field effect transistor having a self-aligned staggered structure according to the fourth embodiment.

【００５４】本実施例４では、下地基板３０１として２
３５ｍｍ□の溶融石英ガラスを用いたが、６００℃の工
程最高温度に耐え得る基板又は下地物質で有るならば、
その種類や大きさは無論問われない。例えば通常ガラス
基板の他にシリコンウェハーなどの半導体基板及びそれ
らを加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン
・カーバイト、アルミナ、窒化アルミニウムなどのセラ
ミックス基板なども下地基板として可能で有る。In the fourth embodiment, the base substrate 301 is 2
35mm □ fused silica glass was used, but if it is a substrate or base material that can withstand the maximum process temperature of 600 ° C,
Of course, its kind and size are not questioned. For example, in addition to a glass substrate, a semiconductor substrate such as a silicon wafer, an LSI obtained by processing them, a three-dimensional LSI, or a ceramics substrate such as silicon carbide, alumina, or aluminum nitride can be used as the base substrate.

【００５５】まずアセトン又はメチル・エチル・ケト
ン，メチル・イソ・ブチル・ケトンやシクロヘキサノン
などの有機溶剤中に下地基板３０１を浸し、超音波洗浄
を行う。洗浄後窒素中又は減圧下にて乾燥を施し、更に
エタノールによる超音波洗浄を行った後窒素バブリング
されている純水にて水洗を施す。次に下地基板３０１を
沸騰している濃度６０％の硝酸中に５分間浸し、更に窒
素バブリングされている純水中で洗浄した。基板として
金属など酸に依り腐食されたり、変質して仕舞う物質を
用いる場合、この硝酸に依る洗浄は必要とされない。又
この強酸に依る洗浄では酸として硝酸の他に硫酸なども
可能で有る。First, the base substrate 301 is immersed in an organic solvent such as acetone or methyl-ethyl-ketone, methyl-iso-butyl-ketone or cyclohexanone, and ultrasonic cleaning is performed. After cleaning, the product is dried in nitrogen or under reduced pressure, further ultrasonically cleaned with ethanol, and then rinsed with pure water with nitrogen bubbling. Next, the base substrate 301 was immersed in boiling nitric acid having a concentration of 60% for 5 minutes, and further washed in pure water with nitrogen bubbling. When a substance such as a metal that is corroded by acid or deteriorates and is used as a substrate is used, the cleaning by nitric acid is not required. In addition, in washing with this strong acid, sulfuric acid as well as nitric acid can be used as the acid.

【００５６】こうして洗浄された石英基板上に常圧気相
化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化
硅素膜（ＳｉＯ₂膜）３０２を２０００Å堆積した。こ
の下地ＳｉＯ₂膜３０２は前述の如き種々多様な物質を
基板として用いる際、後に堆積される半導体膜の膜質、
及びそれを用いて構成される薄膜トランジスタの性能を
安定化する為に必要で有る。と同時に、例えば基板３０
１として通常ガラスを用いた場合、ガラス中に含まれて
いるナトリウムなどの可動イオンが、又基板３０１とし
て各種セラミック板を用いた際には基板中に添加されて
いる焼結助材原料などがトランジスタ部に拡散混入する
のを防ぐ役割をも演じている。又金属板を基板３０１と
して用いる場合は、絶縁性を確保する為に下地ＳｉＯ₂
は必要不可欠で有る。又、三次元ＬＳＩ素子では、トラ
ンジスタ間や配線間の層間絶縁膜に相当している。下地
ＳｉＯ₂膜３０２堆積時の基板温度は３００℃で、窒素
に依り２０％に希釈されたシラン６００SCCMを８４０SC
CMの酸素と共にＡＰＣＶＤ法で堆積した。この時のＳｉ
Ｏ₂膜の堆積速度は３．９Å／ｓｅｃで有った。2000 Å of silicon dioxide film (SiO ₂ film) 302 serving as a base protective film was deposited on the thus cleaned quartz substrate by atmospheric pressure chemical vapor deposition (APCVD method). This underlying SiO ₂ film 302 is a film quality of a semiconductor film to be deposited later when various substances as described above are used as a substrate,
Also, it is necessary to stabilize the performance of the thin film transistor configured using the same. At the same time, for example, the substrate 30
When ordinary glass is used as 1, the mobile ions such as sodium contained in the glass are used, and when various ceramic plates are used as the substrate 301, the sintering aid raw material added to the substrate is It also plays a role in preventing diffusion and mixing in the transistor section. When a metal plate is used as the substrate 301, a base SiO ₂ film is used to ensure insulation.
Is indispensable. Also, in a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors and between wirings. The substrate temperature at the time of depositing the underlying SiO ₂ film 302 is 300 ° C., and 840 SC of silane 600 SCCM diluted to 20% with nitrogen is used.
It was deposited by the APCVD method together with CM oxygen. Si at this time
The deposition rate of the O ₂ film was 3.9 Å / sec.

【００５７】次に減圧ＣＶＤ法でいずれ能動層となる非
晶質半導体膜を堆積した。本実施例４では半導体膜とし
てシリコンを用いたが、シリコン・ゲルマニウムやガリ
ウム・ヒ素等他の半導体も可能で有る。Next, an amorphous semiconductor film, which will eventually become an active layer, is deposited by the low pressure CVD method. Although silicon is used as the semiconductor film in the fourth embodiment, other semiconductors such as silicon-germanium and gallium-arsenic are also possible.

【００５８】半導体膜堆積に用いた減圧ＣＶＤ反応炉の
容積は１８４．５ｌで、基板は反応炉中央付近に水平に
置かれる。原料ガス及びヘリウム・窒素・アルゴン・水
素等の希釈ガスは必要に応じて反応炉下部より炉内に導
入され、反応炉上部から排気される。石英ガラスで作ら
れた反応炉の外側には３ゾーンに分かれたヒーターが設
置されて居り、それらを独立に調整する事で反応炉内中
央部付近に所望の温度で均熱帯を形成する。この均熱帯
は約３５０ｍｍの高さで広がり、その範囲内での温度の
ずれは、例えば５００℃に設定した時０．２℃以内であ
る。従って挿入基板間の間隔を７ｍｍとすれば１バッチ
で５０枚の基板の処理が可能で有る。本実施例４では２
０ｍｍ間隔で１７枚の基板を均熱帯内に設置した。The volume of the low pressure CVD reactor used for semiconductor film deposition was 184.5 l, and the substrate was placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, hydrogen, etc. are introduced into the furnace from the lower part of the reaction furnace and exhausted from the upper part of the reaction furnace as needed. Outside the reactor made of quartz glass, there are heaters divided into three zones, and by adjusting them independently, a soaking zone is formed near the center of the reactor at a desired temperature. This soaking zone spreads at a height of about 350 mm, and the temperature shift within that range is within 0.2 ° C. when set to 500 ° C., for example. Therefore, if the distance between the insertion substrates is 7 mm, it is possible to process 50 substrates in one batch. 2 in the fourth embodiment
Seventeen substrates were placed in the soaking zone at 0 mm intervals.

【００５９】排気はロータリーポンプとメカニカル・ブ
ースターポンプを直結して行い、反応炉内の圧力は測定
値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バ
ラトロン・マノメーター）に依り測定した。反応炉を５
５０℃に保って、ガス導入用のバルブを閉じて両ポンプ
にて真空引きを行った場合、反応炉内圧は０mtorrで有
る為、背景真空度は悪くとも１０^-4torr程度以下で有
る。Exhaust was carried out by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reaction furnace was measured by a diaphragm pressure gauge (MKS Co. Baratron Manometer) whose measured value did not depend on the type of gas. 5 reactors
When the temperature is kept at 50 ° C., the gas introduction valve is closed, and both pumps are evacuated, the internal pressure of the reaction furnace is 0 mtorr, and therefore the background vacuum degree is at most 10 ⁻⁴ torr or less.

【００６０】半導体膜を堆積すべき基板は、表側を下向
きとして減圧ＣＶＤ炉内に挿入された。挿入時の反応炉
内温度は３９５℃から４００℃程度で有った。基板挿入
時に反応炉内には上部より純度が９９・９９９９％以上
のヘリウムと水素の混合気体が３０ＳＬＭ導入され、こ
れらの混合気体は反応炉下部に設けられた基板挿入口よ
り排出されて居る。基板挿入口の直径は５４０ｍｍでそ
の断面積は２２９０ｃｍ²で有る。混合気体が４００℃
に熱せられていると、基板挿入口からの混合気体の排出
速度は２９．６ｃｍ／ｍｉｎとなる。又、本実施例４の
如く２３５ｍｍ□の基板を水平に設置する場合、基板面
積は５５２ｃｍ²で有るから基板が基板挿入口より反応
炉内に入っていく時に基板挿入口と基板の隙間から排出
される混合気体の排出速度は３９．０ｃｍ／ｍｉｎで有
る。本実施例４では２０ｃｍ／ｍｉｎの上昇速度で基板
を反応炉に挿入したが、混合気体の排出速度の方が速い
為、基板挿入に伴う空気等の反応室への混入を防ぐ事が
出来る。又、混合気体の密度は空気密度よりもはるかに
小さく、しかも熱せられているので重い空気がこれらの
軽い気体を押し退けて下から上へ入る可能性は殆ど無
い。本実施例４で反応炉上部より導入した混合気体の濃
度はヘリウム９７％に水素３％で有った。水素の爆発下
限界は４．０％なので、これ以下の濃度で有れば基板挿
入口より室内に排出されても安全で有る。こうした基板
挿入方法を用いる事に依り、ロードロック室を用いて１
バッチ毎に真空引きを行うといった煩雑な過程を経る事
無くして、反応炉内を清浄な非酸化性雰囲気下に保てら
れるので有る。基板挿入時に空気や水等の不純物気体が
反応炉内に流れ込むと、これらは反応炉内壁の半導体層
に吸着し、又は半導体元素と反応して反応炉内に残留
し、半導体膜堆積の際、脱ガスとして現れ、堆積膜の膜
品質を低下させる原因となる。従って本発明の基板挿入
を用いたＣＶＤ方法では容易に高品質半導体膜が堆積さ
れるので有る。The substrate on which the semiconductor film was to be deposited was inserted into a low pressure CVD furnace with the front side facing downward. The temperature inside the reaction furnace at the time of insertion was about 395 ° C to 400 ° C. When the substrate was inserted, 30 SLM of a mixed gas of helium and hydrogen having a purity of 99.9999% or more was introduced into the reaction furnace from above, and the mixed gas was discharged from the substrate insertion port provided in the lower part of the reaction furnace. The diameter of the substrate insertion port is 540 mm and its cross-sectional area is 2290 cm ² . Mixed gas is 400 ° C
When heated to, the discharge rate of the mixed gas from the substrate insertion port becomes 29.6 cm / min. Further, when a 235 mm square substrate is installed horizontally as in the fourth embodiment, since the substrate area is 552 cm ² , the substrate is discharged from the gap between the substrate insertion port and the substrate when entering the reaction furnace from the substrate insertion port. The discharge rate of the mixed gas is 39.0 cm / min. In Example 4, the substrate was inserted into the reaction furnace at a rising rate of 20 cm / min. However, since the mixed gas is discharged at a higher rate, it is possible to prevent air or the like from entering the reaction chamber when the substrate is inserted. Also, the density of the mixed gas is much smaller than the air density, and since it is heated, there is little possibility that heavy air will push these light gases away and enter from the bottom to the top. The concentration of the mixed gas introduced from the upper portion of the reactor in Example 4 was 97% helium and 3% hydrogen. The lower limit of hydrogen explosion is 4.0%, so if the concentration is lower than this, it is safe to be discharged indoors from the substrate insertion port. By using this board insertion method, it is possible to
The inside of the reaction furnace can be kept in a clean non-oxidizing atmosphere without having to go through the complicated process of vacuuming each batch. When an impurity gas such as air or water flows into the reaction furnace at the time of inserting the substrate, these are adsorbed to the semiconductor layer on the inner wall of the reaction furnace, or react with the semiconductor elements and remain in the reaction furnace. It appears as degassing and causes deterioration of the film quality of the deposited film. Therefore, a high-quality semiconductor film can be easily deposited by the CVD method using substrate insertion of the present invention.

【００６１】基板挿入後、真空引き、漏洩検査を施し
た。漏洩検査では反応炉に通ずる全バルブを閉じて反応
炉を完全に孤立させて、反応炉内圧力の変化を調べた。
本実施例４では反応炉内温度が４００℃で２分間の完全
孤立後、反応炉内圧力は１mtorr以下で有った。漏洩検
査にて異常が無い事を確認した後、反応炉内温度を挿入
温度の４００℃から堆積温度まで昇温する。本実施例４
では５１０℃でチャンネル部となる半導体膜を堆積した
為、昇温するのに一時間費やした。炉内温度が堆積温度
の５１０℃に達するには３５分間程度で済むが、反応炉
壁からの脱ガスを充分放出する為にも、最短一時間以
上、好ましくは数時間の昇温期間が望ましい。この昇温
期間中、二つのポンプは運転状態に有り、少なくとも純
度が９９．９９５％以上の不活性又は還元性ガスを流し
続ける。これらのガス種は水素・ヘリウム・窒素・ネオ
ン・アルゴン・キセノン・クリプトン等の純ガスの他、
これらのガスの混合ガスも可能で有る。本実施例４では
純度９９．９９９９％以上のヘリウムを３５０SCCM流し
続け、反応炉内圧力は８１±１．２mtorrで有った。After inserting the substrate, vacuuming and leakage inspection were performed. In the leak test, all the valves leading to the reactor were closed to completely isolate the reactor, and the change in pressure inside the reactor was examined.
In Example 4, after the reactor was completely isolated at 400 ° C. for 2 minutes, the reactor pressure was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature inside the reaction furnace is raised from the insertion temperature of 400 ° C. to the deposition temperature. Example 4
Then, since the semiconductor film to be the channel portion was deposited at 510 ° C., it took 1 hour to raise the temperature. It takes about 35 minutes for the temperature in the furnace to reach the deposition temperature of 510 ° C., but in order to sufficiently release the degas from the reaction furnace wall, the temperature rising period of at least 1 hour or more, preferably several hours is desirable. . During this temperature rising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995%. These gases are pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton,
A mixed gas of these gases is also possible. In Example 4, helium having a purity of 99.9999% or more was continuously flowed at 350 SCCM, and the pressure in the reaction furnace was 81 ± 1.2 mtorr.

【００６２】堆積温度到達後、原料ガスで有る所定量の
シラン又はシランと希釈ガスの混合ガスを反応炉内に導
入し、非晶質半導体膜を堆積する。希釈ガスとしては、
先の昇温期間に流したガスと同種の組み合わせが可能で
有るが、望ましくは各ガスの純度はそれぞれが９９．９
９９％以上が良い。本実施例４では希釈ガスを用いず、
純度９９．９９９％以上のシランを２００SCCM流して非
晶質半導体膜を堆積した。堆積時に於ける反応炉内の圧
力は反応炉とメカニカル・ブースターポンプの間に設置
されたコンダクタンスバルヴの開閉度を調整して、１．
０torrに保った。本実施例４では非晶質半導体膜は２０
Å／ｍｉｎの堆積速度で２５０Åの膜厚に堆積した。After reaching the deposition temperature, a predetermined amount of silane, which is a source gas, or a mixed gas of silane and a diluent gas is introduced into the reaction furnace to deposit an amorphous semiconductor film. As a diluent gas,
It is possible to use the same kind of combination as the gas that was made to flow in the previous heating period, but it is desirable that the purity of each gas is 99.9.
99% or more is good. In Example 4, no diluent gas was used,
Silane having a purity of 99.999% or more was passed through 200 SCCM to deposit an amorphous semiconductor film. The pressure in the reactor at the time of deposition was adjusted by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump.
I kept it at 0 torr. In Example 4, the amorphous semiconductor film is 20
It was deposited to a film thickness of 250 Å at a deposition rate of Å / min.

【００６３】本実施例４では非晶質半導体膜の堆積をＬ
ＰＣＶＤ法で行い、原料ガスもモノシランを用いたが、
これ以外にもプラズマＣＶＤ法や光ＣＶＤ法、ＡＰＣＶ
Ｄ等の各種ＣＶＤ法やスパッター法、蒸着法等各種ＰＶ
Ｄ法等で堆積する事も可能で有る。又原料ガスもモノシ
ランに限らず、ジシランやトリシランなどの高次シラン
やジクロールシラン或いはゲルマンなども可能で有る。
又、無論上記種々のＣＶＤ法と上記種々の原料の組み合
わせに依って非晶質半導体膜を堆積する事も可能で有
る。In Example 4, the deposition of the amorphous semiconductor film was performed by L
Although the PCVD method was used and monosilane was used as the source gas,
Other than this, plasma CVD method, optical CVD method, APCV
Various PV such as various CVD methods such as D, sputtering method, vapor deposition method, etc.
It is also possible to deposit by the D method or the like. Further, the source gas is not limited to monosilane, but higher order silanes such as disilane and trisilane, dichlorsilane, or germane may be used.
Of course, it is also possible to deposit an amorphous semiconductor film by combining the various CVD methods described above and the various raw materials described above.

【００６４】こうして得られた非晶質半導体膜は、レジ
ストでパターニングされた後、四弗化炭素（ＣＦ₄）と
酸素（Ｏ₂）の混合プラズマに依りエッチングされ、い
ずれ能動層となる非晶質半導体膜３０３を形成した（図
３ａ）。本実施例４で形成した非晶質半導体膜はＣＦ₄
とＯ₂の比が５０SCCM対１００SCCMで有る１５Ｐａの真
空プラズマ放電で、その出力が７００Ｗの時のエッチン
グでは２．２Å／ｓｅｃのエッチング速度を有してい
た。The amorphous semiconductor film thus obtained is patterned with a resist and then etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to eventually form an amorphous layer which becomes an active layer. A quality semiconductor film 303 was formed (FIG. 3a). The amorphous semiconductor film formed in Example 4 is CF ₄
The etching rate was 2.2 Å / sec in the etching when the output was 700 W with the vacuum plasma discharge of 15 Pa in which the ratio of O ₂ and O ₂ was 50 SCCM to 100 SCCM.

【００６５】次にこの基板を沸騰している濃度６０％の
硝酸にて洗浄しＡＰＣＶＤ法にてゲート絶縁膜となるＳ
ｉＯ₂膜３０４を１５００Å堆積した。ＡＰＣＶＤ法に
てゲート絶縁膜を堆積する時の基板温度は３００℃で窒
素に依り２０％に希釈されたシラン３００SCCMと３００
SCCMの酸素を流してＳｉＯ₂膜を堆積した。本実施例４
ではＡＰＣＶＤ法を用いたが、これ以外にもプラズマＣ
ＶＤ法、光ＣＶＤ法、ＬＰＣＶＤ法等の各種ＣＶＤ法や
スパッタ法等のＰＶＤ法も有効で有る。又、原材料もシ
ランに限らずＴＥＯＳ｛Ｓｉ−（ＣＨ₃−ＣＨ₂−Ｏ−）
₄｝等の有機シリコン化合物も利用し得る。無論ＥＣＲ
−ＰＥＣＶＤ法を用いても良い。Next, this substrate is washed with boiling nitric acid having a concentration of 60%, and S which becomes a gate insulating film is formed by the APCVD method.
An iO ₂ film 304 was deposited at 1500Å. The substrate temperature at the time of depositing the gate insulating film by the APCVD method is 300 ° C., and silane 300SCCM and 300 diluted with nitrogen to 20%
The oxygen of SCCM was flowed to deposit the SiO ₂ film. Example 4
In this case, the APCVD method was used.
Various CVD methods such as the VD method, the photo CVD method, the LPCVD method and the PVD method such as the sputtering method are also effective. Moreover, raw materials is not limited to silane _{TEOS {Si- (CH 3 -CH 2} -O-)
₄ } etc. can be used. Of course ECR
-The PECVD method may be used.

【００６６】次にこうして得られた基板を９７℃の硫酸
にて洗浄し、その後基板は直ちに酸化性雰囲気下に設置
され、熱処理を施された。Next, the substrate thus obtained was washed with sulfuric acid at 97 ° C., after which the substrate was immediately placed in an oxidizing atmosphere and heat-treated.

【００６７】熱処理炉は縦型炉で通常４００℃に保たれ
て居り、純度９９．９９９％以上の酸素を３０SLM流し
続けて熱処理炉内部を酸化性雰囲気としている。従って
熱処理炉内の酸素分圧はおよそ１気圧となる。熱処理炉
の容積は１８４．５ｌで有る。基板は縦型炉下部より熱
処理炉内に挿入されるが、酸素は熱処理炉上部より炉内
に導入され下部の挿入口より流出している。室温と温度
平衡に達している基板は酸化性雰囲気で４００℃の炉に
挿入された。基板挿入後熱処理炉の温度を一時間かけて
６００℃まで上げ、その後６００℃にて１５時間維持し
た。この熱処理に依り非晶質半導体膜は結晶化して多結
晶半導体膜へと固体状態を変える。非晶質膜を構成して
いた半導体元素が多結晶状態へと移動すると原子密度の
減少及び空間移動に関する自由度の低さに起因して、出
来上がった多結晶粒内部には必然的におびただしき数の
欠陥や不対電子が発生する。ところが本発明が示す所に
依ると、この様な欠陥及び不対電子は酸素と結合して終
端されるので有る。一般に６００℃程度の温度に於ける
酸素のＳｉＯ₂の拡散は非常に遅い。特にシリコンを酸
化して得られるＳｉＯ₂は稠密で有る為膜厚が数十Åも
有るとＳｉとＳｉＯ₂の界面（以後これをＭＯＳ界面と
呼ぶ）への酸素供給量はかなり限定される。従ってもし
稠密なＳｉＯ₂膜がＳｉ上に１５００Åの厚みで形成さ
れていれば、６００℃、１気圧、十数時間の熱処理では
ＭＯＳ界面に酸素は殆ど供給されない。ところが本実施
例４に於いてはゲート絶縁膜となるＳｉＯ₂膜がＣＶＤ
法により堆積された空疎な膜で有る為、Ｓｉ表面に形成
された数十Å未満の稠密な自然酸化膜までは酸素は自由
に供給されるので有る。稠密で酸素拡散係数の小さいＳ
ｉＯ₂の膜厚が数十Å程度未満で有る事に依り、６００
℃で一気圧程度で有ってもＭＯＳ界面に酸素が供給さ
れ、結晶成長に伴って発生した欠陥や不対電子は効果的
に終端されるので有る。更にＣＶＤ法等で堆積されたＳ
ｉＯ₂膜には未反応Ｓｉ原子やＳｉ−Ｈ基、Ｓｉ−ＯＨ
基、及び不対電子等が沢山残っている。これらの未反応
物はＳｉＯ₂中の電荷となってトランジスタのしきい値
電圧（Ｖｔｈ）を大きくしたり、界面電荷（Ｑｓｓ）を
増大させ、良好な特性を生じさせぬ原因となる。又、こ
れらの未反応物は化学的に不安定で有るので、薄膜半導
体装置を作成した際、半導体装置の経時安定性を損なう
事となる。即ち、稠密で安定的な熱酸化膜に比べて、Ｃ
ＶＤＳｉＯ₂膜は劣っているので有る。ところが本実施
例４では半導体膜の結晶化促進と同時に、酸素熱処理に
よるゲート酸化膜の反応促進と稠密化がなされ、酸化膜
質を大きく向上させるので有る。この熱処理により酸化
膜中に存在していたＳｉ−Ｈ、Ｓｉ−ＯＨ、Ｓｉ−ｅ^-
等はＳｉ−Ｏ−Ｓｉと反応が進められ、同時に稠密とも
なるので有る。実際１．６７％弗化水素酸水溶液による
ＳｉＯ₂のエッチング速度を調べると、熱酸化膜が１．
０Å／ｓｅｃでＡＰＣＶＤのＳｉＯ₂膜が２２Å／ｓｅ
ｃで有ったのに対し、ＡＰＣＶＤ膜を酸素熱処理した本
発明のエッチング速度は４．３Å／ｓｅｃと大幅に改善
されていた。又、従来はＣＶＤＳｉＯ₂膜やそれらの膜
を不活性雰囲気下で熱処理したＳｉＯ₂膜に弗化水素酸
系の水溶液を用いてコンタクト・ホール開孔等の部分エ
ッチングを施すと図５に示す様なＳｉ−ＳｉＯ₂界面に
逆テーパーが生ずる事が頻々と生じていた。これはＳｉ
とＳｉＯ₂の密着性が悪い為、エッチング液がＳｉとＳ
ｉＯ₂の界面に急速に侵入する事に基づく。これに対し
て酸素熱処理を施した本発明のＳｉＯ₂膜は反応が促進
され、密着性が改善されたが故、逆テーパーは生じず、
図６に示す様な順テーパーとなる。コンタクト・ホール
を開孔した時に逆テーパーが生ずると断線となり、電気
的導通が取れないから、薄膜半導体装置を安定的に沢山
製造するには順テーパーは必要不可欠で有る。The heat treatment furnace is a vertical furnace, which is usually kept at 400 ° C., and oxygen having a purity of 99.999% or more is kept flowing at 30 SLM to make the inside of the heat treatment furnace an oxidizing atmosphere. Therefore, the oxygen partial pressure in the heat treatment furnace is about 1 atm. The volume of the heat treatment furnace is 184.5 l. The substrate is inserted into the heat treatment furnace from the lower part of the vertical furnace, but oxygen is introduced into the furnace from the upper part of the heat treatment furnace and flows out from the lower insertion port. The substrate that had reached temperature equilibrium with room temperature was placed in a furnace at 400 ° C. in an oxidizing atmosphere. After inserting the substrate, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained at 600 ° C. for 15 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change its solid state into a polycrystalline semiconductor film. When the semiconductor element that made up the amorphous film moves to the polycrystalline state, it is inevitable that the inside of the finished polycrystalline grain will be affected by the decrease in atomic density and the low degree of freedom in space movement. Frequency defects and unpaired electrons are generated. However, according to the present invention, such defects and unpaired electrons are terminated by combining with oxygen. Generally, diffusion of oxygen SiO ₂ at a temperature of about 600 ° C. is very slow. In particular, since SiO ₂ obtained by oxidizing silicon is dense, if the film thickness is several tens of liters, the amount of oxygen supplied to the interface between Si and SiO ₂ (hereinafter referred to as the MOS interface) is considerably limited. Therefore, if a dense SiO ₂ film is formed on Si with a thickness of 1500 Å, almost no oxygen is supplied to the MOS interface by heat treatment at 600 ° C., 1 atmospheric pressure for more than 10 hours. However, in the fourth embodiment, the SiO ₂ film serving as the gate insulating film is formed by CVD.
Since it is a vacant film deposited by the method, oxygen is freely supplied up to a dense natural oxide film of less than several tens of liters formed on the Si surface. S is dense and has a small oxygen diffusion coefficient
600 due to the fact that the film thickness of io ₂ is less than several tens of liters
Oxygen is supplied to the MOS interface even at about 1 atm in temperature, and defects and unpaired electrons generated by crystal growth are effectively terminated. Further, S deposited by the CVD method or the like
An unreacted Si atom, Si-H group, Si-OH is formed on the iO ₂ film.
A lot of radicals and unpaired electrons remain. These unreacted substances become charges in SiO ₂ to increase the threshold voltage (Vth) of the transistor and increase the interface charge (Qss), which is a cause of not producing good characteristics. Further, since these unreacted substances are chemically unstable, when a thin film semiconductor device is produced, the stability over time of the semiconductor device is impaired. That is, compared to a dense and stable thermal oxide film, C
This is because the VDSiO ₂ film is inferior. However, in Example 4, simultaneously with the crystallization of the semiconductor film, the reaction of the gate oxide film with the oxygen heat treatment was promoted and the density was increased, thereby greatly improving the quality of the oxide film. Si-H was present in the oxide film by the heat treatment, Si-OH, Si-e -
Etc. are reacted with Si-O-Si and at the same time become dense. Actually, when the etching rate of SiO ₂ by a 1.67% hydrofluoric acid aqueous solution was examined, the thermal oxide film was found to be 1.
At 0Å / sec, the APCVD SiO ₂ film is 22Å / se
However, the etching rate of the present invention in which the APCVD film was heat-treated with oxygen was significantly improved to 4.3 Å / sec. Further, conventionally as shown in FIG. 5 when subjected to partial etching such as a contact hole opening with an aqueous solution of CVD SiO ₂ film or hydrofluoric acid based their film SiO ₂ film subjected to heat treatment in an inert atmosphere The reverse taper frequently occurred at the Si-SiO ₂ interface. This is Si
And SiO ₂ have poor adhesion, the etching solution is Si and S
It is based on rapid penetration into the interface of iO ₂ . On the other hand, the SiO ₂ film of the present invention subjected to the oxygen heat treatment promoted the reaction and improved the adhesion, so that the reverse taper did not occur,
It becomes a forward taper as shown in FIG. If a reverse taper is generated when the contact hole is opened, the wire is disconnected and electrical conduction cannot be established. Therefore, the forward taper is indispensable for stably manufacturing many thin film semiconductor devices.

【００６８】本実施例４では酸化性雰囲気の酸素分圧は
１気圧で有った。酸化性雰囲気を酸素に依り作り出す場
合、酸素分圧は０．０５気圧から５０気圧程度が好まし
い。より好ましくは０．１気圧から５気圧、更に好まし
くは０．５気圧から３気圧程度で有る。最適分圧は半導
体膜材質と熱処理温度に依って決定される。又、笑気ガ
ス（Ｎ₂Ｏ）や水（Ｈ₂Ｏ）を用いる場合はこれらのガス
分圧は０．０１気圧から１０気圧程度が好ましく、より
好ましくは０．０２気圧から１気圧、更に好ましくは
０．１気圧から０．６気圧程度で有る。又、熱処理温度
は５００℃から７００℃程度の間が使用される。結晶成
長をゆっくり大きくさせるとの観点からは低温の方が好
ましいが、結晶化に長時間費やす。本実施例４の様に６
００℃にて熱処理を施す場合は１０時間で結晶化はほぼ
完了するが、５５０℃とすると熱処理時間は１００時間
以上となり、又７００℃とすると１時間程度で済む。熱
処理温度はこうした長短より決められるが、好ましくは
５３０℃程度から６７０℃程度、更に好ましくは５５０
℃から６５０℃程度、より好ましくは５７０℃程度から
６３０℃程度で有る。In Example 4, the oxygen partial pressure of the oxidizing atmosphere was 1 atm. When an oxidizing atmosphere is created by oxygen, the oxygen partial pressure is preferably about 0.05 atm to 50 atm. The pressure is more preferably 0.1 atm to 5 atm, still more preferably 0.5 atm to 3 atm. The optimum partial pressure is determined depending on the semiconductor film material and the heat treatment temperature. When laughing gas (N ₂ O) or water (H ₂ O) is used, the partial pressure of these gases is preferably 0.01 atm to 10 atm, more preferably 0.02 atm to 1 atm. It is preferably about 0.1 to 0.6 atm. The heat treatment temperature is about 500 to 700 ° C. From the viewpoint of slowly increasing the crystal growth, a low temperature is preferable, but it takes a long time for crystallization. 6 as in the fourth embodiment
When heat treatment is performed at 00 ° C., crystallization is almost completed in 10 hours, but at 550 ° C., the heat treatment time is 100 hours or more, and at 700 ° C., it takes about 1 hour. The heat treatment temperature is determined depending on the length, but is preferably about 530 ° C to 670 ° C, more preferably 550 ° C.
C. to 650.degree. C., more preferably about 570.degree. C. to 630.degree.

【００６９】次にタンタルをスパッター法で堆積し、パ
ターニングに依り、ゲート電極３０６を形成した。本実
施例４ではゲート電極材料としてタンタルを用いたが、
無論これ以外の導電性物質も可能で有るし、又その形成
方法もスパッター法に限らず蒸着法やＣＶＤ法なども可
能で有る。ゲート電極作成後、ゲート電極をマスクとし
てドナー又はアクセプターとなる元素をイオン注入３０
７し、ソース・ドレイン領域３０８及びチャンネル領域
３０９を作成した（図３Ｃ）。本実施例４ではＮＭＯＳ
トランジスタ作成を目指し、水素希釈された５％フォス
フィンを質量非分離型イオン注入装置にて打ち込んだ。
加速電圧は１１０ｋｖで水素原子を含む総イオン打ち込
み量は１．０×１０¹⁶ｃｍ^-2で有った。続いてＡＰＣＶ
Ｄ法で層間絶縁膜３１０となるＳｉＯ₂膜を５０００Å
堆積した。この堆積は本実施例４で下地ＳｉＯ₂膜３０
２を堆積した条件と全く同一で唯一堆積時間のみを変え
て行った。層間絶縁膜形成後、注入イオンの活性化と層
間絶縁膜の焼き締めを兼ねて、窒素中で３００℃１時間
の熱処理を施した。熱処理後のソース・ドレイン領域の
シート抵抗値は９５％の信頼係数で（８０±１８）ｋΩ
／□で有った。本実施例４ではイオン注入を質量非分離
型イオン注入装置で行い、３００℃の低温熱処理に依り
注入イオンの活性化を行ったが、これに限らず例えば通
常の質量分離型イオン注入装置にてイオン注入し、レー
ザー照射に依り活性化しても良い。その後コンタクトホ
ールを開け、ソース・ドレイン取り出し電極３１１をス
パッター法などで形成し、トランジスタが完成する（図
３ｄ）。本実施例４ではソース・ドレイン取り出し電極
材料としてアルミニウムを用いスパッター法で８０００
Åの膜厚に堆積して、ソース・ドレイン取り出し電極を
形成した。この時堆積アルミニウム膜のシート抵抗は４
２．５±２．０ｍΩ／□で有った。Next, tantalum was deposited by the sputtering method, and the gate electrode 306 was formed by patterning. Although tantalum was used as the gate electrode material in Example 4,
Of course, other conductive materials are also possible, and the forming method is not limited to the sputtering method, and the vapor deposition method or the CVD method is also possible. After the gate electrode is formed, an element serving as a donor or an acceptor is ion-implanted using the gate electrode as a mask.
Then, the source / drain region 308 and the channel region 309 were formed (FIG. 3C). In the fourth embodiment, the NMOS
5% phosphine diluted with hydrogen was implanted with a mass non-separation type ion implanter for the purpose of forming a transistor.
The acceleration voltage was 110 kv, and the total ion implantation amount including hydrogen atoms was 1.0 × 10 ¹⁶ cm ^-2 . Then APCV
The SiO ₂ film to be the interlayer insulating film 310 is formed by the D method at 5000 Å
Deposited. This deposition is performed in the fourth embodiment by using the base SiO ₂ film 30.
The same conditions as those for depositing No. 2 were used, and only the deposition time was changed. After the formation of the interlayer insulating film, heat treatment was performed in nitrogen at 300 ° C. for 1 hour in order to activate the implanted ions and harden the interlayer insulating film. The sheet resistance value of the source / drain region after heat treatment is (80 ± 18) kΩ with 95% reliability coefficient.
It was / □. In the fourth embodiment, the ion implantation is performed by the mass non-separation type ion implantation apparatus and the implantation ions are activated by the low temperature heat treatment at 300 ° C. However, the present invention is not limited to this. Ions may be implanted and activated by laser irradiation. After that, contact holes are opened and source / drain extraction electrodes 311 are formed by a sputtering method or the like to complete a transistor (FIG. 3d). In the fourth embodiment, aluminum is used as the source / drain extraction electrode material and the sputtering method is performed at 8000.
The source / drain extraction electrodes were formed by depositing to a thickness of Å. At this time, the sheet resistance of the deposited aluminum film is 4
It was 2.5 ± 2.0 mΩ / □.

【００７０】この様にして試作した薄膜トランジスタ
（ＴＦＴ）の特性を温度２５℃で測定した。トランジス
タサイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１
０μｍで有った。ＳＰＣ膜中の欠陥や不対電子が終端さ
れ、更にゲート酸化膜質が改善された事実を反映して良
好なトランジスタ特性が得られた。実施例１に述べた発
明（図１のＡ）及び比較例（図１のＤ）と、実施例２
（図１−Ｂ）、実施例３（図１−Ｃ）のトランジスタ特
性と共に本実施例４の結果を表１にまとめる。The characteristics of the thin film transistor (TFT) manufactured in this manner were measured at a temperature of 25 ° C. Transistor size is channel length L = 10μm, width W = 1
It was 0 μm. Good transistor characteristics were obtained reflecting the fact that defects and unpaired electrons in the SPC film were terminated and the quality of the gate oxide film was further improved. The invention described in Example 1 (A in FIG. 1) and the comparative example (D in FIG. 1), and Example 2
(FIG. 1-B) and the transistor characteristics of Example 3 (FIG. 1-C) and the results of Example 4 are summarized in Table 1.

【００７１】[0071]

【表１】 [Table 1]

【００７２】従来技術の比較例と比べる迄もなく、高い
オン電流と低いオフ電流が実現されているのが分かる。
本発明が従来技術に比してソース・ドレイン領域のシー
ト抵抗を下げる原因も、優良な薄膜半導体装置を製造し
得る理由も、本発明に依り半導体膜中の欠陥が補修され
たり、不対電子が酸素で終端された為、電子等のキャリ
アの欠陥及び不対電子等との非弾性散乱が減った事や、
結晶粒界及び結晶粒内での捕獲準位数が減ったが故で有
る。加えてゲート絶縁膜の品質が上がった為、オン電流
が大きくなり同時に最小電流となるゲート電圧（Ｖｇｓ
ｍｉｎ）も０Ｖに近づき、急峻なスイッチング特性が
実現したので有る。同時に経時安定性も増し、ＳｉＯ₂
膜に開孔されたコンタクト・ホールの逆テーパーも解決
されたので有る。It can be seen that a high on-current and a low off-current are realized without much comparing with the comparative example of the prior art.
The reason why the present invention lowers the sheet resistance of the source / drain regions as compared with the prior art, and the reason why an excellent thin film semiconductor device can be manufactured, the defect in the semiconductor film is repaired by the present invention, and the unpaired electron Since oxygen is terminated with oxygen, the defects of carriers such as electrons and the inelastic scattering with unpaired electrons are reduced,
This is because the number of trap levels in the grain boundaries and crystal grains has decreased. In addition, since the quality of the gate insulating film is improved, the on-current increases, and at the same time, the gate voltage (Vgs
(min) also approaches 0 V, and a sharp switching characteristic is realized. At the same time, the stability over time increases and SiO ₂
The reverse taper of the contact hole formed in the film was also solved.

【００７３】この様に本発明に依り良質な半導体膜が得
られ、これらにドナー又はアクセプターとなる不純物を
添加すると低抵抗の電気伝導膜が得られ、又これらを能
動層半導体膜として用いると優良な薄膜半導体装置が得
られるので有る。As described above, according to the present invention, good-quality semiconductor films can be obtained, and by adding impurities serving as donors or acceptors to them, low-resistance electric conductive films can be obtained. Also, when these are used as active layer semiconductor films, they are excellent. That is, a thin film semiconductor device can be obtained.

【００７４】（実施例５）図４ａ〜ｄは本実施例５に於
ける自己整合型スタガード構造のＭＩＳ型電界効果トラ
ンジスタを構成するシリコン薄膜半導体装置の製造工程
を断面で示した図で有る。(Embodiment 5) FIGS. 4A to 4D are sectional views showing a manufacturing process of a silicon thin film semiconductor device which constitutes a MIS field effect transistor having a self-aligned staggered structure according to the present embodiment 5.

【００７５】本実施例５では、下地基板４０１として２
３５ｍｍ□の溶融石英ガラスを用いたが、６００℃の工
程最高温度に耐え得る基板又は下地物質で有るならば、
その種類や大きさは無論問われない。例えば通常ガラス
基板の他にシリコンウェハーなどの半導体基板及びそれ
らを加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン
・カーバイト、アルミナ、窒化アルミニウムなどのセラ
ミックス基板なども下地基板として可能で有る。In the fifth embodiment, as the base substrate 401, 2
35mm □ fused silica glass was used, but if it is a substrate or base material that can withstand the maximum process temperature of 600 ° C,
Of course, its kind and size are not questioned. For example, in addition to a glass substrate, a semiconductor substrate such as a silicon wafer, an LSI obtained by processing them, a three-dimensional LSI, or a ceramics substrate such as silicon carbide, alumina, or aluminum nitride can be used as the base substrate.

【００７６】まずアセトン又はメチル・エチル・ケト
ン，メチル・イソ・ブチル・ケトンやシクロヘキサノン
などの有機溶剤中に下地基板４０１を浸し、超音波洗浄
を行う。洗浄後窒素中又は減圧下にて乾燥を施し、更に
エタノールによる超音波洗浄を行った後窒素バブリング
されている純水にて水洗を施す。次に下地基板４０１を
沸騰している濃度６０％の硝酸中に５分間浸し、更に窒
素バブリングされている純水中で洗浄した。基板として
金属など酸に依り腐食されたり、変質して仕舞う物質を
用いる場合、この硝酸に依る洗浄は必要とされない。又
この強酸に依る洗浄では酸として硝酸の他に硫酸なども
可能で有る。First, the base substrate 401 is immersed in an organic solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone, and ultrasonic cleaning is performed. After cleaning, the product is dried in nitrogen or under reduced pressure, further ultrasonically cleaned with ethanol, and then rinsed with pure water with nitrogen bubbling. Next, the base substrate 401 was dipped in boiling nitric acid having a concentration of 60% for 5 minutes, and further washed in pure water with nitrogen bubbling. When a substance such as a metal that is corroded by acid or deteriorates and is used as a substrate is used, the cleaning by nitric acid is not required. In addition, in washing with this strong acid, sulfuric acid as well as nitric acid can be used as the acid.

【００７７】こうして洗浄された石英基板上に常圧気相
化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化
硅素膜（ＳｉＯ₂膜）４０２を２０００Å堆積した。こ
の下地ＳｉＯ₂膜４０２は前述の如き種々多様な物質を
基板として用いる際、後に堆積される半導体膜の膜質、
及びそれを用いて構成される薄膜トランジスタの性能を
安定化する為に必要で有る。と同時に、例えば基板４０
１として通常ガラスを用いた場合、ガラス中に含まれて
いるナトリウムなどの可動イオンが、又基板４０１とし
て各種セラミック板を用いた際には基板中に添加されて
いる焼結助材原料などがトランジスタ部に拡散混入する
のを防ぐ役割をも演じている。又金属板を基板４０１と
して用いる場合は、絶縁性を確保する為に下地ＳｉＯ₂
は必要不可欠で有る。又、三次元ＬＳＩ素子では、トラ
ンジスタ間や配線間の層間絶縁膜に相当している。下地
ＳｉＯ₂膜４０２堆積時の基板温度は３００℃で、窒素
に依り２０％に希釈されたシラン６００SCCMを８４０SC
CMの酸素と共にＡＰＣＶＤ法で堆積した。この時のＳｉ
Ｏ₂膜の堆積速度は３．９Å／ｓｅｃで有った。2000 Å of silicon dioxide film (SiO ₂ film) 402 as a base protection film was deposited on the thus cleaned quartz substrate by atmospheric pressure chemical vapor deposition (APCVD method). The base SiO ₂ film 402 is a film quality of a semiconductor film to be deposited later when various substances as described above are used as a substrate,
Also, it is necessary to stabilize the performance of the thin film transistor configured using the same. At the same time, for example, the substrate 40
When ordinary glass is used as 1, the mobile ions such as sodium contained in the glass are used, and when various ceramic plates are used as the substrate 401, the sintering aid raw material added to the substrate is It also plays a role in preventing diffusion and mixing in the transistor section. When a metal plate is used as the substrate 401, a base SiO ₂ film is used to ensure insulation.
Is indispensable. Also, in a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors and between wirings. The substrate temperature at the time of depositing the underlying SiO ₂ film 402 is 300 ° C., and 840 SC of silane 600 SCCM diluted to 20% with nitrogen
It was deposited by the APCVD method together with CM oxygen. Si at this time
The deposition rate of the O ₂ film was 3.9 Å / sec.

【００７８】次に減圧ＣＶＤ法でいずれ能動層となる非
晶質半導体膜を堆積した。本実施例５では半導体膜とし
てシリコンを用いたが、シリコン・ゲルマニウムやガリ
ウム・ヒ素等他の半導体も可能で有る。Next, an amorphous semiconductor film which will eventually become an active layer was deposited by a low pressure CVD method. Although silicon is used as the semiconductor film in the fifth embodiment, other semiconductors such as silicon-germanium and gallium-arsenic are also possible.

【００７９】半導体膜堆積に用いた減圧ＣＶＤ反応炉の
容積は１８４．５ｌで、基板は反応炉中央付近に水平に
置かれる。原料ガス及びヘリウム・窒素・アルゴン・水
素等の希釈ガスは必要に応じて反応炉下部より炉内に導
入され、反応炉上部から排気される。石英ガラスで作ら
れた反応炉の外側には３ゾーンに分かれたヒーターが設
置されて居り、それらを独立に調整する事で反応炉内中
央部付近に所望の温度で均熱帯を形成する。この均熱帯
は約３５０ｍｍの高さで広がり、その範囲内での温度の
ずれは、例えば５００℃に設定した時０．２℃以内であ
る。従って挿入基板間の間隔を５ｍｍとすれば１バッチ
で７０枚の基板の処理が可能で有る。本実施例５では２
０ｍｍ間隔で１７枚の基板を均熱帯内に設置した。The volume of the low pressure CVD reactor used for semiconductor film deposition was 184.5 l, and the substrate was placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, hydrogen, etc. are introduced into the furnace from the lower part of the reaction furnace and exhausted from the upper part of the reaction furnace as needed. Outside the reactor made of quartz glass, there are heaters divided into three zones, and by adjusting them independently, a soaking zone is formed near the center of the reactor at a desired temperature. This soaking zone spreads at a height of about 350 mm, and the temperature shift within that range is within 0.2 ° C. when set to 500 ° C., for example. Therefore, if the spacing between the inserted substrates is 5 mm, 70 substrates can be processed in one batch. In the fifth embodiment, 2
Seventeen substrates were placed in the soaking zone at 0 mm intervals.

【００８０】排気はロータリーポンプとメカニカル・ブ
ースターポンプを直結して行い、反応炉内の圧力は測定
値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バ
ラトロン・マノメーター）に依り測定した。反応炉を５
５０℃に保って、ガス導入用のバルブを閉じて両ポンプ
にて真空引きを行った場合、反応炉内圧は０mtorrで有
る為、背景真空度は悪くとも１０^-4torr程度以下で有
る。Exhaust was carried out by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reaction furnace was measured by a diaphragm pressure gauge (MKS Co. Baratron Manometer) whose measured value did not depend on the type of gas. 5 reactors
When the temperature is kept at 50 ° C., the gas introduction valve is closed, and both pumps are evacuated, the internal pressure of the reaction furnace is 0 mtorr, and therefore the background vacuum degree is at most 10 ⁻⁴ torr or less.

【００８１】半導体膜を堆積すべき基板は、表側を下向
きとして減圧ＣＶＤ炉内に挿入された。挿入時の反応炉
内温度は３９５℃から４００℃程度で有った。基板挿入
時に反応炉内には上部より純度が９９・９９９９％以上
の窒素と水素の混合気体が３０ＳＬＭ導入され、これら
の混合気体は反応炉下部に設けられた基板挿入口より排
出されて居る。基板挿入口の直径は５４０ｍｍでその断
面積は２２９０ｃｍ²で有る。混合気体が４００℃に熱
せられていると、基板挿入口からの混合気体の排出速度
は２９．６ｃｍ／ｍｉｎとなる。又、本実施例５の如く
２３５ｍｍ□の基板を水平に設置する場合、基板面積は
５５２ｃｍ²で有るから基板が基板挿入口より反応炉内
に入っていく時に基板挿入口と基板の隙間から排出され
る混合気体の排出速度は３９．０ｃｍ／ｍｉｎで有る。
本実施例５では５ｃｍ／ｍｉｎの上昇速度で基板を反応
炉に挿入したが、混合気体の排出速度の方が速い為、基
板挿入に伴う空気等の反応室への混入を防ぐ事が出来
る。又、混合気体の密度は空気密度よりも小さく、しか
も熱せられているので重い空気がこれらの軽い気体を押
し退けて下から上へ入る可能性は殆ど無い。本実施例５
で反応炉上部より導入した混合気体の濃度は窒素９７％
に水素３％で有った。水素の爆発下限界は４．０％なの
で、これ以下の濃度で有れば基板挿入口より室内に排出
されても安全で有る。こうした基板挿入方法を用いる事
に依り、ロードロック室を用いて１バッチ毎に真空引き
を行うといった煩雑な過程を経る事無くして、反応炉内
を清浄な非酸化性雰囲気下に保てられるので有る。基板
挿入時に空気や水等の不純物気体が反応炉内に流れ込む
と、これらは反応炉内壁の半導体層に吸着し、又は半導
体元素と反応して反応炉内に残留し、半導体膜堆積の
際、脱ガスとして現れ、堆積膜の膜品質を低下させる原
因となる。従って本発明の基板挿入を用いたＣＶＤ方法
では容易に高品質半導体膜が堆積されるので有る。The substrate on which the semiconductor film was to be deposited was inserted into a low pressure CVD furnace with the front side facing downward. The temperature inside the reaction furnace at the time of insertion was about 395 ° C to 400 ° C. At the time of inserting the substrate, 30 SLM of a mixed gas of nitrogen and hydrogen having a purity of 99.9999% or more was introduced into the reaction furnace from the upper part, and these mixed gases were discharged from the substrate insertion port provided in the lower part of the reaction furnace. The diameter of the substrate insertion port is 540 mm and its cross-sectional area is 2290 cm ² . When the mixed gas is heated to 400 ° C., the discharge rate of the mixed gas from the substrate insertion port becomes 29.6 cm / min. Further, when a 235 mm square substrate is installed horizontally as in the fifth embodiment, since the substrate area is 552 cm ² , the substrate is discharged from the gap between the substrate insertion port and the substrate when entering the reaction furnace from the substrate insertion port. The discharge rate of the mixed gas is 39.0 cm / min.
In Example 5, the substrate was inserted into the reaction furnace at a rising rate of 5 cm / min. However, since the mixed gas is discharged at a higher rate, it is possible to prevent air and the like from entering the reaction chamber when the substrate is inserted. Further, since the density of the mixed gas is smaller than that of the air and is heated, there is almost no possibility that the heavy air pushes these light gases and moves from the bottom to the top. Example 5
The concentration of the mixed gas introduced from above the reactor was 97% nitrogen.
Was 3% hydrogen. The lower limit of hydrogen explosion is 4.0%, so if the concentration is lower than this, it is safe to be discharged indoors from the substrate insertion port. By using such a substrate insertion method, the inside of the reaction furnace can be kept in a clean non-oxidizing atmosphere without a complicated process such as evacuation for each batch using a load lock chamber. There is. When an impurity gas such as air or water flows into the reaction furnace at the time of inserting the substrate, these are adsorbed to the semiconductor layer on the inner wall of the reaction furnace, or react with the semiconductor elements and remain in the reaction furnace. It appears as degassing and causes deterioration of the film quality of the deposited film. Therefore, a high-quality semiconductor film can be easily deposited by the CVD method using substrate insertion of the present invention.

【００８２】基板挿入後、真空引き、漏洩検査を施し
た。漏洩検査では反応炉に通ずる全バルブを閉じて反応
炉を完全に孤立させて、反応炉内圧力の変化を調べた。
本実施例５では反応炉内温度が４００℃で２分間の完全
孤立後、反応炉内圧力は１mtorr以下で有った。漏洩検
査にて異常が無い事を確認した後、反応炉内温度を挿入
温度の４００℃から堆積温度まで昇温する。本実施例５
では４９５℃でチャンネル部となる半導体膜を堆積した
為、昇温するのに一時間費やした。炉内温度が堆積温度
の４９５℃に達するには３５分間程度で済むが、反応炉
壁からの脱ガスを充分放出する為にも、最短一時間以
上、好ましくは数時間の昇温期間が望ましい。この昇温
期間中、二つのポンプは運転状態に有り、少なくとも純
度が９９．９９５％以上の不活性又は還元性ガスを流し
続ける。これらのガス種は水素・ヘリウム・窒素・ネオ
ン・アルゴン・キセノン・クリプトン等の純ガスの他、
これらのガスの混合ガスも可能で有る。本実施例５では
純度９９．９９９９％以上のヘリウムを３５０SCCM流し
続け、反応炉内圧力は８１±１．２mtorrで有った。After inserting the substrate, vacuuming and leakage inspection were performed. In the leak test, all the valves leading to the reactor were closed to completely isolate the reactor, and the change in pressure inside the reactor was examined.
In Example 5, after the reactor was completely isolated at 400 ° C. for 2 minutes, the reactor pressure was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature inside the reaction furnace is raised from the insertion temperature of 400 ° C. to the deposition temperature. Example 5
Then, since the semiconductor film to be the channel portion was deposited at 495 ° C., it took 1 hour to raise the temperature. It takes about 35 minutes for the temperature in the furnace to reach the deposition temperature of 495 ° C., but in order to sufficiently release the degas from the reaction furnace wall, a minimum heating time of 1 hour or more, preferably several hours is desirable. . During this temperature rising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995%. These gases are pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton,
A mixed gas of these gases is also possible. In Example 5, helium having a purity of 99.9999% or more was continuously flowed at 350 SCCM, and the pressure in the reaction furnace was 81 ± 1.2 mtorr.

【００８３】堆積温度到達後、原料ガスで有る所定量の
シラン又はシランと希釈ガスの混合ガスを反応炉内に導
入し、非晶質半導体膜を堆積する。希釈ガスとしては、
先の昇温期間に流したガスと同種の組み合わせが可能で
有るが、望ましくは各ガスの純度はそれぞれが９９．９
９９％以上が良い。本実施例５では希釈ガスを用いず、
純度９９．９９９％以上のシランを２００SCCM流して非
晶質半導体膜を堆積した。堆積時に於ける、反応炉内の
圧力は反応炉とメカニカル・ブースターポンプの間に設
置されたコンダクタンスバルヴの開閉度を調整して、
１．３torrに保った。本実施例５では非晶質半導体膜は
１６Å／ｍｉｎの堆積速度で３５０Åの膜厚に堆積し
た。After reaching the deposition temperature, a predetermined amount of silane, which is a source gas, or a mixed gas of silane and a diluent gas is introduced into the reaction furnace to deposit an amorphous semiconductor film. As a diluent gas,
It is possible to use the same kind of combination as the gas that was made to flow in the previous heating period, but it is desirable that the purity of each gas is 99.9.
99% or more is good. In Example 5, no diluent gas was used,
Silane having a purity of 99.999% or more was passed through 200 SCCM to deposit an amorphous semiconductor film. At the time of deposition, the pressure inside the reactor was adjusted by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump.
I kept it at 1.3 torr. In Example 5, the amorphous semiconductor film was deposited to a film thickness of 350Å at a deposition rate of 16Å / min.

【００８４】本実施例５では非晶質半導体膜の堆積をＬ
ＰＣＶＤ法で行い、原料ガスもモノシランを用いたが、
これ以外にもプラズマＣＶＤ法や光ＣＶＤ法、ＡＰＣＶ
Ｄ等の各種ＣＶＤ法やスパッター法、蒸着法等各種ＰＶ
Ｄ法等で堆積する事も可能で有る。又原料ガスもモノシ
ランに限らず、ジシランやトリシランなどの高次シラン
やジクロールシラン或いはゲルマンなども可能で有る。
又、無論上記種々のＣＶＤ法と上記種々の原料の組み合
わせに依って非晶質半導体膜を堆積する事も可能で有
る。In Example 5, the deposition of the amorphous semiconductor film was performed by L
Although the PCVD method was used and monosilane was used as the source gas,
Other than this, plasma CVD method, optical CVD method, APCV
Various PV such as various CVD methods such as D, sputtering method, vapor deposition method, etc.
It is also possible to deposit by the D method or the like. Further, the source gas is not limited to monosilane, but higher order silanes such as disilane and trisilane, dichlorsilane, or germane may be used.
Of course, it is also possible to deposit an amorphous semiconductor film by combining the various CVD methods described above and the various raw materials described above.

【００８５】こうして得られた非晶質半導体膜は、レジ
ストでパターニングされた後、四弗化炭素（ＣＦ₄）と
酸素（Ｏ₂）の混合プラズマに依りエッチングされ、い
ずれ能動層となる非晶質半導体膜４０３を形成した（図
４ａ）。本実施例５で形成した非晶質半導体膜はＣＦ₄
とＯ₂の比が５０SCCM対１００SCCMで有る１５Ｐａの真
空プラズマ放電で、その出力が７００Ｗの時のエッチン
グでは２．２Å／ｓｅｃのエッチング速度を有してい
た。The amorphous semiconductor film thus obtained is patterned with a resist and then etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to eventually become an amorphous layer which becomes an active layer. A quality semiconductor film 403 was formed (FIG. 4a). The amorphous semiconductor film formed in Example 5 is CF ₄
The etching rate was 2.2 Å / sec in the etching when the output was 700 W with the vacuum plasma discharge of 15 Pa in which the ratio of O ₂ and O ₂ was 50 SCCM to 100 SCCM.

【００８６】次にこの基板を沸騰している濃度６０％の
硝酸にて洗浄しＥＣＲ−ＰＥＣＶＤ法にてゲート絶縁膜
となる酸化膜４０４と窒化膜４０５及び酸化膜４０６を
総計で１５００Å堆積した。本実施例５では酸化膜４０
４としてはＳｉＯ₂膜を３００Å堆積し、窒化膜４０５
として窒化珪素膜（ＳｉＮ_X）を１０００Å連続堆積
し、更に酸化膜４０６としてＳｉＯ₂膜を２００Å堆積
した。ＥＣＲ−ＰＥＣＶＤ法にてゲート絶縁膜を堆積す
る時の基板温度は1００℃で三層の絶縁膜を連続堆積し
た。本実施例５ではＥＣＲ−ＰＥＣＶＤ法に依り原料ガ
スとしてモノシラン（ＳｉＨ₄）及び酸素（Ｏ₂）、窒素
（Ｎ₂）を用いたが、これ以外にも通常のＰＥＣＶＤ法
や光ＣＶＤ法等の各種ＣＶＤ法やスパッタ法等のＰＶＤ
法も有効で有る。又、原材料もモノシランに限らずジシ
ランやトリシランなどの高次シランやジクロールシラン
等の塩化シランやフッ化シラン等のハロゲン化物及びＴ
ＥＯＳ｛Ｓｉ−（ＣＨ₃−ＣＨ₂−Ｏ−）₄｝等の有機シ
リコン化合物も利用し得る。又、酸化剤や窒化剤として
も笑気ガス、水、二酸化炭素、ＮＯ_Xなどの窒素酸化物
やアンモニアなどが利用出来る。三層の絶縁膜堆積後酸
素イオン（¹⁶Ｏ⁺）を６５ｋｅＶの加速電圧で下側の酸
化膜４０４中に打ち込んだ（４０７）。この加速電圧に
於ける酸素イオンの飛程は１２５０Åで飛程偏差は３６
０Å程度で有る。従って注入イオンの大半は下側の酸化
膜４０４中に存在している。打ち込みイオン量は１×１
０¹⁴ｃｍ^-2で有った。次にこうして得られた基板を洗浄
し、熱処理を施した。この熱処理により非晶質半導体膜
４０３は結晶化半導体膜４０８へと固相状態を変える。
（図４−ｂ）。本実施例５では酸化性雰囲気下で熱処理
を施した。これは上側の酸化膜４０６を実施例４で詳述
した様に改善する為で有るが、上側酸化膜４０６の品質
はＭＯＳ界面を形成する下側酸化膜４０４ほど重要では
ないので、この熱処理雰囲気は特に酸化性に限られる事
無く、製造上の都合に応じて自由に設定し得る。Next, this substrate was washed with boiling nitric acid having a concentration of 60%, and an oxide film 404, a nitride film 405 and an oxide film 406 serving as a gate insulating film were deposited in a total amount of 1500 liters by the ECR-PECVD method. In the fifth embodiment, the oxide film 40
As No. 4, a SiO ₂ film was deposited to 300 Å and a nitride film 405
A silicon nitride film (SiN _x ) was continuously deposited as 1000 Å, and an SiO ₂ film was further deposited as 200 Å as an oxide film 406. The substrate temperature at the time of depositing the gate insulating film by the ECR-PECVD method was 100 ° C., and three layers of insulating films were continuously deposited. In Example 5, monosilane (SiH ₄ ), oxygen (O ₂ ), and nitrogen (N ₂ ) were used as the raw material gas according to the ECR-PECVD method. PVD such as various CVD methods and sputtering methods
The law is also valid. The raw materials are not limited to monosilane, but higher order silanes such as disilane and trisilane, chloride silanes such as dichlorosilane, and halides such as fluorinated silane and T
Organosilicon compounds such as _{EOS {Si- (CH 3 -CH 2} -O-) 4} it may also be utilized. Further, nitrous oxide as an oxidant and nitriding agent, water, carbon dioxide, such as nitrogen oxides and ammonia, such as NO _X is available. After depositing the three-layer insulating film, oxygen ions ( ¹⁶ O ⁺ ) were implanted into the lower oxide film 404 at an acceleration voltage of 65 keV (407). The range of oxygen ions at this accelerating voltage is 1250Å and the range deviation is 36.
It is about 0Å. Therefore, most of the implanted ions are present in the lower oxide film 404. Implanted ion amount is 1 x 1
It was 0 ¹⁴ cm ^-2 . Next, the substrate thus obtained was washed and heat-treated. By this heat treatment, the amorphous semiconductor film 403 changes into a crystallized semiconductor film 408 in a solid state.
(Fig. 4-b). In Example 5, the heat treatment was performed in an oxidizing atmosphere. This is to improve the upper oxide film 406 as described in detail in the fourth embodiment. However, since the quality of the upper oxide film 406 is not as important as that of the lower oxide film 404 forming the MOS interface, this heat treatment atmosphere Is not particularly limited to oxidative property, and can be freely set according to manufacturing convenience.

【００８７】熱処理炉は縦型炉で通常４００℃に保たれ
て居り、純度９９．９９９％以上の酸素を３０SLM流し
続けて熱処理炉内部を酸化性雰囲気としている。従って
熱処理炉内の酸素分圧はおよそ１気圧となる。熱処理炉
の容積は１８４．５ｌで有る。基板は縦型炉下部より熱
処理炉内に挿入されるが、酸素は熱処理炉上部より炉内
に導入され下部の挿入口より流出している。室温と温度
平衡に達している基板は酸化性雰囲気で４００℃の炉に
挿入された。基板挿入後熱処理炉の温度を一時間かけて
６００℃まで上げ、その後６００℃にて１５時間維持し
た。この熱処理に依り非晶質半導体膜は結晶化して多結
晶半導体膜へと固体状態を変える。同時に下側酸化膜４
０４に注入された酸素イオンは下側酸化膜の未反応物の
酸化を促進し、下側酸化膜４０４の膜質及びＭＯＳ界面
を改善する。更に非晶質膜を構成していた半導体元素が
多結晶状態へと移動すると原子密度の減少及び空間移動
に関する自由度の低さに起因して、出来上がった多結晶
粒内部には必然的におびただしき数の欠陥や不対電子が
発生するが、化学的に活性な注入酸素イオンがＭＯＳ界
面及び結晶化半導体膜中に拡散して、この様な欠陥及び
不対電子と結合し、終端させるので有る。ＭＯＳ界面近
傍の半導体膜中に存在する欠陥や不対電子の濃度は１×
１０¹⁷ｃｍ^-3から１×１０¹⁹ｃｍ^-3程度で有る。本実施
例５では打ち込み量が１×１０¹⁴ｃｍ^-2で飛程偏差が３
６０Å程度で有るから、注入イオン濃度は１．４×１０
¹⁹ｃｍ^-3程度となりＳｉＯ₂中の未反応物の反応を促進
したり、結晶化半導体膜中の欠陥補正するには十分で有
る。酸素イオンは注入量が少なすぎると欠陥修復を十分
に行えず、反対に多すぎると余分な酸化膜を形成した
り、酸素原子が半導体膜内部にまで取り込まれて半導体
膜品質を劣化させてしまう。従って最適注入量は注入後
の濃度が１×１０¹⁷ｃｍ^-3から１×１０²⁰ｃｍ^-3、好ま
しくは１×１０¹⁸ｃｍ^-3から５×１０¹⁹ｃｍ^-3、更に好
ましくは５×１０¹⁸ｃｍ^-3から２×１０¹⁹ｃｍ^-3となる
もので有る。通常窒化膜４０５中の酸素拡散は非常に遅
いので注入酸素原子は酸化膜中から半導体膜方向へのみ
拡散するので効果的に酸素を供給し得る。又、供給源が
酸化膜中に有って半導体膜中にないので、酸素が不必要
に半導体膜中に取り込まれる事がない。酸素イオンが酸
化膜中から拡散に依ってＭＯＳ界面や半導体膜に達する
にはある程度の時間が必要で、この間に半導体原子の再
配例、即ち結晶化が生ずるので、結晶化を妨げる事無く
欠陥補修がなされるので有る。熱処理温度は５００℃か
ら７００℃程度の間が使用される。結晶成長をゆっくり
大きくさせるとの観点からは低温の方が好ましいが、結
晶化に長時間費やす。本実施例５の様に６００℃にて熱
処理を施す場合は１０時間で結晶化はほぼ完了するが、
５５０℃とすると熱処理時間は１００時間以上となり、
又７００℃とすると１時間程度で済む。熱処理温度はこ
うした長短より決められるが、好ましくは５３０℃程度
から６７０℃程度、更に好ましくは５５０℃から６５０
℃程度、より好ましくは５７０℃程度から６３０℃程度
で有る。The heat treatment furnace is a vertical furnace, which is usually kept at 400 ° C., and oxygen having a purity of 99.999% or more is continuously flowed at 30 SLM to make the inside of the heat treatment furnace an oxidizing atmosphere. Therefore, the oxygen partial pressure in the heat treatment furnace is about 1 atm. The volume of the heat treatment furnace is 184.5 l. The substrate is inserted into the heat treatment furnace from the lower part of the vertical furnace, but oxygen is introduced into the furnace from the upper part of the heat treatment furnace and flows out from the lower insertion port. The substrate that had reached temperature equilibrium with room temperature was placed in a furnace at 400 ° C. in an oxidizing atmosphere. After inserting the substrate, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained at 600 ° C. for 15 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change its solid state into a polycrystalline semiconductor film. At the same time lower oxide film 4
The oxygen ions implanted in 04 promote the oxidation of unreacted substances in the lower oxide film, and improve the film quality of the lower oxide film 404 and the MOS interface. Furthermore, when the semiconductor element that constitutes the amorphous film moves to the polycrystalline state, the atomic density is reduced and the degree of freedom in space movement is low, so that the inside of the finished polycrystalline grain is inevitably affected. However, a certain number of defects and unpaired electrons are generated, but chemically active implanted oxygen ions diffuse into the MOS interface and into the crystallized semiconductor film, combine with such defects and unpaired electrons, and terminate. Because it is. The concentration of defects and unpaired electrons existing in the semiconductor film near the MOS interface is 1 ×
It is about 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . In Example 5, the driving amount was 1 × 10 ¹⁴ cm ⁻² and the range deviation was 3
Since it is about 60Å, the concentration of implanted ions is 1.4 × 10.
^{It is} about ¹⁹ cm ^−3, which is sufficient for accelerating the reaction of unreacted substances in SiO ₂ and correcting defects in the crystallized semiconductor film. If the implantation amount of oxygen ions is too small, the defect cannot be sufficiently repaired. On the contrary, if the implantation amount is too large, an extra oxide film is formed or oxygen atoms are taken into the inside of the semiconductor film to deteriorate the quality of the semiconductor film. . Therefore, the optimum injection amount is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , preferably 1 × 10 ¹⁸ cm ⁻³ to 5 × 10 ¹⁹ cm ⁻³ , more preferably 5 × 10 5 after injection. ^{It is from 18} cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . Normally, oxygen diffusion in the nitride film 405 is very slow, and the implanted oxygen atoms diffuse only from the oxide film toward the semiconductor film, so that oxygen can be effectively supplied. Further, since the supply source is in the oxide film and not in the semiconductor film, oxygen is not unnecessarily taken into the semiconductor film. It takes a certain amount of time for oxygen ions to reach the MOS interface or the semiconductor film from the oxide film due to diffusion. During this time, semiconductor atoms are rearranged, that is, crystallization occurs, so that defects do not interfere with crystallization. Yes, because it will be repaired. The heat treatment temperature is about 500 to 700 ° C. From the viewpoint of slowly increasing the crystal growth, a low temperature is preferable, but it takes a long time for crystallization. When heat treatment is performed at 600 ° C. as in this Example 5, crystallization is almost completed in 10 hours,
At 550 ° C, the heat treatment time is 100 hours or more,
If the temperature is 700 ° C., it takes about 1 hour. The heat treatment temperature is determined depending on the length, but is preferably about 530 ° C to 670 ° C, more preferably 550 ° C to 650 ° C.
C., and more preferably about 570 to 630.degree.

【００８８】次にタンタルをスパッター法で堆積し、パ
ターニングに依り、ゲート電極４０９を形成した。本実
施例５ではゲート電極材料としてタンタルを用いたが、
無論これ以外の導電性物質も可能で有るし、又その形成
方法もスパッター法に限らず蒸着法やＣＶＤ法なども可
能で有る。ゲート電極作成後、ゲート電極をマスクとし
てドナー又はアクセプターとなる元素をイオン注入４１
０し、ソース・ドレイン領域４１１及びチャンネル領域
４１２を作成した（図４Ｃ）。本実施例５ではＮＭＯＳ
トランジスタ作成を目指し、水素希釈された５％フォス
フィンを質量非分離型イオン注入装置にて打ち込んだ。
加速電圧は１１０ｋｖで水素原子を含む総イオン打ち込
み量は１．０×１０¹⁶ｃｍ^-2で有った。続いてＡＰＣＶ
Ｄ法で層間絶縁膜４１３となるＳｉＯ₂膜を５０００Å
堆積した。この堆積は本実施例５で下地ＳｉＯ₂膜４０
２を堆積した条件と全く同一で唯一堆積時間のみを変え
て行った。層間絶縁膜形成後、注入イオンの活性化と層
間絶縁膜の焼き締めを兼ねて、窒素中で３００℃１時間
の熱処理を施した。熱処理後のソース・ドレイン領域の
シート抵抗値は９５％の信頼係数で（５６±１２）ｋΩ
／□で有った。本実施例５ではイオン注入を質量非分離
型イオン注入装置で行い、３００℃の低温熱処理に依り
注入イオンの活性化を行ったが、これに限らず例えば通
常の質量分離型イオン注入装置にてイオン注入し、レー
ザー照射に依り活性化しても良い。その後コンタクトホ
ールを開け、ソース・ドレイン取り出し電極４１４をス
パッター法などで形成し、トランジスタが完成する（図
４ｄ）。本実施例５ではソース・ドレイン取り出し電極
材料としてアルミニウムを用いスパッター法で８０００
Åの膜厚に堆積して、ソース・ドレイン取り出し電極を
形成した。この時堆積アルミニウム膜のシート抵抗は４
２．５±２．０ｍΩ／□で有った。Next, tantalum was deposited by a sputtering method, and a gate electrode 409 was formed by patterning. In Example 5, tantalum was used as the gate electrode material,
Of course, other conductive materials are also possible, and the forming method is not limited to the sputtering method, and the vapor deposition method or the CVD method is also possible. After the gate electrode is formed, an element serving as a donor or an acceptor is ion-implanted 41 using the gate electrode as a mask.
Then, the source / drain region 411 and the channel region 412 were formed (FIG. 4C). In the fifth embodiment, the NMOS
5% phosphine diluted with hydrogen was implanted with a mass non-separation type ion implanter for the purpose of forming a transistor.
The acceleration voltage was 110 kv, and the total ion implantation amount including hydrogen atoms was 1.0 × 10 ¹⁶ cm ^-2 . Then APCV
The SiO ₂ film to be the interlayer insulating film 413 was formed by the D method at 5000 Å
Deposited. This deposition is performed by the base SiO ₂ film 40 in the fifth embodiment.
The same conditions as those for depositing No. 2 were used, and only the deposition time was changed. After the formation of the interlayer insulating film, heat treatment was performed in nitrogen at 300 ° C. for 1 hour in order to activate the implanted ions and harden the interlayer insulating film. The sheet resistance value of the source / drain region after heat treatment is (56 ± 12) kΩ with 95% reliability coefficient.
It was / □. In Example 5, the ion implantation was performed by the mass non-separation type ion implantation apparatus and the implantation ions were activated by the low temperature heat treatment at 300 ° C. However, the present invention is not limited to this. Ions may be implanted and activated by laser irradiation. After that, contact holes are opened, and source / drain extraction electrodes 414 are formed by a sputtering method or the like to complete the transistor (FIG. 4d). In the fifth embodiment, aluminum is used as the source / drain extraction electrode material and the sputtering method is performed at 8000.
The source / drain extraction electrodes were formed by depositing to a thickness of Å. At this time, the sheet resistance of the deposited aluminum film is 4
It was 2.5 ± 2.0 mΩ / □.

【００８９】この様にして試作した薄膜トランジスタ
（ＴＦＴ）の特性を温度２５℃で測定した。トランジス
タサイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１
０μｍで有った。ＳＰＣ膜中の欠陥や不対電子が酸素イ
オンで終端された事、下側ゲート酸化膜４０４の膜品質
が酸素イオン注入とその後の熱処理で改善された事、上
側ゲート酸化膜４０６が酸化性雰囲気下の熱処理で改善
された事、及びゲート絶縁膜の中間層に誘電率の大きな
窒化珪素膜を用いた事により、トランジスタ特性は大幅
に向上した。実際オン電流（Ｖｄｓ＝４Ｖ、Ｖｇｓ＝１
５Ｖ）は４．３×１０^-5Ａと従来の比較例の３倍程度に
も増大し、Ｉｄｓの最小値もゲート電圧が０Ｖの時とな
り、その値（ＩOFF：Ｖｄｓ＝４Ｖ、Ｖｇｓ＝０Ｖ）も
８．９×１０^-14と良好な値を示した。この結果ゲート
電圧１５Ｖの変調に対するオン・オフ比は８．７桁にも
達する優れたスイッチング特性を有する薄膜半導体装置
が実現された。The characteristics of the thin film transistor (TFT) manufactured as described above were measured at a temperature of 25 ° C. Transistor size is channel length L = 10μm, width W = 1
It was 0 μm. Defects and unpaired electrons in the SPC film were terminated by oxygen ions, the film quality of the lower gate oxide film 404 was improved by oxygen ion implantation and subsequent heat treatment, and the upper gate oxide film 406 was in an oxidizing atmosphere. The transistor characteristics were significantly improved due to the improvement by the heat treatment below and the use of the silicon nitride film having a large dielectric constant as the intermediate layer of the gate insulating film. Actual ON current (Vds = 4V, Vgs = 1
5V) is 4.3 × 10 ⁻⁵ A, which is about three times as large as that of the conventional comparative example, and the minimum value of Ids is also when the gate voltage is 0V, and the values (IOFF: Vds = 4V, Vgs = 0V). ) Also showed a good value of 8.9 × 10 ^-14 . As a result, a thin film semiconductor device having an excellent switching characteristic with an on / off ratio for modulation of a gate voltage of 15 V reaching 8.7 digits was realized.

【００９０】尚、本実施例５では下側ゲート酸化膜をＣ
ＶＤ法で堆積して形成したが、酸素イオン注入法及びそ
の後の熱処理で形成する事もできる。この場合、まず非
晶質半導体膜４０３を６００Å程度堆積し、パターニン
グを行う。次いで窒化珪素膜４０５を１０００Å程度と
連続して上側酸化珪素膜４０６を２００Å程度堆積した
後、非晶質半導体膜と窒化珪素膜の界面に酸素イオンを
打ち込む。打ち込み量は下側酸化膜４０４が３００Å程
度形成される量で界面よりも窒化膜側に飛程中心が来る
様にする。例えば酸素イオンを５５ｋｅＶの加速電圧で
打ち込むと、その飛程と飛程偏差はそれぞれ１０７５Å
と３２５Å程度で有る。従って飛程中心は界面から１２
５Å程窒化膜側に出来、酸素イオンは非晶質半導体膜表
面２００Å程度内に分布する。打ち込み量を６．５×１
０¹⁷ｃｍ^-2とし、その後熱処理する事で半導体膜表面に
は３００Å程度の下側酸化膜４０４が形成され、結晶化
半導体膜４０８の膜厚は４００Å程度となる。この熱処
理も６００℃程度で十数時間程度との前述の熱処理と同
じで構わない。以下本実施例５と同じ工程で薄膜半導体
装置を作成する。本実施例５では下側酸化膜４０４と窒
化膜４０５、上側酸化膜４０６を連続成膜したが、これ
らの膜を別装置で形成しても良い。その場合、この方法
を用いると下側酸化膜４０４の堆積を行わなくて良い分
だけ工程は簡略化されるので有る。In the fifth embodiment, the lower gate oxide film is C
Although it is formed by depositing by the VD method, it may be formed by the oxygen ion implantation method and the subsequent heat treatment. In this case, first, the amorphous semiconductor film 403 is deposited to about 600 Å and patterned. Next, after depositing the upper silicon oxide film 406 at a thickness of about 200 Å continuously with the silicon nitride film 405 at a thickness of about 1000 Å, oxygen ions are implanted into the interface between the amorphous semiconductor film and the silicon nitride film. The implantation amount is such that the lower oxide film 404 is formed to about 300 Å so that the range center is closer to the nitride film than the interface. For example, when oxygen ions are implanted at an acceleration voltage of 55 keV, the range and range deviation are 1075Å
And about 325Å. Therefore, the range center is 12 from the interface.
About 5Å is formed on the side of the nitride film, and oxygen ions are distributed within about 200Å of the surface of the amorphous semiconductor film. The driving amount is 6.5 x 1
The lower oxide film 404 of about 300 Å is formed on the surface of the semiconductor film by heat treatment at 0 ¹⁷ cm ^-2, and the film thickness of the crystallized semiconductor film 408 is about 400 Å. This heat treatment may be the same as the above-mentioned heat treatment of about 600 ° C. and about a dozen hours. Hereinafter, a thin film semiconductor device is manufactured through the same steps as in the fifth embodiment. Although the lower oxide film 404, the nitride film 405, and the upper oxide film 406 are continuously formed in the fifth embodiment, these films may be formed by another device. In this case, the use of this method simplifies the process because the lower oxide film 404 need not be deposited.

【００９１】この様に本発明に依り良質な半導体膜とＭ
ＯＳ界面及びゲート絶縁膜が得られ、これらにドナー又
はアクセプターとなる不純物を添加すると低抵抗の電気
伝導膜が得られ、又これらを能動層半導体膜として用い
ると優良な薄膜半導体装置が得られるので有る。As described above, according to the present invention, a high-quality semiconductor film and M
Since an OS interface and a gate insulating film are obtained, and an impurity serving as a donor or an acceptor is added thereto, a low resistance electric conductive film is obtained, and when these are used as an active layer semiconductor film, a good thin film semiconductor device is obtained. There is.

【００９２】[0092]

【発明の効果】以上述べて来た様に、本発明に依れば、
良質な半導体膜をＥＣＲ−ＰＥＣＶＤ装置等の高価で面
倒な装置を用いる事無く、通常の簡単な装置でしかも水
素化処理を施す事無く簡単に得る事が可能になった。こ
れに依り、優良なトランジスタ特性を有する薄膜半導体
装置を大面積に均一に簡便な手法にて形成する事が可能
となり、ＬＳＩの多層化や薄膜トランジスタを用いたア
クティブマトリックス液晶ディスプレイの高性能化や低
価格化を実現すると言う多大な効果を有する。As described above, according to the present invention,
It has become possible to easily obtain a high-quality semiconductor film by using an ordinary simple device without using an expensive and cumbersome device such as an ECR-PECVD device and without performing a hydrogenation process. As a result, it becomes possible to form a thin film semiconductor device having excellent transistor characteristics uniformly in a large area by a simple method, and to increase the performance of an active matrix liquid crystal display using a multi-layered LSI or a thin film transistor It has a great effect of realizing price reduction.

【００９３】又、本発明に依り、ロードロック室を用い
なくとも熱処理炉内やＣＶＤ装置を清浄に保つ事が可能
となり、良質な膜作成等を極めて簡単に行える様になっ
た。これに依りやはりＬＳＩや液晶ディスプレイ等の高
性能化や低価額化を実現すると言う多大な効果を有す
る。Further, according to the present invention, it is possible to keep the inside of the heat treatment furnace and the CVD apparatus clean without using the load lock chamber, and it has become possible to easily form a high quality film. This has a great effect of realizing high performance and low price of LSIs and liquid crystal displays.

【００９４】更に本発明により良質な半導体膜とＭＯＳ
界面及びゲート絶縁膜が形成され、きわめて優良なトラ
ンジスタ特性を有する薄膜半導体装置を大面積に形成す
る事が可能となり、液晶ディスプレイ等の高性能化や低
価額化を実現するという多大な効果を有する。Further, according to the present invention, a good quality semiconductor film and MOS
Since the interface and the gate insulating film are formed, it is possible to form a thin film semiconductor device having extremely excellent transistor characteristics in a large area, which has a great effect of realizing high performance and low cost of a liquid crystal display or the like. .

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の効果を示す図。FIG. 1 is a diagram showing an effect of the present invention.

【図２】 本発明の一実施例を示すシリコン薄膜半導体
装置製造の各工程に於ける素子断面図。FIG. 2 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

【図３】 本発明の一実施例を示すシリコン薄膜半導体
装置製造の各工程に於ける素子断面図。FIG. 3 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

【図４】 本発明の一実施例を示すシリコン薄膜半導体
装置製造の各工程に於ける素子断面図。FIG. 4 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

【図５】 エッチングの逆テーパーを説明する図。FIG. 5 is a diagram illustrating an inverse taper of etching.

【図６】 エッチングの順テーパーを説明する図。FIG. 6 is a diagram illustrating a forward taper of etching.

【符号の説明】[Explanation of symbols]

２０１…下地基板 ２０２…下地保護膜 ２０３…半導体膜 ２０４…ゲート絶縁膜 ２０５…ゲート電極 ２０６…イオン注入 ２０７…ソース・ドレイン領域 ２０８…チャンネル領域 ２０９…層間絶縁膜 ２１０…ソース・ドレイン取り出し電極 ３０１…下地基板 ３０２…下地保護膜 ３０３…非晶質半導体膜 ３０４…ゲート絶縁膜 ３０５…結晶化半導体膜 ３０６…ゲート電極 ３０７…イオン注入 ３０８…ソース・ドレイン領域 ３０９…チャンネル領域 ３１０…層間絶縁膜 ３１１…ソース・ドレイン取り出し電極 ４０１…下地基板 ４０２…下地保護膜 ４０３…非晶質半導体膜 ４０４…酸化膜 ４０５…窒化膜 ４０６…酸化膜 ４０７…酸素イオン注入 ４０８…結晶化半導体膜 ４０９…ゲート電極 ４１０…イオン注入 ４１１…ソース・ドレイン領域 ４１２…チャンネル領域 ４１３…層間絶縁膜 ４１４…ソース・ドレイン取り出し電極 201 ... Base substrate 202 ... Base protective film 203 ... Semiconductor film 204 ... Gate insulating film 205 ... Gate electrode 206 ... Ion implantation 207 ... Source / drain regions 208 ... Channel area 209 ... Interlayer insulating film 210 ... Source / drain extraction electrodes 301 ... Base substrate 302 ... Base protection film 303 ... Amorphous semiconductor film 304 ... Gate insulating film 305 ... Crystallized semiconductor film 306 ... Gate electrode 307 ... Ion implantation 308 ... Source / drain regions 309 ... Channel area 310 ... Interlayer insulating film 311 ... Source / drain extraction electrodes 401 ... Base substrate 402 ... Base protection film 403 ... Amorphous semiconductor film 404 ... Oxide film 405 ... Nitride film 406 ... Oxide film 407 ... Oxygen ion implantation 408 ... Crystallized semiconductor film 409 ... Gate electrode 410 ... Ion implantation 411 ... Source / drain region 412 ... Channel area 413 ... Interlayer insulating film 414 ... Source / drain extraction electrode

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.⁷，ＤＢ名) H01L 21/205 H01L 21/20 H01L 21/324 H01L 21/336 H01L 29/786 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/205 H01L 21/20 H01L 21/324 H01L 21/336 H01L 29/786

Claims (22)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】少なくとも表面が絶縁性物質で有る基板上
に結晶性半導体膜を形成する半導体膜形成方法であっ
て、 前記基板上に非晶質半導体膜を形成する第一の工程と、 前記非晶質半導体膜が形成された基板を不活性雰囲気下
にて熱処理し、連続して酸化性雰囲気下において熱処理
することにより、前記非晶質半導体膜を結晶化して前記
結晶性半導体膜とする第二の工程と、 を含む事を特徴とする半導体膜形成方法。1. A semiconductor film forming method for forming a crystalline semiconductor film on a substrate, at least the surface of which is an insulating material, comprising: a first step of forming an amorphous semiconductor film on the substrate; The amorphous semiconductor film is crystallized into the crystalline semiconductor film by heat-treating the substrate on which the amorphous semiconductor film is formed in an inert atmosphere and continuously heat-treating it in an oxidizing atmosphere. A method for forming a semiconductor film, comprising: a second step. 【請求項２】少なくとも表面が絶縁性物質で有る基板上
に結晶性半導体膜を形成する半導体膜形成方法であっ
て、 前記絶縁性物質上に非晶質半導体膜を形成する第一の工
程と、 前記非晶質半導体膜が形成された基板を還元性雰囲気下
にて熱処理した後、連続して酸化性雰囲気下において熱
処理することにより、前記非晶質半導体膜を結晶化して
前記結晶性半導体膜とする第二の工程と、 を含む事を特徴とする半導体膜形成方法。2. A semiconductor film forming method for forming a crystalline semiconductor film on a substrate having at least a surface made of an insulating material, comprising: a first step of forming an amorphous semiconductor film on the insulating material. After the substrate on which the amorphous semiconductor film is formed is heat-treated in a reducing atmosphere, the amorphous semiconductor film is crystallized by continuously heat-treating it in an oxidizing atmosphere. A method of forming a semiconductor film, comprising: a second step of forming a film. 【請求項３】請求項２に記載の半導体膜形成方法におい
て、 前記還元性雰囲気は水素に依り作り出され、前記還元性
雰囲気における水素分圧は０．１ mtorrから１０気圧の
範囲である事を特徴とする半導体膜形成方法。3. The method for forming a semiconductor film according to claim 2, wherein the reducing atmosphere is created by hydrogen, and the hydrogen partial pressure in the reducing atmosphere is in the range of 0.1 mtorr to 10 atmospheres. A characteristic method for forming a semiconductor film. 【請求項４】請求項２または３に記載の半導体膜形成方
法において、 前記酸化性雰囲気は酸素に依り作り出され、前記酸化性
雰囲気における酸素分圧は０．１気圧から１０気圧の範
囲である事を特徴とする半導体膜形成方法。4. The method of forming a semiconductor film according to claim 2, wherein the oxidizing atmosphere is created by oxygen, and the oxygen partial pressure in the oxidizing atmosphere is in the range of 0.1 atm to 10 atm. A method for forming a semiconductor film, characterized by the above. 【請求項５】請求項１乃至４のいずれかに記載の半導体
膜形成方法において、 前記結晶性半導体膜を構成する元素にシリコンを含む事
を特徴とする半導体膜形成方法。5. The method of forming a semiconductor film according to claim 1, wherein the element forming the crystalline semiconductor film contains silicon. 【請求項６】少なくとも表面が絶縁性物質で有る基板上
にシリコン膜を形成する半導体膜形成方法であって、 前記絶縁性物質上に非晶質シリコン膜を形成する第一の
工程と、 前記非晶質シリコン膜が形成された基板を不活性雰囲気
下にて熱処理した後、連続して酸化性雰囲気下にて熱処
理する第二の工程と、 を含む事を特徴とする半導体膜形成方法。6. A method for forming a semiconductor film, comprising forming a silicon film on a substrate having at least a surface made of an insulating material, comprising: a first step of forming an amorphous silicon film on the insulating material; A semiconductor film forming method comprising: a second step of heat-treating a substrate on which an amorphous silicon film is formed in an inert atmosphere, and then continuously performing heat treatment in an oxidizing atmosphere. 【請求項７】少なくとも表面が絶縁性物質で有る基板上
にシリコン膜を形成する半導体膜形成方法であって、 前記絶縁性物質上に非晶質シリコン膜を形成する第一の
工程と、 前記非晶質シリコン膜が形成された基板を還元性雰囲気
下にて熱処理した後、連続して酸化性雰囲気下にて熱処
理する第二の工程と、 を含む事を特徴とする半導体膜形成方法。7. A method for forming a semiconductor film, comprising forming a silicon film on a substrate having at least a surface made of an insulating material, comprising: a first step of forming an amorphous silicon film on the insulating material; A semiconductor film forming method comprising: a second step of heat-treating a substrate on which an amorphous silicon film is formed in a reducing atmosphere, and then continuously heat-treating in an oxidizing atmosphere. 【請求項８】請求項１乃至７のいずれかに記載の半導体
膜形成方法を用いて製造された事を特徴とする半導体装
置。8. A semiconductor device manufactured by using the method for forming a semiconductor film according to claim 1. Description: 【請求項９】絶縁性物質上に非晶質半導体膜を形成する
第一の工程と、 前記非晶質半導体膜が形成された基板を不活性雰囲気下
にて熱処理した後、連続して酸化性雰囲気下において熱
処理することにより、前記非晶質半導体膜を結晶化して
結晶性半導体膜を形成する第二の工程と、 を含む事を特徴とする半導体装置の製造方法。9. A first step of forming an amorphous semiconductor film on an insulating material, the substrate on which the amorphous semiconductor film is formed is heat-treated in an inert atmosphere, and then continuously oxidized. A second step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film by performing heat treatment in a strong atmosphere. 2. A method of manufacturing a semiconductor device, comprising: 【請求項１０】絶縁性物質上に非晶質半導体膜を形成す
る第一の工程と、 前記非晶質半導体膜が形成された基板を還元性雰囲気下
にて熱処理した後、連続して酸化性雰囲気下において熱
処理することにより、前記非晶質半導体膜を結晶化して
結晶性半導体膜を形成する第二の工程と、 を含む事を特徴とする半導体装置の製造方法。10. A first step of forming an amorphous semiconductor film on an insulating material, and a substrate on which the amorphous semiconductor film is formed is heat-treated in a reducing atmosphere and then continuously oxidized. A second step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film by performing heat treatment in a neutral atmosphere, and a method of manufacturing a semiconductor device. 【請求項１１】請求項９または１０に記載の半導体装置
の製造方法において、 前記結晶性半導体膜をパターニングする第三の工程をさ
らに行う事を特徴とする半導体装置の製造方法。11. The method of manufacturing a semiconductor device according to claim 9, further comprising a third step of patterning the crystalline semiconductor film. 【請求項１２】請求項９乃至１１のいずれかに記載の半
導体装置の製造方法において、 前記結晶性半導体膜を構成する元素にシリコンを含む事
を特徴とする半導体装置の製造方法。12. The method of manufacturing a semiconductor device according to claim 9, wherein the element forming the crystalline semiconductor film contains silicon. 【請求項１３】絶縁性物質上に非晶質シリコン膜を形成
する第一の工程と、 前記非晶質シリコン膜が形成された基板を不活性雰囲気
下にて熱処理した後、連続して酸化性雰囲気下において
熱処理する第二の工程と、 を含む事を特徴とする半導体装置の製造方法。13. A first step of forming an amorphous silicon film on an insulating material, and a substrate on which the amorphous silicon film is formed is heat-treated in an inert atmosphere and continuously oxidized. And a second step of performing heat treatment in a neutral atmosphere. 【請求項１４】絶縁性物質上に非晶質シリコン膜を形成
する第一の工程と、 前記非晶質シリコン膜が形成された基板を還元性雰囲気
下にて熱処理した後、連続して酸化性雰囲気下において
熱処理する第二の工程と、 を含む事を特徴とする半導体装置の製造方法。14. A first step of forming an amorphous silicon film on an insulating material, the substrate on which the amorphous silicon film is formed is heat treated in a reducing atmosphere, and then continuously oxidized. And a second step of performing heat treatment in a volatile atmosphere, and a method of manufacturing a semiconductor device. 【請求項１５】絶縁性物質上に非晶質シリコン膜を堆積
する第一の工程と、 前記非晶質シリコン膜を島状にパターニング加工した
後、酸化膜を堆積する第二の工程と、 続いて酸化性雰囲気下において熱処理する第三の工程
と、 を含む事を特徴とする半導体装置の製造方法。15. A first step of depositing an amorphous silicon film on an insulating material, and a second step of depositing an oxide film after patterning the amorphous silicon film into an island shape. Then, a third step of performing a heat treatment in an oxidizing atmosphere, and a method of manufacturing a semiconductor device, comprising: 【請求項１６】絶縁性物質上に非晶質シリコン膜を堆積
する第一の工程と、 前記非晶質シリコン膜を島状にパターニング加工した
後、窒化膜を堆積する第二の工程と、 前記非晶質シリコン膜と前記窒化膜の界面に酸素イオン
を打ち込む第三の工程と、 続いて熱処理を施す第四の工程と、 を含む事を特徴とする半導体装置の製造方法。16. A first step of depositing an amorphous silicon film on an insulating material, and a second step of depositing a nitride film after patterning the amorphous silicon film into an island shape. A method of manufacturing a semiconductor device, comprising: a third step of implanting oxygen ions into an interface between the amorphous silicon film and the nitride film; and a fourth step of performing heat treatment subsequently. 【請求項１７】絶縁性物質上に非晶質半導体膜を堆積す
る第一の工程と、 前記非晶質半導体膜を島状にパターニング加工した後、
酸化膜を堆積する第二の工程と、 続いて酸化性雰囲気下において熱処理することにより前
記非晶質半導体膜を結晶化する第三の工程と、 を含む事を特徴とする半導体装置の製造方法。17. A first step of depositing an amorphous semiconductor film on an insulating material, and after patterning the amorphous semiconductor film into islands,
A method of manufacturing a semiconductor device, comprising: a second step of depositing an oxide film; and a third step of crystallizing the amorphous semiconductor film by subsequently performing a heat treatment in an oxidizing atmosphere. . 【請求項１８】請求項１７に記載の半導体装置の製造方
法において、 前記半導体膜を構成する元素にシリコンが含まれてお
り、且つ前記酸化膜に酸化珪素が含まれている事を特徴
とする半導体装置の製造方法。18. The method of manufacturing a semiconductor device according to claim 17, wherein the element forming the semiconductor film contains silicon, and the oxide film contains silicon oxide. Manufacturing method of semiconductor device. 【請求項１９】絶縁性物質上に非晶質半導体膜を堆積す
る第一の工程と、 前記非晶質半導体膜を島状にパターニング加工した後、
酸化膜を堆積する第二の工程と、 続いて窒化膜を堆積する第三の工程と、 前記酸化膜中に酸素イオンを打ち込む第四の工程と、 続いて熱処理することにより前記非晶質半導体膜を結晶
化する第五の工程と、 を含む事を特徴とする半導体装置の製造方法。19. A first step of depositing an amorphous semiconductor film on an insulating material; and after patterning the amorphous semiconductor film into islands,
A second step of depositing an oxide film, a third step of depositing a nitride film, a fourth step of implanting oxygen ions into the oxide film, and a heat treatment followed by the amorphous semiconductor A method of manufacturing a semiconductor device, comprising: a fifth step of crystallizing a film; 【請求項２０】絶縁性物質上に非晶質半導体膜を堆積す
る第一の工程と、 前記非晶質半導体膜を島状にパターニング加工した後、
窒化膜を堆積する第二の工程と、 前記非晶質半導体膜と前記窒化膜の界面に酸素イオンを
打ち込む第三の工程と、 続いて熱処理を施すことにより前記非晶質半導体膜を結
晶化する第四の工程と、 含む事を特徴とする半導体装置の製造方法。20. A first step of depositing an amorphous semiconductor film on an insulating material, and after patterning the amorphous semiconductor film into an island shape,
A second step of depositing a nitride film, a third step of implanting oxygen ions into the interface between the amorphous semiconductor film and the nitride film, and a heat treatment subsequently performed to crystallize the amorphous semiconductor film. And a fourth step for manufacturing a semiconductor device. 【請求項２１】請求項１９または２０に記載の半導体装
置の製造方法において、 前記半導体膜を構成する元素にシリコンが含まれてお
り、且つ前記窒化膜が窒化珪素膜である事を特徴とする
半導体装置の製造方法。21. The method of manufacturing a semiconductor device according to claim 19, wherein the element forming the semiconductor film contains silicon, and the nitride film is a silicon nitride film. Manufacturing method of semiconductor device. 【請求項２２】絶縁性物質上に非晶質シリコン膜を堆積
する第一の工程と、 前記非晶質シリコン膜を島状にパターニング加工した
後、酸化膜を堆積する第二の工程と、 続いて窒化膜を堆積する第三の工程と、 前記酸化膜中に酸素イオンを打ち込む第四の工程と、 続いて熱処理する第五の工程と、 を含む事を特徴とする半導体装置の製造方法。22. A first step of depositing an amorphous silicon film on an insulating material, and a second step of depositing an oxide film after patterning the amorphous silicon film into an island shape. Then, a third step of depositing a nitride film, a fourth step of implanting oxygen ions into the oxide film, and a fifth step of subsequently performing heat treatment are included. .