JP3178881U - 集積回路素子パッケージ構造 - Google Patents

集積回路素子パッケージ構造 Download PDF

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JP3178881U
JP3178881U JP2012004517U JP2012004517U JP3178881U JP 3178881 U JP3178881 U JP 3178881U JP 2012004517 U JP2012004517 U JP 2012004517U JP 2012004517 U JP2012004517 U JP 2012004517U JP 3178881 U JP3178881 U JP 3178881U
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package structure
integrated circuit
conductive bump
metal pad
metal
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ルー−チェン ホワン
ユ−リン マ
ピー．シー． チェン
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ミューチュアル−パク テクノロジー カンパニー リミテッド
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Abstract

【課題】ウェハが有する複数の集積回路素子の横側を保護するパッケージ構造を提供する。
【解決手段】パッケージ構造は、延伸金属パッド１１２と、第１、第２導電バンプ１１４，１２０と、絶縁層１１８とを含む。延伸金属パッドは、少なくとも１つの複数の集積回路素子１０４に電気的に接触する。第１導電バンプは、延伸金属パッド上に位置する。絶縁層は、少なくとも１つの複数の集積回路素子の上方及び側壁上に位置する。
【選択図】図８

Description

本考案は、集積回路素子パッケージ構造に関する。より詳細には、ウェハレベルの集積回路素子パッケージ構造に関する。
通常、ウェハレベルパッケージ構造のパッケージ材料は、集積回路素子の上方にのみ形成される。パッケージが完了し、個別のチップに切り分けるとき、集積回路素子の横側はパッケージ材料で保護されていない。
そのため、集積回路素子の横側も保護される集積回路素子パッケージ構造が必要とされている。
特開２００１−１４４１２１ 特開２００６−１００５３５ 特開２００２−３７３９６７ 特開平６−１５１４３８ 特開２００５−３４０６５５ 特開２００４−５６０２６
上記の必要に鑑み、本考案は、集積回路素子の横側も保護される集積回路素子パッケージ構造を提供することを目的とする。
本考案の１つの実施形態によると、複数の集積回路素子を有するウェハと、少なくとも１つのスリットと、延伸金属パッドと、第１導電バンプと、絶縁層とを含むパッケージ構造を提供する。少なくとも１つのスリットは、ウェハの中に位置し、ウェハを切り分けるためのものである。延伸金属パッドは、少なくとも１つの複数の集積回路素子に電気接続されている。第１導電バンプは、延伸金属パッド上に設けられる。絶縁層は、複数の集積回路素子の上方と少なくとも１つのスリット内に形成される。絶縁層は、少なくとも１つの複数の集積回路素子の１つの側壁を覆う。
延伸金属パッドの材料は、チタン（Ｔｉ）、チタンタングステン合金（ＴｉＷ）、クロム（Ｃｒ）、銅（Ｃｕ）、又はその組み合わせとすることができる。絶縁層の材料は、エポキシ樹脂、ポリイミド、ベンゾシクロブテン、液晶高分子、又はその組み合わせとすることができる。絶縁層は印刷により形成することができる。
パッケージ構造は、第１導電バンプ上に位置する第２導電バンプと、第２導電バンプ上に位置する表面金属層とをさらに備えていてもよい。第１導電バンプ及び第２導電バンプのうちの少なくとも一方は、複数の金属粒子と高分子化合物とを含有するものであってもよい。複数の金属粒子は、銅（Ｃｕ）、ニッケル（Ｎｉ）、銀（Ａｇ）、金（Ａｕ）粒子、又はその組み合わせとすることができる。複数の金属粒子の寸法は、１〜１０ミクロン（μｍ）の間とすることができる。高分子化合物は、エポキシ樹脂、液晶高分子、又はその組み合わせとすることができる。複数の金属粒子及び高分子化合物の体積比は、少なく
とも８５：１５とすることができる。第１導電バンプ及び第２導電バンプは、印刷により形成することができる。表面金属層の材料は、ニッケル、金、又はその組み合わせとすることができる。
パッケージ構造は、第１導電バンプ上に位置する金属壁をさらに備えていてもよい。金属壁の材料は、ニッケル、銅、金、又はその組み合わせとすることができる。
パッケージ構造は、少なくとも１つの複数の集積回路素子と延伸金属パッドとの間に設けられて、延伸金属パッドが少なくとも１つの複数の集積回路素子に電気コンタクトを取るための金属パッドをさらに備えることもできる。延伸金属パッドの面積は、金属パッドの面積よりも大きい。パッケージ構造は、少なくとも１つの複数の集積回路素子と延伸金属パッドとの間に位置する保護層をさらに含むこともできる。金属パッドの材料は、アルミニウム（Ａｌ）とすることができる。保護層の材料は、シリコン酸窒化膜（ＳｉＮＯ）とすることができる。
本考案のさらなる実施形態によると、ウェハが有する複数の集積回路素子の少なくとも１つをパッケージングしてあるパッケージ構造を提供する。パッケージ構造は、延伸金属パッドと、第１導電バンプと、絶縁層とを含む。延伸金属パッドは、少なくとも１つの複数の集積回路素子に電気的に接触する。第１導電バンプは、延伸金属パッド上に位置する。絶縁層は、少なくとも１つの複数の集積回路素子の上方及び側壁上に位置する。
延伸金属パッドの材料は、チタン、チタンタングステン合金、クロム、銅、又はその組み合わせとすることができる。前記絶縁層の材料は、エポキシ樹脂、ポリイミド、ベンゾシクロブテン、液晶高分子、又はその組み合わせとすることができる。絶縁層は、印刷により形成することができる。
パッケージ構造は、第１導電バンプ上に位置する第２導電バンプと、第２導電バンプ上に位置する表面金属層とをさらに備えていてもよい。第１導電バンプ及び第２導電バンプのうちの少なくとも一方は、複数の金属粒子と高分子化合物とからなるものであってもよい。複数の金属粒子は、銅、ニッケル、銀、金粒子、又はその組み合わせとすることができる。複数の金属粒子の寸法は、１〜１０ミクロンの間とすることができる。高分子化合物は、エポキシ樹脂、液晶高分子、又はその組み合わせとすることができる。複数の金属粒子及び高分子化合物の体積比は、少なくとも８５：１５とすることができる。第１導電バンプ及び第２導電バンプは、印刷により形成することができる。表面金属層の材料は、ニッケル、金、又はその組み合わせとすることができる。
パッケージ構造は、第１導電バンプ上に位置する金属壁をさらに備えてもよい。金属壁の材料は、ニッケル、銅、金、又はその組み合わせとすることができる。
パッケージ構造は、少なくとも１つの複数の集積回路素子と延伸金属パッドとの間に位置し、延伸金属パッドを複数の集積回路素子のうちの少なくとも１つに電気接続するための金属パッドをさらに備えることもできる。延伸金属パッドの面積は、金属パッドの面積よりも大きい。パッケージ構造は、少なくとも１つの複数の集積回路素子と延伸金属パッドとの間に位置する保護層をさらに備えていてもよい。金属パッドの材料は、アルミニウムとすることができる。保護層の材料は、シリコン酸窒化膜とすることができる。
本考案のさらにもう１つの実施形態は、ウェハ切り分け用に、少なくとも１つのスリットをウェハの中に形成するステップと、少なくとも１つの複数の集積回路素子に電気的に接触する延伸金属パッドを形成するステップと、第１導電バンプを延伸金属パッド上に形成するステップと、絶縁層を複数の集積回路素子の上方及び少なくとも１つのスリット内に形成するステップと、少なくとも１つのスリットを利用してウェハを切り分け、パッケージ済みの複数のチップを形成するステップとを含む、ウェハが有する複数の集積回路素
子の少なくとも１つをパッケージングするパッケージ構造の製造方法を提供する。絶縁層は、少なくとも１つの複数の集積回路素子の１つの側壁を覆う。
パッケージ構造の製造方法は、少なくとも１つのパッケージ済みの複数のチップを基板に実装するステップをさらに備えていてもよく、この基板は相互接続構造を有する。相互接続構造の材料は、ハンダ、銀ペースト、又はその組み合わせとすることができる。基板は、フレキシブルプリント基板（ＦＰＣ）、プリント回路基板（ＰＣＢ）、又はセラミック基板とすることができる。実装ステップは、パッケージ済みの複数のチップ及び相互接続構造を、表面実装技術（ＳＭＴ）を介して接合することを含むことができる。
延伸金属パッドの材料は、チタン、チタンタングステン合金、クロム、銅、又はその組み合わせとすることができる。絶縁層の材料は、エポキシ樹脂、ポリイミド、ベンゾシクロブテン、液晶高分子、又はその組み合わせとすることができる。絶縁層を複数の集積回路素子の上方及び少なくとも１つのスリット内に形成するステップは、絶縁層を複数の集積回路素子の上方及び少なくとも１つのスリット内に印刷し形成することを含むことができる。
パッケージ構造の製造方法は、第２導電バンプを第１導電バンプ上に形成するステップと、表面金属層を第２導電バンプ上に形成するステップとをさらに備えることが可能である。第１導電バンプを延伸金属パッド上に形成するステップ及び第２導電バンプを第１導電バンプ上に形成するステップの少なくとも一方において、複数の金属粒子及び高分子化合物を含有する導電バンプを形成してもよい。複数の金属粒子は、銅、ニッケル、銀、金粒子、又はその組み合わせとすることができる。複数の金属粒子の寸法は、１〜１０ミクロンの間とすることが可能である。高分子化合物は、エポキシ樹脂、液晶高分子、又はその組み合わせとすることが可能である。複数の金属粒子及び高分子化合物の体積比は、少なくとも８５：１５とすることができる。第１導電バンプを延伸金属パッド上に形成するステップ及び第２導電バンプを第１導電バンプ上に形成するステップは、それぞれ第１導電バンプを延伸金属パッド上に印刷し形成するステップと、第２導電バンプを第１導電バンプ上に印刷し形成するステップとを備えることができる。表面金属層の材料は、ニッケル、金、又はその組み合わせとすることができる。
パッケージ構造の製造方法は、金属壁を第１導電バンプ上に形成するステップをさらに備えることもできる。金属壁の材料は、ニッケル、銅、金、又はその組み合わせとすることができる。
パッケージ構造の製造方法は、延伸金属パッドが少なくとも１つの複数の集積回路素子に電気的に接触するようにする金属パッドを、少なくとも１つの複数の集積回路素子と延伸金属パッドとの間に形成するステップをさらに含むこともできる。延伸金属パッドの面積は、金属パッドの面積よりも大きい。このパッケージ構造の形成方法は、保護層を少なくとも１つの複数の集積回路素子と延伸金属パッドとの間に形成するステップをさらに含むことができる。金属パッドの材料は、アルミニウムとすることができる。保護層の材料は、シリコン酸窒化膜とすることができる。
本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。 本考案のパッケージ構造の形成方法に基づく実施例及びそれによって形成されるパッケージ構造を例示する断面図。
本考案の目的と特徴をさらに明確にするため、図面と合わせて実施例について詳細に説明する。
図１〜８は、本考案のパッケージ構造１００の形成方法に基づく実施例及びそれによって形成されるパッケージ構造１００を例示する断面図である。パッケージ構造１００は、ウェハ１０２が有する複数の集積回路素子１０４の少なくとも１つをパッケージングする。
先ず、図１に示すように、ウェハ１０２は複数の集積回路素子１０４、及びその上に形成された金属パッド１０８と保護層１１０とを有する。ここでは１つの集積回路素子１０４によって説明するが、その限りでない。この実施例は、少なくとも１つのスリット１０６をウェハの中に形成するステップを含む。この例において、スリット１０６は罫書き線（ｓｃｒｉｂｅ ｌｉｎｅ）であり、後でウェハを個別のチップに切り分けるために用い
る。
図２に示すように、次に、集積回路素子１０４に電気的に接触する延伸金属パッド１１２を形成する。この実施例において、延伸金属パッド１１２は、金属パッド１０８を介して集積回路素子１０４に接触し、延伸金属パッド１１２の面積は金属パッド１０８の面積よりも大きいが、その限りでない。延伸金属パッド１１２の材料は、チタン、チタンタングステン合金、クロム、銅、又はその組み合わせ、若しくは集積回路素子１０４に電気的に接触可能なその他の材料とすることができる。金属パッド１０８の材料は、アルミニウム、又は延伸金属パッド１１２を集積回路素子１０４に電気的に接触させることが可能なその他の材料とすることができる。保護層１１０の材料は、シリコン酸窒化膜、又は集積回路素子１０４を保護可能なその他の材料とすることができる。
図３において、第１導電バンプ１１４を延伸金属パッド１１２上に形成する。第１導電バンプ１１４は、複数の金属粒子及び高分子化合物を選択的に含むことができる。複数の金属粒子は、銅、ニッケル、銀、金粒子、又はその組み合わせとすることができるが、その限りでない。複数の金属粒子の寸法は、１〜１０ミクロンの間とすることができる。高分子化合物は、エポキシ樹脂、液晶高分子、又はその組み合わせとすることができるが、その限りでない。複数の金属粒子及び高分子化合物の体積比は、少なくとも８５：１５とすることができる。第１導電バンプ１１４を延伸金属パッド１１２上に形成するステップは、印刷により形成することができる。
この実施例は、金属壁１１６を第１導電バンプ１１４上に形成するステップをさらに選択的に含むことができる。金属壁１１６は、第１導電バンプ１１４の導電性を増加することができる。金属壁１１６の材料は、ニッケル、銅、金、又はその組み合わせとすることができるが、その限りでない。
図４に示すように、次に絶縁層１１８を集積回路素子１０４の上方とスリット１０６の中に形成する。この例において、絶縁層１１８は、金属壁１１６で選択的に覆われた第１導電バンプ１１４の横側及び延伸金属パッド１１２上にさらに形成されている。スリット１０６は集積回路素子１０４に隣接しているため、後でウェハを個別のチップに切り分けるときに、スリット１０６の中に分布した絶縁層１１８が集積回路素子１０４の側壁を覆い、集積回路素子１０４がさらに全面的に保護される。絶縁層１１８の材料は、エポキシ樹脂、ポリイミド、ベンゾシクロブテン、液晶高分子、又はその組み合わせ、若しくは集積回路素子１０４を保護可能なその他の材料とすることができる。絶縁層１１８を形成するステップは、印刷により形成することができる。
図５に示すように、本実施例は、絶縁層１１８の一部を取り除き、第１導電バンプ１１４を露出させることができる。図６に示すように、次に第２導電バンプ１２０を第１導電バンプ１１４上に形成する。表面金属層１２２を第２導電バンプ１２０上に選択的に形成し、パッケージ構造実施例１００を形成する。第２導電バンプ１２０は、複数の金属粒子及び高分子化合物を選択的に含むことができる。複数の金属粒子は、銅、ニッケル、銀、金粒子、又はその組み合わせとすることができるが、その限りでない。複数の金属粒子の寸法は、１〜１０ミクロンの間とすることができる。高分子化合物は、エポキシ樹脂、液晶高分子、又はその組み合わせとすることができるが、その限りでない。複数の金属粒子及び高分子化合物の体積比は、少なくとも８５：１５とすることができる。第２導電バンプ１２０を第１導電バンプ１１４上に形成するステップは、印刷により形成することができる。表面金属層１２２の材料は、ニッケル、金、又はその組み合わせ、若しくはパッケージ構造１００をその他の装置に接合するのに役立つその他の材料とすることができる。
図７に示すように、前記パッケージ構造１００の形成後、少なくとも一部のウェハ１０２を取り除くことができる。スリット１０６を利用してパッケージ済みの個別のチップを切り出すことができ、例えば点線Ｌに沿って分離する。スリット１０６の中に分布した絶縁層１１８が集積回路素子１０４の側壁を覆っているため、集積回路素子１０４がさらに全面的に保護される。
次に図８に示すように、パッケージ済みのチップを基板２２４に組み立てることができる。基板２２４は、相互接続構造２２６及び導線２２８を有する。絶縁層１１８が集積回路素子１０４の側壁を覆っているため、集積回路素子１０４がさらに全面的に保護されていることがここでも分かる。相互接続構造２２６の材料は、ハンダ、銀ペースト、又はその組み合わせ、若しくは表面金属層１２２で選択的に覆われた第２導電バンプ１２０と基板２２４とを接合可能なその他の材料とすることができる。基板２２４は、フレキシブルプリント基板、プリント基板、又はセラミック基板とすることができる。この実装ステップは、パッケージ済みのチップ及び相互接続構造２２６を、表面実装技術を介して接合する。
以上の内容は、本考案の比較的優れた実施例でしかなく、本考案の実用新案登録請求の範囲を限定するためのものではない。本考案で開示された主旨を逸脱しないその他の同等の変更又は修飾は、いずれも実用新案登録請求の範囲内に含まれる。
１００…パッケージ構造、１０２…ウェハ、１０４…集積回路素子、１０６…スリット、１０８…金属パッド、１１０…保護層、１１２…延伸金属パッド、１１４…第１導電バンプ、１１６…金属壁、１１８…絶縁層、１２０…第２導電バンプ、１２２…表面金属層、２２４…基板、２２６…相互接続構造、２２８…導線。

Claims (10)

  1. ウェハに設けられた複数の集積回路素子のうちの少なくとも１つの集積回路素子がパッケージングされているパッケージ構造において、
    前記少なくとも１つの集積回路素子に電気接続された延伸金属パッドと、
    前記延伸金属パッド上に設けられた第１導電バンプと、
    前記第１導電バンプ上に位置する第２導電バンプと、
    前記少なくとも１つの集積回路素子の上方及び側壁上に設けられた絶縁層とからなり、前記第１導電バンプ及び第２導電バンプのうちの少なくとも一方が、複数の金属粒子及び高分子化合物からなる、パッケージ構造。
  2. 前記第２導電バンプ上に位置する表面金属層をさらに備える請求項１に記載のパッケージ構造。
  3. 前記複数の金属粒子と前記高分子化合物の体積比が８５：１５であり、又は金属粒子の体積比がこれよりも高い、請求項２に記載のパッケージ構造。
  4. 前記第１導電バンプ上に設けられた金属壁をさらに備える、請求項３に記載のパッケージ構造。
  5. 前記少なくとも１つの集積回路素子と前記延伸金属パッドとの間に設けられて、前記延伸金属パッドを前記少なくとも１つの集積回路素子に電気接続させるさらなる金属パッドをさらに備え、
    前記延伸金属パッドの面積は前記さらなる金属パッドの面積よりも大きいものである、請求項４に記載のパッケージ構造。
  6. 前記少なくとも１つの集積回路素子と前記延伸金属パッドの間に設けられた保護層をさらに備える、請求項５に記載のパッケージ構造。
  7. 前記複数の金属粒子は、銅、ニッケル、銀、金粒子、又はその組み合わせからなる請求項３に記載のパッケージ構造。
  8. 前記複数の金属粒子の寸法は、１〜１０ミクロンの間である請求項７に記載のパッケージ構造。
  9. 前記高分子化合物は、エポキシ樹脂、液晶高分子、又はその組み合わせである、請求項８に記載のパッケージ構造。
  10. 前記絶縁層の材料は、エポキシ樹脂、ポリイミド、ベンゾシクロブテン、液晶高分子、又はその組み合わせである、請求項３に記載のパッケージ構造。
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Publication number Priority date Publication date Assignee Title
ES2226133T3 (es) 1997-05-15 2005-03-16 Palomar Medical Technologies, Inc. Aparato de tratamiento dermatologico.
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
TWI419284B (zh) * 2010-05-26 2013-12-11 Chipmos Technologies Inc 晶片之凸塊結構及凸塊結構之製造方法
US8829676B2 (en) * 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
EP2938265B1 (en) * 2012-12-28 2023-02-15 Philips Image Guided Therapy Corporation Intravascular ultrasound imaging apparatus
US9041198B2 (en) * 2013-10-22 2015-05-26 Applied Materials, Inc. Maskless hybrid laser scribing and plasma etching wafer dicing process
CN105097566A (zh) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 一种晶圆级扇出封装的制作方法
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2653179B2 (ja) * 1989-08-21 1997-09-10 富士電機株式会社 集積回路装置用バンプ電極の製造方法
JPH06151438A (ja) * 1992-11-12 1994-05-31 Tanaka Kikinzoku Kogyo Kk 感光性導電ペーストによるバンプ形成方法
JP3351706B2 (ja) * 1997-05-14 2002-12-03 株式会社東芝 半導体装置およびその製造方法
US6740960B1 (en) * 1997-10-31 2004-05-25 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
JP3516592B2 (ja) * 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6316952B1 (en) * 1999-05-12 2001-11-13 Micron Technology, Inc. Flexible conductive structures and method
US6593658B2 (en) * 1999-09-09 2003-07-15 Siliconware Precision Industries, Co., Ltd. Chip package capable of reducing moisture penetration
JP2001085361A (ja) * 1999-09-10 2001-03-30 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP3455762B2 (ja) * 1999-11-11 2003-10-14 カシオ計算機株式会社 半導体装置およびその製造方法
JP2001176899A (ja) * 1999-12-21 2001-06-29 Sanyo Electric Co Ltd 半導体装置の製造方法
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
JP2002289768A (ja) * 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
JP4183375B2 (ja) * 2000-10-04 2008-11-19 沖電気工業株式会社 半導体装置及びその製造方法
US6844957B2 (en) * 2000-11-29 2005-01-18 International Business Machines Corporation Three level stacked reflective display
US7498196B2 (en) * 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
JP3660275B2 (ja) * 2001-06-14 2005-06-15 シャープ株式会社 半導体装置およびその製造方法
US6818475B2 (en) * 2001-10-22 2004-11-16 Wen-Kun Yang Wafer level package and the process of the same
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
JP3951845B2 (ja) * 2002-07-24 2007-08-01 カシオ計算機株式会社 半導体装置の製造方法
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US6649445B1 (en) * 2002-09-11 2003-11-18 Motorola, Inc. Wafer coating and singulation method
US8269329B2 (en) * 2003-07-24 2012-09-18 Via Technologies, Inc. Multi-chip package
US7034394B2 (en) * 2003-10-08 2006-04-25 Intel Corporation Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
KR100604848B1 (ko) * 2004-04-30 2006-07-31 삼성전자주식회사 솔더 범프와 골드 범프의 접합을 갖는 시스템 인 패키지및 그 제조방법
JP2005340655A (ja) * 2004-05-28 2005-12-08 Shinko Electric Ind Co Ltd 半導体装置の製造方法および半導体基板の支持構造体
US7170187B2 (en) * 2004-08-31 2007-01-30 International Business Machines Corporation Low stress conductive polymer bump
JP4607531B2 (ja) * 2004-09-29 2011-01-05 カシオマイクロニクス株式会社 半導体装置の製造方法
US7160756B2 (en) * 2004-10-12 2007-01-09 Agency For Science, Techology And Research Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices
JP4731191B2 (ja) * 2005-03-28 2011-07-20 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
US7659612B2 (en) * 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7648847B2 (en) * 2006-06-26 2010-01-19 Hamilton Sundstrand Corporation In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit
US7626269B2 (en) * 2006-07-06 2009-12-01 Micron Technology, Inc. Semiconductor constructions and assemblies, and electronic systems
US7935568B2 (en) * 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US20080197480A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
US20080197474A1 (en) * 2007-02-16 2008-08-21 Advanced Chip Engineering Technology Inc. Semiconductor device package with multi-chips and method of the same
US7833881B2 (en) * 2007-03-02 2010-11-16 Micron Technology, Inc. Methods for fabricating semiconductor components and packaged semiconductor components
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US7727875B2 (en) * 2007-06-21 2010-06-01 Stats Chippac, Ltd. Grooving bumped wafer pre-underfill system
US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
JP4596001B2 (ja) * 2007-12-12 2010-12-08 カシオ計算機株式会社 半導体装置の製造方法
JP5175803B2 (ja) * 2009-07-01 2013-04-03 新光電気工業株式会社 半導体装置の製造方法
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof

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