JP2536640B2 - Wiring method - Google Patents
Wiring methodInfo
- Publication number
- JP2536640B2 JP2536640B2 JP1305379A JP30537989A JP2536640B2 JP 2536640 B2 JP2536640 B2 JP 2536640B2 JP 1305379 A JP1305379 A JP 1305379A JP 30537989 A JP30537989 A JP 30537989A JP 2536640 B2 JP2536640 B2 JP 2536640B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- area
- divided
- pin
- route searching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線処理方式に関し、特に大規模集積回路
（以下、LSIと略記する），プリント配線板（以下、PWB
と略記する）等の配線設計に用いられる配線処理方式に
関する。The present invention relates to a wiring processing method, and more particularly to a large scale integrated circuit (hereinafter abbreviated as LSI), a printed wiring board (hereinafter PWB).
Abbreviated as “) and the like.
従来、LSI,PWB等の配線設計に用いられる配線処理方
式では、配線領域内で配線すべきすべてのピンペアの配
線を１つの配線経路探索手段（いわゆるプロセッサ）に
より逐次的に行っていた。このような逐次的な配線処理
方式では、１つの配線経路探索手段が１ピンペアの配線
経路を求めるのに平均で1Tの時間を要すると仮定する
と、例えば25対のピンペアを配線するのに25Tの時間を
要していた。Conventionally, in a wiring processing method used for wiring design of LSI, PWB, etc., wiring of all pin pairs to be wired in a wiring area is sequentially performed by one wiring route searching means (so-called processor). In such a sequential wiring processing method, assuming that it takes an average of 1T to obtain a wiring route of one pin pair by one wiring route searching means, for example, it takes 25T to route 25 pin pairs. It took time.
また、１つの配線経路探索手段によりソフトウェア的
にピンペアの配線を並列的に行う配線処理方式もあった
が、このような配線処理方式は、配線手法（アルゴリズ
ム）に依存するところが大きく、チャンネル配線法，迷
路法等といった種々の配線手法に適用できる汎用的な手
法は存在しなかった（参考文献：「論理装置のCAD」，
情報処理学会，昭和56年３月20日発行）。There is also a wiring processing method in which one pair of wiring route searching means performs wiring of pin pairs in parallel by software, but such a wiring processing method largely depends on a wiring method (algorithm), and the channel wiring method is used. , There was no general-purpose method that can be applied to various wiring methods such as the maze method (Reference: "CAD of logic device",
Information Processing Society of Japan, published March 20, 1981).
上述した従来の配線処理方式では、配線領域内で配線
すべきすべてのピンペアの配線を１つの配線経路探索手
段により行っていたので、LSI,PWB等の大規模化および
高集積度化に伴い配線すべきピンペアの数が増大すると
配線処理に要する時間（ターンアラウンドタイム）もピ
ンペアの数の増大に伴って増えていくことになり、十分
に対処できなくなるという欠点がある。In the above-mentioned conventional wiring processing method, wiring of all pin pairs to be wired in the wiring area is performed by one wiring path searching means, so that wiring is required in accordance with large scale and high integration of LSI, PWB and the like. If the number of pin pairs to be increased increases, the time required for wiring processing (turnaround time) also increases with the increase in the number of pin pairs, and there is a drawback in that it cannot be adequately dealt with.
本発明の目的は、上述の点に鑑み、配線領域を複数の
分割配線領域に分割して各分割配線領域内でのピンペア
の配線を複数の配線経路探索手段に並列的に処理させる
ことにより、配線処理に要する時間を短縮することがで
きるようにした配線処理方式を提供することにある。In view of the above-mentioned point, the object of the present invention is to divide the wiring area into a plurality of divided wiring areas and process the wiring of the pin pair in each divided wiring area in parallel by a plurality of wiring route search means, An object of the present invention is to provide a wiring processing method capable of shortening the time required for wiring processing.
本発明の配線処理方式は、配線領域内で配線すべきピ
ンペアについて領域分割線を横切らないピンペアの数が
各分割配線領域で同じ程度になるように配線領域を複数
の分割配線領域に分割する配線領域分割手段と、配線時
に各分割配線領域内で配線すべきピンペアを配線経路探
索手段に割り当てる配線ピンペア割当て手段と、前記配
線領域分割手段により分割された各分割配線領域内でピ
ンペアの配線を行う並列処理可能な複数の前記配線経路
探索手段とを有する。The wiring processing method of the present invention divides a wiring area into a plurality of divided wiring areas such that the number of pin pairs that do not cross the area division line for the pin pairs to be wired in the wiring area is the same in each divided wiring area. An area dividing unit, a wiring pin pair assigning unit that assigns a pin pair to be wired in each divided wiring region to the wiring route searching unit at the time of wiring, and a pin pair is wired in each divided wiring region divided by the wiring region dividing unit. And a plurality of wiring route searching means capable of parallel processing.
本発明の配線処理方式では、配線領域分割手段が配線
領域内で配線すべきピンペアについて領域分割線を横切
らないピンペアの数が各分割配線領域で同じ程度になる
ように配線領域を複数の分割配線領域に分割し、配線ピ
ンペア割当て手段が配線時に各分割配線領域内で配線す
べきピンペアを配線経路探索手段に割り当て、並列処理
可能な複数の前記配線経路探索手段が配線領域分割手段
により分割された各分割配線領域内でピンペアの配線を
行う。According to the wiring processing method of the present invention, the wiring area dividing means divides the wiring area into a plurality of divided wirings such that the number of pin pairs that do not cross the area dividing line for the pin pairs to be wired in the wiring area is the same in each divided wiring area. The wiring pin pair assigning means assigns pin pairs to be wired in each divided wiring area to the wiring route searching means at the time of wiring, and the plurality of wiring route searching means capable of parallel processing are divided by the wiring area dividing means. Pin pair wiring is performed in each divided wiring area.
次に、本発明について図面を参照して詳細に説明す
る。Next, the present invention will be described in detail with reference to the drawings.
第１図は、本発明の一実施例に係る配線処理方式の構
成を示すブロック図である。本実施例の配線処理方式
は、配線領域内で配線すべきピンペアについて領域分割
線を横切らないピンペアの数が各分割配線領域で同じ程
度になるように配線領域を複数の分割配線領域に分割す
る配線領域分割手段１と、配線時に各分割配線領域内で
配線すべきピンペアを配線経路探索手段３に割り当てる
配線ピンペア割当て手段２と、配線領域分割手段１によ
り分割された各分割配線領域内でピンペアの配線を行う
並列処理可能な複数の配線経路探索手段（いわゆるプロ
セッサ）３と、配線領域の情報および配線結果の情報を
記憶する配線領域・配線結果記憶手段４と、配線領域内
の配線すべきピンペアに関する情報を記憶する配線ピン
ペア情報記憶手段５とから構成されている。FIG. 1 is a block diagram showing the configuration of a wiring processing system according to an embodiment of the present invention. The wiring processing method according to the present embodiment divides the wiring area into a plurality of divided wiring areas so that the number of pin pairs that do not cross the area division line for the pin pairs to be wired in the wiring area is the same in each divided wiring area. Wiring area dividing means 1, wiring pin pair allocating means 2 for allocating a pin pair to be wired in each divided wiring area to the wiring route searching means 3 at the time of wiring, and pin pairs in each divided wiring area divided by the wiring area dividing means 1. A plurality of wiring path search means (so-called processors) 3 capable of parallel processing for wiring, wiring area / wiring result storage means 4 for storing information on wiring areas and information on wiring results, and wiring within wiring areas It is composed of a wiring pin pair information storage means 5 for storing information about pin pairs.
次に、このように構成された本実施例の配線処理方式
の動作について説明する。Next, the operation of the wiring processing method of this embodiment configured as described above will be described.
ここでは、第２図（ａ）に示すような２層の配線領域
内で１層の端子の25対のピンペア201〜225を配線する場
合を例にとって説明する。なお、配線領域の分割法とし
て縦方向および横方向への分割を採用し、配線経路探索
手段３が４つある場合を想定する。Here, a case will be described as an example in which 25 pairs of pin pairs 201 to 225 of terminals of one layer are wired in a wiring region of two layers as shown in FIG. 2A. It is assumed that vertical and horizontal divisions are adopted as a method of dividing the wiring area and there are four wiring route searching means 3.
まず、配線領域分割手段１は、配線領域・配線結果記
憶手段４および配線ピンペア情報記憶手段５に格納され
た情報に基づいて、第２図（ｂ）に示すように、配線領
域内で配線すべきピンペア201〜225について領域分割線
を横切らないピンペアの数が各分割配線領域で同じ程度
になるように縦方向の３本の領域分割線226〜228を求
め、配線領域を４つの分割配線領域229〜232に分割す
る。このとき、各分割配線領域229〜232内で閉じるピン
ペアの数は、第２図（ｂ）からも明らかなように、各々
3,3,3および３となる。First, the wiring area dividing means 1 performs wiring within the wiring area based on the information stored in the wiring area / wiring result storage means 4 and the wiring pin pair information storage means 5, as shown in FIG. 2 (b). For the power pin pairs 201 to 225, three vertical area dividing lines 226 to 228 are obtained so that the number of pin pairs that do not cross the area dividing line becomes the same in each divided wiring area, and the wiring area is divided into four divided wiring areas. Divide into 229 to 232. At this time, the number of pin pairs to be closed in each of the divided wiring areas 229 to 232 is as shown in FIG. 2 (b).
It becomes 3,3,3 and 3.
次に、配線ピンペア割当て手段２は、４つの分割配線
領域229〜232内で閉じるピンペアの組を、４つの配線経
路探索手段３にそれぞれ割り当てる。Next, the wiring pin pair allocating means 2 allocates the pair of pin pairs closed in the four divided wiring areas 229 to 232 to the four wiring route searching means 3, respectively.
続いて、４つの配線経路探索手段３は、並列的にピン
ペアの配線経路を探索して配線を行い、第２図（ｃ）に
示すような配線233〜239を得、配線結果の情報を配線領
域・配線結果記憶手段４に記憶する。この時点までの配
線処理に要した時間は、１つの配線経路探索手段３が１
ピンペアの配線経路を求めるのに平均で1Tの時間を要す
ると仮定すると、３ピンペア分の処理時間に当たる3Tで
ある。Subsequently, the four wiring route search means 3 parallelly search the wiring routes of the pin pair to perform wiring, obtain the wirings 233 to 239 as shown in FIG. 2C, and wire the wiring result information. It is stored in the area / wiring result storage means 4. The time required for the wiring process up to this point is one wiring route searching means 3
Assuming that it takes 1T on average to obtain the wiring route of the pin pair, it is 3T, which is the processing time for 3 pin pairs.
さらに、配線領域分割手段１は、配線領域・配線結果
記憶手段４および配線ピンペア情報記憶手段５に格納さ
れた情報に基づいて、第２図（ｄ）に示すように、配線
領域内で配線すべきピンペア201〜225について領域分割
線を横切らないピンペアの数が各分割配線領域で同じ程
度になるように横方向の３本の領域分割線240〜242を求
め、配線領域を４つの分割配線領域243〜246に分割す
る。このとき、各分割配線領域243〜246内で閉じるピン
ペアの数は、第２図（ｄ）からも明らかなように、各々
3,3,4および３となる。Further, the wiring area dividing means 1 performs wiring within the wiring area based on the information stored in the wiring area / wiring result storage means 4 and the wiring pin pair information storage means 5, as shown in FIG. 2 (d). For the power pin pairs 201 to 225, the three horizontal area dividing lines 240 to 242 are obtained so that the number of pin pairs that do not cross the area dividing line becomes the same in each divided wiring area, and the wiring area is divided into four divided wiring areas. Divide into 243-246. At this time, the number of pin pairs to be closed in each of the divided wiring areas 243 to 246 is as shown in FIG. 2 (d).
It becomes 3,3,4 and 3.
次に、配線ピンペア割当て手段２は、４つの分割配線
領域243〜246内で閉じるピンペアの組を、４つの配線経
路探索手段３にそれぞれ割り当てる。Next, the wiring pin pair allocating means 2 allocates the pairs of pin pairs closed in the four divided wiring areas 243 to 246 to the four wiring route searching means 3, respectively.
続いて、４つの配線経路探索手段３は、並列的にピン
ペアの配線経路を探索して配線を行い、第２図（ｅ）に
示すような配線247〜253を得、最終的な配線結果の情報
を配線領域・配線結果記憶手段４に記憶する。この時点
での配線処理に要した時間は、４ピンペア分の処理時間
が加算されて7Tとなる。この配線処理に要した時間7T
が、既述した従来の逐次的な配線処理方式により25対の
ピンペアを配線するのに要した時間25Tに比べて格段的
に短くなっていることはいうまでもない。Subsequently, the four wiring route searching means 3 search the wiring routes of the pin pairs in parallel and perform wiring to obtain the wirings 247 to 253 as shown in FIG. Information is stored in the wiring area / wiring result storage means 4. The time required for the wiring processing at this point is 7T by adding the processing time for 4 pin pairs. Time required for this wiring process 7T
However, it goes without saying that the time required to wire 25 pairs of pins by the above-mentioned conventional sequential wiring processing method is much shorter than 25T.
なお、上記実施例の動作の説明では、配線領域の分割
法として縦方向および横方向への分割を採用し、配線経
路探索手段３が４つある場合を想定したが、配線領域の
分割法が縦方向および横方向への分割に限られるもので
はなく、また配線経路探索手段３の数が４つに限られる
ものでもないことはもちろんである。In the description of the operation of the above-mentioned embodiment, it is assumed that the wiring area is divided in the vertical direction and the horizontal direction and that there are four wiring route searching means 3. However, the wiring area dividing method is It is needless to say that the number of wiring route searching means 3 is not limited to four, and the number of wiring route searching means 3 is not limited to four.
以上説明したように本発明は、配線領域を複数の分割
配線領域に分割して各分割配線領域内でのピンペアの配
線を複数の配線経路探索手段に並列的に処理させること
により、配線処理に要する時間を従来に比べて大幅に短
縮することができ、これによりLSI,PWB等の大規模化お
よび高集積化に伴うピンペアの数の増加による配線処理
に要する時間の増大に対処することが可能になるという
効果がある。As described above, the present invention divides a wiring area into a plurality of divided wiring areas and causes a plurality of wiring route searching means to process the wiring of a pin pair in each divided wiring area in parallel, thereby performing wiring processing. The time required can be greatly reduced compared to the conventional one, and it is possible to cope with the increase in the time required for wiring processing due to the increase in the number of pin pairs accompanying the large-scale integration and high integration of LSI and PWB. Has the effect of becoming.
第１図は本発明の一実施例に係る配線処理方式の構成を
示すブロック図、 第２図（ａ）は２層の配線領域と１層の端子のピンペア
を例示する図、 第２図（ｂ）は第１図中の配線領域分割手段により分割
された分割配線領域および縦方向の領域分割線の一例を
示す図、 第２図（ｃ）は第１図中の配線経路探索手段により並列
的に配線処理が行われて得られた配線の一例を示す図、 第２図（ｄ）は第１図中の配線領域分割手段により分割
された分割配線領域および横方向の領域分割線の一例を
示す図、 第２図（ｅ）は第１図中の配線経路探索手段により並列
的に配線処理が行われて得られた配線の一例を示す図で
ある。 図において、 １……配線領域分割手段、 ２……配線ピンペア割当て手段、 ３……配線経路探索手段、 ４……配線領域・配線結果記憶手段、 ５……配線ピンペア情報記憶手段である。FIG. 1 is a block diagram showing a configuration of a wiring processing method according to an embodiment of the present invention, FIG. 2 (a) is a diagram illustrating a wiring layer of two layers and pin pairs of terminals of one layer, FIG. 2B is a diagram showing an example of divided wiring areas and vertical area dividing lines divided by the wiring area dividing means in FIG. 1, and FIG. 2C is parallel by the wiring route searching means in FIG. FIG. 2D is a diagram showing an example of a wiring obtained by performing a wiring process, and FIG. 2D is an example of a divided wiring area divided by the wiring area dividing means in FIG. 1 and an area dividing line in the lateral direction. FIG. 2 (e) is a diagram showing an example of wiring obtained by performing wiring processing in parallel by the wiring route searching means in FIG. In the figure, 1 ... Wiring area dividing means, 2 ... Wiring pin pair allocating means, 3 ... Wiring route searching means, 4 ... Wiring area / wiring result storage means, 5 ... Wiring pin pair information storage means.
Claims (1)
領域分割線を横切らないピンペアの数が各分割配線領域
で同じ程度になるように配線領域を複数の分割配線領域
に分割する配線領域分割手段と、 配線時に各分割配線領域内で配線すべきピンペアを配線
経路探索手段に割り当てる配線ピンペア割当て手段と、 前記配線領域分割手段により分割された各分割配線領域
内でピンペアの配線を行う並列処理可能な複数の前記配
線経路探索手段と を有することを特徴とする配線処理方式。1. A wiring area dividing means for dividing a wiring area into a plurality of divided wiring areas such that the number of pin pairs that do not cross the area division line for pin pairs to be wired in the wiring area is the same in each divided wiring area. And a wiring pin pair assigning means for assigning a pin pair to be routed in each divided wiring area to the wiring route searching means at the time of wiring, and pin pair wiring in each divided wiring area divided by the wiring area dividing means A plurality of the wiring route searching means, and a wiring processing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1305379A JP2536640B2 (en) | 1989-11-24 | 1989-11-24 | Wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1305379A JP2536640B2 (en) | 1989-11-24 | 1989-11-24 | Wiring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03165052A JPH03165052A (en) | 1991-07-17 |
| JP2536640B2 true JP2536640B2 (en) | 1996-09-18 |
Family
ID=17944411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1305379A Expired - Lifetime JP2536640B2 (en) | 1989-11-24 | 1989-11-24 | Wiring method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536640B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0731693B2 (en) * | 1987-04-30 | 1995-04-10 | 横河電機株式会社 | Automatic wiring method for printed circuit boards |
-
1989
- 1989-11-24 JP JP1305379A patent/JP2536640B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03165052A (en) | 1991-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0403826B1 (en) | Minimizing the interconnection cost of electronically linked objects | |
| JP4187947B2 (en) | PATTERN CORRECTION METHOD, PATTERN CORRECTION DEVICE, AND RECORDING MEDIUM CONTAINING PATTERN CORRECTION PROGRAM | |
| JPS63225869A (en) | Wiring path search system | |
| JPS63137A (en) | Processor for determining wiring region | |
| Suaris et al. | A quadrisection-based combined place and route scheme for standard cells | |
| US5550714A (en) | Schematic generator and schematic generating method | |
| US4700316A (en) | Automated book layout in static CMOS | |
| JP2536640B2 (en) | Wiring method | |
| KR20010024944A (en) | A method for manufacturing and designing an electronic device and electronic apparatus | |
| JP3006140B2 (en) | Automatic wiring method | |
| JP2536119B2 (en) | Wiring method | |
| JP3006244B2 (en) | Automatic wiring method | |
| JPH0645446A (en) | Method of wiring layout | |
| JP2687699B2 (en) | Parallel wiring processing method for integrated circuit | |
| JPH07202000A (en) | Lsi wiring system by parallel processing | |
| JP2825928B2 (en) | Channel merge wiring method | |
| Cha et al. | SEGRA: a very fast general area router for multichip modules | |
| JP3006156B2 (en) | Automatic wiring method | |
| JP2914025B2 (en) | LSI automatic placement and routing processing method | |
| JPS62285184A (en) | Lsi design method | |
| JPH0962731A (en) | Wiring housing capacity evaluation system | |
| JPH0645443A (en) | Hierarchical wiring method | |
| JPS63226774A (en) | Automatic wiring method for integrated circuit | |
| JPH02298048A (en) | Automatic layout system | |
| JPH05160263A (en) | Method of determining signal placement for lsi external terminal |