JPH0645446A - Method of wiring layout - Google Patents
Method of wiring layoutInfo
- Publication number
- JPH0645446A JPH0645446A JP4217507A JP21750792A JPH0645446A JP H0645446 A JPH0645446 A JP H0645446A JP 4217507 A JP4217507 A JP 4217507A JP 21750792 A JP21750792 A JP 21750792A JP H0645446 A JPH0645446 A JP H0645446A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- information
- unit areas
- elements
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＣＡＤ装置を使用し
て、ＬＳＩ等の集積回路の素子の自動配置、素子間を接
続する自動配線、それらの再配置、再配線を行うための
配置配線方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to automatic placement of elements in an integrated circuit such as an LSI, automatic wiring for connecting elements, and relocation and rewiring for using the CAD device. It is about the method.
【０００２】[0002]
【従来の技術】従来では、ＣＡＤ装置を使用して、回路
記述（ＶＨＤＬ、ネットリスト等）からマニュアルによ
って回路データの作成を行うとき、回路の構成を理解
し、素子の配置及び配線等を一つ一つ行っている。この
処理において、例えば２点間の自動配線を行うとき、そ
の間に存在する障害物（配置した素子、別の配線等）を
避けるために、膨大な計算やパターン認識が必要となっ
てくる。2. Description of the Related Art Conventionally, when a CAD device is used to manually create circuit data from a circuit description (VHDL, netlist, etc.), it is necessary to understand the structure of the circuit and arrange the elements and wiring. I'm going one by one. In this process, for example, when performing automatic wiring between two points, enormous calculation and pattern recognition are required to avoid obstacles (arranged elements, other wiring, etc.) existing between them.
【０００３】例えば、図６に示すように、素子１〜６が
予め配置されているとき、素子１の端子１ａと素子４の
端子４ａの間を配線する場合に、その配線７は図６に示
す経路を通る配線となり、この配線は可能なものの、か
なりのパターン認識とそれに伴う処理が必要となってく
る。また、図７に示すように、素子８〜１２が配置され
ているとき、点１３と点１４の間を配線する場合、素子
８〜１２の配置（位置関係）に制限（ルール）がなく、
実質的に配線は無理となる。For example, as shown in FIG. 6, when the elements 1 to 6 are arranged in advance, when wiring between the terminal 1a of the element 1 and the terminal 4a of the element 4, the wiring 7 is shown in FIG. Although the wiring passes through the route shown, this wiring is possible, but considerable pattern recognition and accompanying processing are required. Further, as shown in FIG. 7, when the elements 8 to 12 are arranged and when wiring is performed between the points 13 and 14, there is no limitation (rule) on the arrangement (positional relation) of the elements 8 to 12,
Wiring is practically impossible.
【０００４】[0004]
【発明が解決しようとする課題】このように、従来の配
置配線方法では、無限に近い計算やパターン認識が必要
となり、処理工程が多すぎるために、実行速度や拡張性
の面からみて、無駄が多すぎるという問題があった。As described above, the conventional placement and routing method requires nearly infinite calculation and pattern recognition, and since there are too many processing steps, it is wasteful in terms of execution speed and expandability. There was a problem that there were too many.
【０００５】本発明の目的は、実行速度の向上及び処理
の効率を上げることができ、更にオペレーションによる
入力ミスや経験不足による誤りを防ぐことができるよう
にした配置配線方法を提供することである。An object of the present invention is to provide a placement and routing method capable of improving the execution speed and processing efficiency, and further preventing an input error due to an operation and an error due to lack of experience. .
【０００６】[0006]
【課題を解決するための手段】このために本発明は、１
個の単位領域に１個の素子情報、１個の配線情報、又は
空き情報の何れかのみを割り付け、複数の単位領域を行
列状に二次元に集合させてＣＡＤ装置によって自動的に
素子配置及び配線を行う配置配線方法であって、素子情
報を割り付けた２個の単位領域の間の配線を、該２個の
単位領域の間の隣合った空き単位領域を配線領域として
割り付けて行い、空き単位領域がないときに１行又は１
列の単位領域追加を行って、該追加した単位領域の１又
は複数を配線領域とするように構成した。To this end, the present invention provides
Only one piece of element information, one piece of wiring information, or vacant information is assigned to each unit area, and a plurality of unit areas are two-dimensionally assembled in a matrix to automatically arrange elements by a CAD device. A layout wiring method for wiring, wherein wiring between two unit areas to which element information is allocated is performed by allocating adjacent empty unit areas between the two unit areas as wiring areas. 1 line or 1 when there is no unit area
A unit area of a column is added, and one or more of the added unit areas is used as a wiring area.
【０００７】[0007]
【作用】本発明では、行列状に二次元に集合した複数の
単位領域の個々が、素子情報、配線情報、空き情報を持
つので、この単位領域によって配置配線が規則化され、
また単位領域の追加によって、一旦作成した配置配線に
対してそれを修正して再配置、再配線することが容易と
なる。In the present invention, each of a plurality of unit areas that are two-dimensionally arranged in a matrix has element information, wiring information, and vacant information.
Further, the addition of the unit area makes it easy to correct the layout and wiring that has been created once, and to rearrange and re-wire.
【０００８】[0008]
【実施例】以下、本発明の実施例について説明する。図
１はその一実施例の処理のフローチャート、図２は当該
処理を行うためのハードウエア構成図、図３は単位領域
の集合説明図、図４と図５は再度配置の説明図である。EXAMPLES Examples of the present invention will be described below. FIG. 1 is a flowchart of the process of the embodiment, FIG. 2 is a hardware configuration diagram for performing the process, FIG. 3 is an explanatory diagram of a set of unit areas, and FIGS. 4 and 5 are explanatory diagrams of the rearrangement.
【０００９】本実施例では、素子配置及び配線を行う２
次元領域を、図３に示すように、升目状に配列した複数
の単位領域Ａからなる領域と定義付けて、その単位領域
Ａに、素子情報、配線情報、又は空き情報を持たせるよ
うにする。つまり、その単位領域Ａは、素子部分、配線
部分、或いは単なる空き領域のいずれかとなる。In this embodiment, element placement and wiring are performed 2
As shown in FIG. 3, the dimensional area is defined as an area composed of a plurality of unit areas A arranged in a grid pattern, and the unit area A is provided with element information, wiring information, or vacancy information. . That is, the unit area A is either an element portion, a wiring portion, or a vacant area.
【００１０】ＣＡＤ装置は、図２に示すように、ローカ
ルＣＰＵ１５、そのＣＰＵ１５に対して接続されたモニ
タ１６、操作用マウス１７、キーボート１８、データ格
納用ディスク１９、ワークメモリ２０、ローカルＣＰＵ
１５では重い処理を実行するための処理専用のサーバ２
１、バス２２等からなる。As shown in FIG. 2, the CAD device includes a local CPU 15, a monitor 16 connected to the CPU 15, an operating mouse 17, a keyboard 18, a data storage disk 19, a work memory 20, and a local CPU.
15 is a server 2 dedicated to processing for executing heavy processing.
1, bus 22, etc.
【００１１】さて、図１に示すように、作成すべき回路
をコンピュータ用語で記述したＶＨＤＬ、ネットリスト
等の「回路記述情報」を入力して「基本データベース」
を作成し、この「基本データベース」に基づいて、「素
子情報」（個々の素子の種別、当該素子の端子数等）、
単位領域Ａを配列して各単位領域Ａにアドレスを付与し
た「配列パターン情報」、「ネット（接続）情報」等の
データを作成する。Now, as shown in FIG. 1, "circuit description information" such as VHDL and a netlist in which a circuit to be created is described in computer terms is input and a "basic database" is input.
Based on this "basic database", "element information" (type of each element, number of terminals of the element, etc.),
Data such as "arrangement pattern information" and "net (connection) information" in which the unit areas A are arranged and addresses are given to the respective unit areas A are created.
【００１２】そして、これら「素子情報」、「配列パタ
ーン情報」、及び「ネット情報」の各データを取り込ん
で、まず「素子配置処理」を行う。この結果、「素子配
置リスト」のデータが作成される。この「素子配置リス
ト」は、どの素子をどのアドレスの単位領域Ａに割り当
てるかを決めたリストである。Then, each of the "element information", "arrangement pattern information", and "net information" is taken in, and the "element placement processing" is first performed. As a result, the data of the "element arrangement list" is created. This "element arrangement list" is a list that determines which element is assigned to the unit area A of which address.
【００１３】次に、「素子情報」、「素子配置リス
ト」、及び「ネット情報」の各データを取り込んで、
「配線処理」を行う。この「配線処理」は接続すべき素
子を各々割り当てた一方の単位領域Ａから他方の単位領
域Ａまでの間を、隣合った空き単位領域Ａを接続するこ
とで行う。この結果、これらの空き単位領域Ａが配線領
域として機能するようになる。Next, each data of "element information", "element arrangement list", and "net information" is fetched,
Perform "wiring processing". This "wiring process" is performed by connecting adjacent empty unit areas A from one unit area A to which the elements to be connected are assigned to the other unit area A. As a result, these empty unit areas A function as wiring areas.
【００１４】なお、このとき配線すべき両単位領域Ａの
間に空き単位領域Ａが存在しないときは、「素子配置リ
スト」に対して、前記したように一旦決められた素子配
置に関して、配線のために、素子配置を変更する処理及
び単位領域Ａの割込み追加を行う。At this time, when there is no empty unit area A between the unit areas A to be wired, the wiring of the element layout determined once as described above in the "element layout list" is set. In order to do so, the processing for changing the element arrangement and the interrupt addition of the unit area A are performed.
【００１５】例えば、図４に示すように、単位領域Ａ
１、Ａ２、Ａ３に素子３１、３２、３３がマッピング
（割り当て）されているとき、廻り込み処理を行わない
場合（本実施例では行わない）には、素子３１と素子３
３を接続するための空き単位領域Ａがない。For example, as shown in FIG. 4, the unit area A
When the elements 31, 32, and 33 are mapped (assigned) to 1, A2, and A3 and the wraparound process is not performed (not performed in this embodiment), the elements 31 and 3 are
There is no vacant unit area A for connecting No. 3.
【００１６】そこで、図５に示すように、単位領域Ａを
縦方向に一列分だけ追加（網掛で示した。）する。この
とき、素子３２、３３は隣のアドレスの単位領域Ａ
２’、Ａ３’に移動する。このように単位領域Ａが追加
されると、「配列パターン情報」に対して、単位領域Ａ
の追加により増加した内容にデータ変更が行われる。ま
た「素子配置リスト」に対しても、素子配置アドレスの
内容についてデータ変更が行われる。Therefore, as shown in FIG. 5, the unit area A is added by one column in the vertical direction (shown by hatching). At this time, the elements 32 and 33 are arranged in the unit area A of the adjacent address.
Move to 2 ', A3'. When the unit area A is added in this way, the unit area A is added to the “array pattern information”.
The data will be changed to the contents increased by the addition of. In addition, the data of the element arrangement address is changed in the "element arrangement list".
【００１７】そして、このようにデータ変更された、或
いはデータ変更が必要なかった「配列パターン情報」、
「素子配置リスト」に基づいて「配線処理」が行われる
と、「配列パターン情報」のデータに基づいて「回路出
力処理」が行われ、最終的に「回路データ」が得られ
る。Then, the "array pattern information" in which the data has been changed in this way or the data need not be changed,
When the "wiring process" is performed based on the "element layout list", the "circuit output process" is performed based on the data of the "array pattern information", and finally "circuit data" is obtained.
【００１８】なお、ここでは、単位領域Ａの１個に１個
の素子、又は１本の配線の一部を割り当てたが、１個の
素子を複数の単位領域Ａに割り当てることもできる。こ
のときは、この複数単位領域Ａに分離制限を加える必要
がある。Although one element or part of one wiring is assigned to one unit area A here, one element may be assigned to a plurality of unit areas A. At this time, it is necessary to apply a separation restriction to the plurality of unit areas A.
【００１９】また、上記ではマニュアルエディトについ
ては説明しなかったが、これは必要に応じて、素子配置
処理において行えば良い。Although the manual edit has not been described above, this may be performed in the element placement process, if necessary.
【００２０】[0020]
【発明の効果】以上から本発明によれば、配線処理に廻
り込み処理を行う必要がないので、その処理のための時
間が不要となり、処理速度、処理効率が向上する。ま
た、配線経路の割り出しは、接続すべき素子間の単位領
域を調べることにより行われるので、その領域は特定の
範囲に制限され、この点でも処理速度が向上する。更に
操作が簡単となるので、オペレーションによる入力ミス
や経験不足による誤りを防ぐこともできる。As described above, according to the present invention, since it is not necessary to perform the wrap-around processing in the wiring processing, the time for the processing is unnecessary, and the processing speed and the processing efficiency are improved. Further, since the wiring path is determined by checking the unit area between the elements to be connected, the area is limited to a specific range, and the processing speed is improved also in this respect. Further, since the operation becomes simple, it is possible to prevent an input error due to the operation and an error due to lack of experience.
【図１】 本発明の一実施例の処理のフローチャートで
ある。FIG. 1 is a flowchart of processing according to an embodiment of the present invention.
【図２】 当該処理を行うためのハードウエア構成図で
ある。FIG. 2 is a hardware configuration diagram for performing the processing.
【図３】 単位領域の集合説明図である。FIG. 3 is an explanatory diagram of a set of unit areas.
【図４】 再度配置の説明図である。FIG. 4 is an explanatory diagram of arrangement again.
【図５】 再度配置の説明図である。FIG. 5 is an explanatory diagram of arrangement again.
【図６】 従来の配線方法の説明図である。FIG. 6 is an explanatory diagram of a conventional wiring method.
【図７】 従来の配線方法の説明図である。FIG. 7 is an explanatory diagram of a conventional wiring method.
Ａ、Ａ１〜Ａ３：単位領域、１〜６：素子、７：配線、
８〜１２：素子、１３、１４：点、３１、〜３３：素
子。A, A1 to A3: unit area, 1 to 6: element, 7: wiring,
8 to 12: element, 13, 14: point, 31, to 33: element.
Claims (1)
の配線情報、又は空き情報の何れかのみを割り付け、複
数の単位領域を行列状に二次元に集合させてＣＡＤ装置
によって自動的に素子配置及び配線を行う配置配線方法
であって、 素子情報を割り付けた２個の単位領域の間の配線を、該
２個の単位領域の間の隣合った空き単位領域を配線領域
として割り付けて行い、空き単位領域がないときに１行
又は１列の単位領域追加を行って、該追加した単位領域
の１又は複数を配線領域とすることを特徴とする配置配
線方法。1. A unit device allocates only one piece of element information, one piece of wiring information, or free information, and a plurality of unit areas are two-dimensionally gathered in a matrix form by a CAD device. A layout and wiring method for automatically arranging and wiring elements, wherein wiring between two unit areas to which element information is allocated is defined as an adjacent empty unit area between the two unit areas. The layout and wiring method is characterized in that one row or one column of unit areas is added when there is no empty unit area, and one or more of the added unit areas is used as a wiring area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4217507A JPH0645446A (en) | 1992-07-24 | 1992-07-24 | Method of wiring layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4217507A JPH0645446A (en) | 1992-07-24 | 1992-07-24 | Method of wiring layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0645446A true JPH0645446A (en) | 1994-02-18 |
Family
ID=16705322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4217507A Withdrawn JPH0645446A (en) | 1992-07-24 | 1992-07-24 | Method of wiring layout |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0645446A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6378121B2 (en) | 1997-03-27 | 2002-04-23 | Nec Corporation | Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor |
| JP2008090446A (en) * | 2006-09-29 | 2008-04-17 | Fujitsu Ltd | Layout design program, recording medium with same program recorded therein, layout design method, and layout design device |
-
1992
- 1992-07-24 JP JP4217507A patent/JPH0645446A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6378121B2 (en) | 1997-03-27 | 2002-04-23 | Nec Corporation | Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor |
| JP2008090446A (en) * | 2006-09-29 | 2008-04-17 | Fujitsu Ltd | Layout design program, recording medium with same program recorded therein, layout design method, and layout design device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |