JP2508826B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2508826B2
JP2508826B2 JP63295006A JP29500688A JP2508826B2 JP 2508826 B2 JP2508826 B2 JP 2508826B2 JP 63295006 A JP63295006 A JP 63295006A JP 29500688 A JP29500688 A JP 29500688A JP 2508826 B2 JP2508826 B2 JP 2508826B2
Authority
JP
Japan
Prior art keywords
region
drain
base
source
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63295006A
Other languages
Japanese (ja)
Other versions
JPH02369A (en
Inventor
雅之 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP63295006A priority Critical patent/JP2508826B2/en
Publication of JPH02369A publication Critical patent/JPH02369A/en
Application granted granted Critical
Publication of JP2508826B2 publication Critical patent/JP2508826B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/7821—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特にドレインとソース
間の破壊耐量を向上するための保護用のダイオードを備
えた電界効果ドランジスタを含む半導体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a field effect transistor having a protective diode for improving a breakdown resistance between a drain and a source. .

〔従来の技術〕[Conventional technology]

従来この種の半導体装置では、保護用ダイオードを備
えた場合の例として、特開昭59−98557号公報に示され
ているように、縦型電界効果トランジスタの構造に対し
て、半導体基板内部にツェナーダイオードを形成してい
るものがあった。第６図は、この従来の半導体装置の断
面図ぜある。この縦型電界効果トランジスタは、N+導電
型の基板21″及びこのN+導電型基板21″の上に形成され
たＮ導電型のドレイン領域22″からなる半導体基板４″
の下面部にドレイン電極９″が接合され、Ｎ型ドレイン
領域22″内には半導体基板４″の上面側、すなわちドレ
イン電極９″が接合されている側とは反対の表面側から
複数のＰ導電型のベース領域３″が互いに所定間隔をあ
けて拡散形成されている。又、各Ｐ型ベース領域３″内
には一対のN+導電型のソース領域10″が互いに所定間隔
をあけて表面側から拡散形成され、この一対のソース領
域10″の間にはP+導電型のベースコンタクト拡散領域1
1″が形成されている。Ｐ型ベース領域３″が形成され
ていないＮ型ドレイン領域22″の表面部分22a″とＰ型
ベース領域３″の表面及びソース領域10″の表面にゲー
ト酸化膜６″を介してゲートポリシリコン電極５″が形
成されている。又、ソース領域10″及びP+型ベースコン
タクト拡散領域11″にはソース電極８″が形成されソー
ス電極８″とゲート電極５″との間には、層間絶縁膜1
2″が形成されている。このようにして、ソース電極
８″、N+ソース領域10″,P型ベース領域３″,N型トレイ
ン領域22″,N+ドレイン領域21″及びドレイン電極９″
を有する縦型電界効果トランジスタが形成されている。Conventionally, in this type of semiconductor device, as an example of the case where a protective diode is provided, as shown in Japanese Patent Laid-Open No. 59-98557, the structure of a vertical field effect transistor is not provided inside the semiconductor substrate. Some were forming Zener diodes. FIG. 6 is a sectional view of this conventional semiconductor device. The vertical field effect transistor, "semiconductor substrate 4 made of" N conductivity type drain region 22 formed on the N + conductivity type substrate 21 'and the N + conductivity type substrate 21 "
The drain electrode 9 "is joined to the lower surface of the semiconductor substrate 4" in the N-type drain region 22 "from the upper surface side of the semiconductor substrate 4", that is, the surface opposite to the side where the drain electrode 9 "is joined. Conductive type base regions 3 "are diffused and formed at predetermined intervals. Also, in each P type base region 3", a pair of N + conductive type source regions 10 "are provided at predetermined intervals. A P + conductive type base contact diffusion region 1 is formed between the pair of source regions 10 ″ by diffusion formation from the surface side.
1 ″ is formed. A gate oxide film is formed on the surface portion 22a ″ of the N-type drain region 22 ″ where the P-type base region 3 ″ is not formed, the surface of the P-type base region 3 ″ and the surface of the source region 10 ″. A gate polysilicon electrode 5 ″ is formed via 6 ″. A source electrode 8 ″ is formed in the source region 10 ″ and the P + type base contact diffusion region 11 ″, and the interlayer insulating film 1 is formed between the source electrode 8 ″ and the gate electrode 5 ″.
2 ″ are thus formed. In this way, the source electrode 8 ″, the N + source region 10 ″, the P type base region 3 ″, the N type train region 22 ″, the N + drain region 21 ″ and the drain electrode 9 ″.
A vertical field effect transistor having is formed.

また、ベース領域３″の底部はN+ドレイン領域21″と
接するように形成されているので、各ベース領域３″の
底部にはツェナーダイオードが形成される。このように
して、ドレイン領域22″とベース領域３″とで決定され
る耐圧より低いソースドレイン間耐圧でブレークダウン
するツェナーダイオードが、ソース，ドレイン間に形成
され、縦型電界効果トランジスタのソース・ドレイン間
の破壊耐量を増加させている。すなわち、この例の半導
体装置の等価回路は、第７図に示すように、FET70のド
レインＤとソースＳとの間に保護用ツェナーダイオード
DZを接続した構成となっている。なお、14″はフィール
ド熱酸化膜である。Further, since the bottom of the base region 3 ″ is formed so as to be in contact with the N + drain region 21 ″, a Zener diode is formed at the bottom of each base region 3 ″. In this way, the drain region 22 ″ A zener diode that breaks down at a source-drain breakdown voltage lower than the breakdown voltage determined by the base region 3 ″ is formed between the source and the drain to increase the breakdown resistance between the source and drain of the vertical field effect transistor. That is, the equivalent circuit of the semiconductor device of this example has a protective Zener diode between the drain D and the source S of the FET 70 as shown in FIG.
It is configured to connect D Z. In addition, 14 ″ is a field thermal oxide film.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来技術は、縦型電界効果トランジスタ構造
では比較的容易に実現できるが、一つの半導体基板上に
多数の電界効果トランジスタを構成できる横型電界効果
トランジスタにおいては、実現が困難である。又従来技
術においてツェナーダイオードの電圧を変化させるため
にはＰ型ベース領域３″の濃度を変化させる必要があ
る。しかし、従来技術の電界効果トランジスタのチャン
ネル領域はＰ型ベース領域３″の表面に形成されるの
で、このベース領域３″の濃度を変化させるとスレッシ
ュホルド電圧VTも変化してしまう。よって従来技術では
ツェナーダイオードの電圧を変化させるのは困難であっ
た。The above-mentioned conventional technique can be realized relatively easily in the vertical field effect transistor structure, but is difficult to realize in the lateral field effect transistor in which a large number of field effect transistors can be formed on one semiconductor substrate. Further, in the prior art, in order to change the voltage of the Zener diode, it is necessary to change the concentration of the P-type base region 3 ″. However, the channel region of the conventional field effect transistor is located on the surface of the P-type base region 3 ″. Since the threshold voltage V T changes when the concentration of the base region 3 ″ is changed, it is difficult to change the voltage of the Zener diode in the prior art.

また、横型電界効果トランジスタにおいては、第８図
に示すように、半導体基板に独立に形成した電界効果ト
ランジスタ（以降FETと称す）とツェナーダイオードと
を接続した構造とすることが考えられる。この構造は、
Ｐ型の半導体基板81″にＮ型のウェル82″及び86″を設
け、ウェル82″表面にＰ型のベース83″,N型高濃度のソ
ース84″及びＮ型高濃度の不純物領域85″を設け、少く
ともベース83″のチャネル形成領域上にはゲート絶縁膜
を介してゲート88″を設け、ウェル86″表面にはＰ型高
濃度領域83a″及びＮ型高濃度の不純物領域85″を設
け、ソース84″，ベース83″，及びウェル86″内のＰ型
高濃度領域83a″はソース電極89″Ｓに接続され、ウェ
ル82″内のＮ型高濃度のドレイン接続領域85″とウェル
86″内のＮ型高濃度の不純物領域85″には、ドレイン電
極89d″が接続している。ここで、Ｎ型のウェル86″と
Ｐ型高濃度の不純物領域83a″とはそれぞれをカソード
とアノードとする保護用のツェナーダイオードを構成し
ている。Further, in the lateral field effect transistor, as shown in FIG. 8, it may be considered that a field effect transistor (hereinafter referred to as FET) independently formed on a semiconductor substrate and a Zener diode are connected to each other. This structure is
N type wells 82 "and 86" are provided on a P type semiconductor substrate 81 ", and a P type base 83", an N type high concentration source 84 "and an N type high concentration impurity region 85" are provided on the surface of the well 82 ". And a gate 88 ″ is provided at least on the channel formation region of the base 83 ″ through a gate insulating film, and a P-type high concentration region 83a ″ and an N-type high concentration impurity region 85 ″ are provided on the surface of the well 86 ″. The source 84 ″, the base 83 ″, and the P-type high-concentration region 83a ″ in the well 86 ″ are connected to the source electrode 89 ″ S, and the P-type high-concentration drain connection region 85 ″ in the well 82 ″ is formed. Well
A drain electrode 89d ″ is connected to the N-type high-concentration impurity region 85 ″ in 86 ″. Here, the N-type well 86 ″ and the P-type high-concentration impurity region 83a ″ are cathodes, respectively. And a Zener diode for protection, which serves as an anode.

従って、この半導体装置の等価回路も、第７図に示す
ように、FET70のドレインＤとソースＳとの間に保護用
のツェナーダイオードDZを接続した構成となっている。Therefore, the equivalent circuit of this semiconductor device also has a structure in which the protective Zener diode D Z is connected between the drain D and the source S of the FET 70 as shown in FIG.

上述した半導体装置では、FETとサージに対する保護
用のツェナーダイオードとを半導体基板に独立に形成し
ているので、ツェナーダイオードの破壊耐量を充分に大
きくしようとすると素子面積が大きくなり高密度化を阻
害すると共に構造が複雑になって寄生素子効果によるラ
ッチアップが起こるなど動作が不安定になり易いという
欠点がある。In the above-described semiconductor device, the FET and the Zener diode for protection against surge are formed independently on the semiconductor substrate, so if the breakdown resistance of the Zener diode is made sufficiently large, the element area becomes large and the density is hindered. At the same time, the structure becomes complicated and the operation tends to become unstable, such as latch-up due to the parasitic element effect.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置は、第１導電型の半導体層からな
るドレインと、このドレイン表面に設けた第２導電型の
ベースと、このベース表面の所定の位置に設けた第１導
電型のソースと、ベース表面のベースとドレインとに挟
まれた部分からなるチャネル形成領域上にゲート絶縁膜
を介して設けたゲートとを備えた電界効果トランジスタ
を含む半導体装置において、ベース表面のチャネル形成
領域以外の部分にドレインに連なる第１導電型でドレイ
ンより高濃度の不純物領域を形成してベースとこの不純
物領域とからなる保護用のダイオードを設けて成る。The semiconductor device of the present invention includes a drain formed of a semiconductor layer of the first conductivity type, a base of the second conductivity type provided on the surface of the drain, and a source of the first conductivity type provided at a predetermined position on the surface of the base. In a semiconductor device including a field effect transistor having a gate provided on a channel formation region formed of a portion sandwiched between a base and a drain on a base surface via a gate insulating film, a semiconductor device other than the channel formation region on the base surface is provided. An impurity region of the first conductivity type, which is connected to the drain and has a higher concentration than that of the drain, is formed in a portion, and a protective diode including a base and the impurity region is provided.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は、本発明の第１の実施例の断面図である。こ
の実施例は、Ｐ型の半導体基板１にＮ型のウェル２から
なるドレイン領域を設け、ウェル２の表面にＰ型のベー
ス3,N型高濃度のソース10,P型高濃度不純物領域11,及び
ゲート絶縁膜を介して形成したゲート電極５を設け、ベ
ース３をアノードとする保護用のツェナーダイオードの
カソードのＮ型高濃度の不純物領域13を設け、更にベー
ス３とソース10とをソース電極８で接続し、不純物領域
７を介してドレイン電極９にウェル２からなるドレイン
領域とツェナーダイオードのカソードとなる不純物領域
13とを接続している。上記の実施例についてソース，ド
レイン間耐圧25V電流容量1Aの横型電界効果トランジス
タの場合を取り上げ数値を用いて説明する。FIG. 1 is a sectional view of the first embodiment of the present invention. In this embodiment, a drain region composed of an N-type well 2 is provided on a P-type semiconductor substrate 1, and a P-type base 3, an N-type high-concentration source 10, and a P-type high-concentration impurity region 11 are provided on the surface of the well 2. , And a gate electrode 5 formed via a gate insulating film, an N-type high-concentration impurity region 13 of the cathode of a protective Zener diode having the base 3 as an anode, and the base 3 and the source 10 as sources. The drain region 9 is connected to the electrode 8 and is connected to the drain electrode 9 through the impurity region 7 and the impurity region serving as the cathode of the Zener diode.
13 and is connected. The above embodiment will be described using numerical values by taking the case of a lateral field effect transistor having a source-drain breakdown voltage of 25V and a current capacity of 1A.

Ｐ型基板１は比抵抗が11.0〜15.0Ωcm程度のものでそ
の表面から拡散によりＮ型のウェル領域２が形成されて
いる。ウェル領域２は深さ６μｍ程度であり表面濃度は
２〜４×1016atm/cm2である。ベース領域３は、深さ2,5
μｍ程度で表面濃度は５〜８×1017atm/cm2である。こ
の表面濃度によりトランジスタのスレッシュホルド電圧
VTがコントロールされる。ソース領域10及びＰ型高濃度
不純物領域11は両方とも深さ1.0μｍ程度，表面濃度１
×1020程度である。ドレイン領域のＮ型高濃度領域７は
ソース10と同時に形成される。ここで重要な点は、ツェ
ナー電圧を決定する領域13の濃度だがこれはイオン注入
法によって正確にコントロールできる。耐圧25Vの場合
は、加速電圧50KeVドーズ量２×1013cm-2で形成され深
さは２μｍ程度，表面濃度は、１×1017atm/cm2程度に
コントロールされる。横方向の寸法はゲート電極５の幅
は10μｍ間隔は15μｍであり、コンタクト孔の寸法はソ
ース側10μｍドレイン側６μｍアルミニウム電極の幅は
ドレイン側10μｍソース側15μｍである。第２図は本実
施例の平面図である。各領域はそれぞれ第１図に対応し
ている。ツェナー形成用の高濃度不純物領域13はゲート
電極５をとり囲む様に形成してある。この領域は巾５〜
10μｍ程度で十分でありこの領域を形成する為に新たに
素子面積が増加する事はない。それはドレインとソース
間の耐圧を十分確保するためには、高濃度領域７とベー
ス領域３の間は10μｍ以上離す必要がある為、その領域
を使用して、ツェナーダイオードを形成できるからであ
る。この図において15はドレインコンタクト領域、16は
ソースコンタクト領域でありその他は第１図の各領域に
対応している。The P-type substrate 1 has a specific resistance of about 11.0 to 15.0 Ωcm, and an N-type well region 2 is formed by diffusion from the surface thereof. The well region 2 has a depth of about 6 μm and a surface concentration of 2 to 4 × 10 16 atm / cm 2 . The base region 3 has a depth of 2,5
The surface concentration is about 5 μm to 8 × 10 17 atm / cm 2 . Due to this surface concentration, the threshold voltage of the transistor is
V T is controlled. Both the source region 10 and the P-type high concentration impurity region 11 have a depth of about 1.0 μm and a surface concentration of 1
It is about × 10 20 . The N-type high concentration region 7 of the drain region is formed simultaneously with the source 10. The important point here is the concentration of the region 13 that determines the Zener voltage, which can be accurately controlled by the ion implantation method. When the withstand voltage is 25 V, the acceleration voltage is 50 KeV and the dose amount is 2 × 10 13 cm −2. The depth is about 2 μm and the surface concentration is about 1 × 10 17 atm / cm 2 . The lateral dimension is such that the width of the gate electrode 5 is 10 μm and the interval is 15 μm. The dimension of the contact hole is 10 μm on the source side and 6 μm on the drain side. The width of the aluminum electrode is 10 μm on the drain side and 15 μm on the source side. FIG. 2 is a plan view of this embodiment. Each area corresponds to FIG. The high concentration impurity region 13 for forming the Zener is formed so as to surround the gate electrode 5. This area has a width of 5
About 10 μm is sufficient, and the element area will not be newly increased to form this region. This is because the high concentration region 7 and the base region 3 need to be separated by 10 μm or more in order to secure a sufficient breakdown voltage between the drain and the source, and a zener diode can be formed using that region. In this figure, 15 is a drain contact region, 16 is a source contact region, and the others correspond to the regions in FIG.

第３図は本発明の第２の実施例の断面図である。 FIG. 3 is a sectional view of the second embodiment of the present invention.

この実施例では、Ｐ型の半導体基板31′表面のＮ型高
濃度の埋込層32a′上のＰ型の不純物領域31a′からなる
素子分離領域によって仕切られたＮ型のエピタキシャル
層32′からなるドレイン領域を設け、埋込層32a′から
エピタキシャル層32′表面に至るＮ型高濃度の不純物領
域35′からなるドレイン引出し領域を設け、エピタキシ
ャル層32′表面にＰ型のベース38′,N型高濃度のソース
34′及びゲート絶縁膜を介して形成したゲート38′並び
にＮ型高濃度の不純物領域36′からなるツェナーダイオ
ードのカソードを設け、更にソース34′及びベース33′
を接続したソース電極39s′と不純物領域35′に接続し
たドレイン電極39d′とを設けている。In this embodiment, an N-type epitaxial layer 32 'is partitioned by an element isolation region consisting of a P-type impurity region 31a' on an N-type high concentration buried layer 32a 'on the surface of a P-type semiconductor substrate 31'. And a drain extraction region consisting of an N-type high-concentration impurity region 35 'extending from the buried layer 32a' to the surface of the epitaxial layer 32 ', and a P-type base 38', N on the surface of the epitaxial layer 32 '. Mold high concentration sauce
A cathode of a Zener diode consisting of 34 ', a gate 38' formed through a gate insulating film, and an N-type high-concentration impurity region 36 'is provided, and further, a source 34' and a base 33 '.
There is provided a source electrode 39s' connected to each other and a drain electrode 39d 'connected to the impurity region 35'.

第４図は本発明の第３の実施例の断面図である。これ
は、本発明を縦型電界効果トランジスタに適用した場合
である。この第４図は、N+導電型の基板21′及びこのN+
導電型基板21′の上に形成されたＮ導電型のドレイン領
域22′からなる半導体基板４′からなりこの基板の下面
部にドレイン電極９′が接合され、上部には、ベース領
域３′ソース領域10′及びゲートポリシリコン電極
５′，ソースアルミニウム電極８′がある。12′は層間
絶縁膜,11′は高濃度ベース領域である。本実施例の特
徴は、不純物領域13′を有していることであり、ベース
領域３′と不純物領域13′接触させてソースとドレイン
間にツェナーダイオードを形成している。この実施例に
おいても、ツェナーダイオードの電圧をＮ型不純物領域
13′の濃度を変化させることによって、縦型電界効果ト
ランジスタの閾価電圧VTと独立に制御できる。FIG. 4 is a sectional view of the third embodiment of the present invention. This is the case where the present invention is applied to a vertical field effect transistor. This FIG. 4 shows a substrate 21 'of N + conductivity type and this N +
A drain electrode 9'is joined to the lower surface of a semiconductor substrate 4'consisting of an N-conductive type drain region 22 'formed on a conductive type substrate 21', and a base region 3'source is formed on the upper surface. There is a region 10 ', a gate polysilicon electrode 5', a source aluminum electrode 8 '. 12 'is an interlayer insulating film, and 11' is a high-concentration base region. A feature of this embodiment is that it has an impurity region 13 ', and a zener diode is formed between the source and the drain by contacting the base region 3'and the impurity region 13'. Also in this embodiment, the voltage of the Zener diode is set to the N-type impurity region.
By changing the concentration of 13 ', the threshold voltage V T of the vertical field effect transistor can be controlled independently.

なお、第１〜第３の実施例の半導体装置の等価回路
も、第７図に示すように、FET70のドレインＤとソース
４との間に保護用のツェナーダイオードDZを接続した構
成となっている。The equivalent circuits of the semiconductor devices of the first to third embodiments also have a configuration in which a protective Zener diode D Z is connected between the drain D and the source 4 of the FET 70 as shown in FIG. ing.

第５図は、イオンの加速エネルギーが100KeVのとき
の、イオン注入のドーズ量−ツェナー電圧特性図であ
る。FIG. 5 is a dose-zener voltage characteristic diagram of ion implantation when the ion acceleration energy is 100 KeV.

従って、第１〜第３図の実施例の不純物領域13,6′及
び13′を、イオン注入法によって形成する場合には、第
５図に示すような関係によりツェナー電圧を所望の値に
設定することが出来る。Therefore, when the impurity regions 13, 6'and 13 'of the embodiment of FIGS. 1 to 3 are formed by the ion implantation method, the Zener voltage is set to a desired value according to the relationship shown in FIG. You can do it.

〔発明の効果〕〔The invention's effect〕

以上説明した様に本発明の半導体装置では、ソース及
びドレイン間に接続するサージに対する保護用のツェナ
ーダイオードをベースとベースに接する反対導電型の不
純物領域とで構成することによって、破壊耐量の十分に
ある保護用のツェナーダイオードを占有面積をほとんど
とらずに素子内に面積効率良く形成出来て素子の高濃度
化をより一層進めることができる。また、ベースと反対
導電型の不純物領域を付加することによりツェナーダイ
オードを形成しているので構造がより単純になり、寄生
素子によるラッチアップ等の誤動作が起きにくい安定動
作が可能になるという効果がある。さらに、従来の様
に、半導体基板内部に形成するのに対して、本発明にお
いては、不純物領域を表面に設けているので、イオン注
入等により耐圧コントロールが容易にでき、又内部に高
濃度領域がいらない為その分低価格にする事ができる。As described above, in the semiconductor device of the present invention, the Zener diode for protection against surges connected between the source and the drain is composed of the base and the impurity region of the opposite conductivity type in contact with the base, so that the breakdown resistance is sufficiently high. It is possible to form a certain protective Zener diode in the element with a high area efficiency while taking up almost no occupied area, and it is possible to further increase the concentration of the element. Further, since the Zener diode is formed by adding the impurity region of the conductivity type opposite to that of the base, the structure becomes simpler, and the stable operation in which malfunction such as latch-up due to the parasitic element does not occur can be achieved. is there. Further, unlike the prior art, which is formed inside the semiconductor substrate, in the present invention, since the impurity region is provided on the surface, the breakdown voltage can be easily controlled by ion implantation or the like, and the high concentration region is formed inside. Because you do not need it, you can lower the price accordingly.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の第１の実施例を説明するための断面
図、第２図は第１図の平面図であり、第１図は第２図の
AA′線断面図である。第３図は本発明の第２の実施例を
説明するための断面図、第４図は本発明の第３の実施例
を説明するための断面図、第５図は本発明の第１〜第３
の実施例の半導体装置におけるドーズ量とツェナー電圧
との関係を示した図、第６図は従来の半導体装置の断面
図、第７図は本発明の第１〜第３の実施例及び従来の半
導体装置の等価回路図、第８図は本発明と関連する半導
体装置の断面図である。 １……半導体基板、２……ウェル領域、3,3′,3″……
ベース領域、４′,4″……ドレイン基板領域、5,5′,
5″……ゲートポリシリ電極、6,6′,6″……ゲート酸化
膜、７……高濃度ドレイン領域、8,8′,8″……ソース
アルミ電極、9,9′,9″……ドレインアルミ電極、10,1
0′,10″……ソース領域、11,11′,11″……高濃度ベー
ス領域、12,12′,12″……層間絶縁膜、13,13′……ツ
ェナー形成用不純物領域、14,14′,14″……フィールド
酸化膜、15……ドレインコンタクト領域、16……ソース
コンタクト領域、21,21′……N+導電型基板、22′,22″
……Ｎ導電型ドレイン領域、31′,81″……半導体基
板、31a′……不純物領域、32′……エピタキシャル
層、32a′……埋込層、82″……ウェル、33′,83″……
ベース、83a″……不純物領域、34′,84″……ソース、
35′,85″,36′……不純物領域、86″……ウェル、3
7′,37″……酸化膜、38′,88″……ゲート、39d′,89
d″……ドレイン電極、39s′,89s″……ソース電極、70
……FET、Ｄ……ドレイン、DZツェナーダイオード、Ｇ
……ゲート、Ｓ……ソース。FIG. 1 is a sectional view for explaining the first embodiment of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG.
It is a sectional view taken along the line AA ′. 3 is a sectional view for explaining a second embodiment of the present invention, FIG. 4 is a sectional view for explaining a third embodiment of the present invention, and FIG. 5 is a first through a first embodiment of the present invention. Third
Showing the relationship between the dose amount and the Zener voltage in the semiconductor device of the above embodiment, FIG. 6 is a sectional view of the conventional semiconductor device, and FIG. 7 is the first to third embodiments of the present invention and the conventional one. FIG. 8 is an equivalent circuit diagram of the semiconductor device, and FIG. 8 is a sectional view of the semiconductor device related to the present invention. 1 ... semiconductor substrate, 2 ... well region, 3,3 ', 3 "...
Base region, 4 ', 4 "... Drain substrate region, 5,5',
5 ″ ... gate polysilicon electrode, 6,6 ′, 6 ″ …… gate oxide film, 7 …… high-concentration drain region, 8,8 ′, 8 ″ …… source aluminum electrode, 9,9 ′, 9 ″ …… Drain aluminum electrode, 10,1
0 ', 10 "... source region, 11,11', 11" ... high-concentration base region, 12,12 ', 12 "... interlayer insulating film, 13,13' ... Zener forming impurity region, 14 , 14 ′, 14 ″ …… field oxide film, 15 …… drain contact region, 16 …… source contact region, 21,21 ′ …… N + conductivity type substrate, 22 ′, 22 ″
... N-conductivity type drain region, 31 ', 81 "... semiconductor substrate, 31a' ... impurity region, 32 '... epitaxial layer, 32a' ... buried layer, 82" ... well, 33 ', 83 ″ ……
Base, 83a ″ …… impurity region, 34 ′, 84 ″ …… source,
35 ', 85 ", 36' ... impurity region, 86" ... well, 3
7 ', 37 "... oxide film, 38', 88" ... gate, 39d ', 89
d ″ …… Drain electrode, 39s ′, 89s ″ …… Source electrode, 70
…… FET, D …… Drain, D Z Zener diode, G
... gate, S ... source.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】第１導電型の半導体層からなるドレイン
と、該ドレイン表面に設けた第２導電型のベースと、該
ベース表面の所定の位置に設けた前記第１導電型のソー
スと、前記ベース表面の前記ベースと前記ドレインとに
挟まれた部分からなるチャネル形成領域上にゲート絶縁
膜を介して設けたゲートとを備えた電界効果トランジス
タを含む半導体装置において、前記ベース表面のチャネ
ル形成領域以外の部分に前記ドレインに連なる第１導電
型で前記ドレインより高濃度の不純物領域を形成しで前
記ベースと前記不純物領域とからなる保護用のダイオー
ドを設けたことを特徴とする半導体装置1. A drain comprising a semiconductor layer of a first conductivity type, a base of a second conductivity type provided on the surface of the drain, a source of the first conductivity type provided at a predetermined position on the surface of the base, In a semiconductor device including a field effect transistor having a gate provided on a channel forming region formed by a portion sandwiched between the base and the drain on the base surface, forming a channel on the base surface. A semiconductor device, characterized in that an impurity region of a first conductivity type, which is connected to the drain and has a higher concentration than that of the drain, is formed in a portion other than the region, and a protective diode including the base and the impurity region is provided.
JP63295006A 1987-11-24 1988-11-21 Semiconductor device Expired - Lifetime JP2508826B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63295006A JP2508826B2 (en) 1987-11-24 1988-11-21 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP29701187 1987-11-24
JP62-297011 1987-11-24
JP63295006A JP2508826B2 (en) 1987-11-24 1988-11-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02369A JPH02369A (en) 1990-01-05
JP2508826B2 true JP2508826B2 (en) 1996-06-19

Family

ID=26560087

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Country Status (1)

Country Link
JP (1) JP2508826B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2698486B1 (en) * 1992-11-24 1995-03-10 Sgs Thomson Microelectronics Direct overvoltage protection structure for vertical semiconductor component.
JP4872141B2 (en) * 1999-10-28 2012-02-08 株式会社デンソー Power MOS transistor
US7405913B2 (en) * 2003-04-11 2008-07-29 Fuji Electric Device Technology Co. Semiconductor device having transistor with high electro-static discharge capability and high noise capability

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574151A (en) * 1980-06-11 1982-01-09 Hitachi Ltd Mos integrated circuit device
JPS59158546A (en) * 1983-02-28 1984-09-08 Mitsubishi Electric Corp Complementary type metal oxide semiconductor integrated circuit device
JPS6377155A (en) * 1986-09-19 1988-04-07 Fujitsu Ltd Open drain output circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574151A (en) * 1980-06-11 1982-01-09 Hitachi Ltd Mos integrated circuit device
JPS59158546A (en) * 1983-02-28 1984-09-08 Mitsubishi Electric Corp Complementary type metal oxide semiconductor integrated circuit device
JPS6377155A (en) * 1986-09-19 1988-04-07 Fujitsu Ltd Open drain output circuit

Also Published As

Publication number Publication date
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