JPS59158546A - Complementary type metal oxide semiconductor integrated circuit device - Google Patents
Complementary type metal oxide semiconductor integrated circuit deviceInfo
- Publication number
- JPS59158546A JPS59158546A JP58034157A JP3415783A JPS59158546A JP S59158546 A JPS59158546 A JP S59158546A JP 58034157 A JP58034157 A JP 58034157A JP 3415783 A JP3415783 A JP 3415783A JP S59158546 A JPS59158546 A JP S59158546A
- Authority
- JP
- Japan
- Prior art keywords
- type
- bulk
- source
- dielectric resistance
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 230000015556 catabolic process Effects 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 2
- 101100457032 Homo sapiens MGST1 gene Proteins 0.000 description 3
- 102100026741 Microsomal glutathione S-transferase 1 Human genes 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技魯分野〕
この発明は相補形MO8衆種回路装置(0MO8IC)
に関するものである。[Detailed Description of the Invention] [Field of the Invention] This invention relates to a complementary MO8 type circuit device (0MO8IC).
It is related to.
CMO6ICは′i自費電力か少なく、動作電源電圧範
囲が広いなどの利点をもっているので、近年急速に広く
用いられるようになった。第1図はCM OS回路の最
小単位を示す回路図で、第2図はこの回路構成を実腺に
実現した0MO8ICの従来例を示す断面図である。図
において、AはpチャネルM OSトランジスタ(p−
MO8T)、’BはnチャネルM OS T (n−M
O8T)である。第2図において、(1)はn−形半導
体基板、(21はn −MO8T Bを形成するための
p−形アイランド、1′3)はp−MO8TAのソース
、(4)は同じくドレイン、(5)はn−MOfET
Bのソース、(6)は同じくドレインで、(7)は電源
端子■3sへの接続のための′p+形コンタクト層でガ
ードリング層を兼ねている。(8)は電源端子■DDへ
の接続のためのn形コンタクト層である。通常、第1図
に示すように、p −M OS T Aのソース(3)
は電源端子■DDに、p−MO8TBのソース(6)は
電掠端子vS、に接続され、両biO8T人、Bのゲー
1・は共通Gこ入力端子1Nに接続され、両MO8T
A−、Bのドレイン+4+ 、 +6+苗は共通に出
力端子OUTに接続される。CMO6 ICs have advantages such as low self-power consumption and wide operating power supply voltage range, so they have rapidly become widely used in recent years. FIG. 1 is a circuit diagram showing the minimum unit of a CMOS circuit, and FIG. 2 is a cross-sectional view showing a conventional example of an 0MO8IC that actually realizes this circuit configuration. In the figure, A is a p-channel MOS transistor (p-
MO8T), 'B is n-channel MOST (n-M
O8T). In FIG. 2, (1) is an n-type semiconductor substrate, (21 is a p-type island for forming n-MO8T B, 1'3) is the source of p-MO8TA, (4) is also the drain, (5) is n-MOfET
B's source, (6) is also a drain, and (7) is a 'p+ type contact layer for connection to the power supply terminal 3s, which also serves as a guard ring layer. (8) is an n-type contact layer for connection to the power supply terminal DD. Usually, as shown in FIG.
is connected to the power supply terminal ■DD, the source (6) of p-MO8TB is connected to the electric terminal vS, and the gate 1 of both biO8T and B is connected to the common G input terminal 1N, and both MO8T
The drains of +4+ and +6+ of A- and B are commonly connected to the output terminal OUT.
さて、MGSTの面、圧仁シャンクシEンWdE3−と
ゲート電圧とによって大寸り、ゲーt−it化喚の膜厚
は)h常p−MGSTとn−MGSTとで同一であるの
で、第18図の構成では、ジャンクション配圧の低いn
−1、A OS Tのソース°トレイン間耐圧がCM
OS回路の耐圧となる。Now, since the surface of MGST, the thickness of the gate t-it is the same for both p-MGST and n-MGST, In the configuration shown in Figure 18, the junction pressure distribution is low n.
-1, A OS T source ° train breakdown voltage is CM
This becomes the withstand voltage of the OS circuit.
第3図Qこ、第1図の入力端子工Nの°電位をvssに
したときのvDD端子と■S8端子間の敵圧・電流特性
の一例を示す。この条件ではp −M OS ’i″A
は元金にON 状yにあり、n−MO3TBのソース・
ドレイン間に電、圧かかかっている。第3図の1点がn
−MO8TBのソース・ドレイ7 fMJ iit圧(
BV、5)f4す、この状態で電流を流すと図に示すよ
うにY点に振り込む。FIG. 3 shows an example of the pressure/current characteristics between the vDD terminal and the S8 terminal when the potential of the input terminal N in FIG. 1 is set to vss. Under this condition, p −M OS 'i″A
is in ON state y in the principal, and the source of n-MO3TB is
Electricity and pressure are applied between the drains. One point in Figure 3 is n
-MO8TB source/drain 7 fMJ iit pressure (
BV, 5) f4 When current is applied in this state, it is transferred to point Y as shown in the figure.
第2図Cコおいて、n −M OS T Bには、QB
で示す寄生のラテラルnpnj”ランジスタが存在して
おり、そのベース・エミッタ間は抵抗(12)で接続さ
れている。従って、そのコレクタ・エミッタ間の配圧は
BVQER七なり、はぼ、n″′・p−間の耐圧に近い
。In Figure 2 C, n -M OST B has QB
There is a parasitic lateral npnj" transistor shown by , and its base and emitter are connected by a resistor (12). Therefore, the voltage distribution between its collector and emitter is BVQER7, which is n" It is close to the breakdown voltage between ' and p-.
従って、電流値が低い領域では、前に述べたジャンクシ
ョン制圧(こゲート電界が加わる表面部分(M o s
部分)での耐圧”vSDの方が低いので、それによって
ソース・ドレイン間の制圧がき丑る(1点)。しかしな
がら、1点でアバランシェが起こると、寄生nph )
ランジスタ(ujのベース領域にどんどん電子が注入さ
れるので、寄生npn、)ランジスタ(11)の耐圧は
BVCBQに低下する。この点が第3図のY点である。Therefore, in the region where the current value is low, the junction suppression (the surface area to which the gate electric field is applied) (Mos
Since the withstand voltage "vSD" at the point ) is lower, the pressure between the source and drain becomes weaker (1 point). However, if an avalanche occurs at one point, the parasitic nph)
Since more and more electrons are injected into the base region of the transistor (uj), the breakdown voltage of the parasitic npn transistor (11) decreases to BVCBQ. This point is point Y in FIG.
以上説明し7たように、従来の0M08回路の電源耐圧
は、擾り込み現象があり、定常電源電圧として、第3図
のY点に和尚する電圧以上の電圧を印加していると、サ
ージなどによって、第5図のXA(二相労する定圧を越
えるこ七カ・あると、撮り込み現象によって〜、素子の
電源制圧がY点Gこ相当する′電圧1で下り、素子が破
壊するという問題があつた。また、ソース・ドレイン間
かアバランシェ・ブレークダウンすると、ゲート中に電
子や正孔か注入され光子か劣化するという問題がおった
。As explained above, the power supply breakdown voltage of the conventional 0M08 circuit has a sag phenomenon, and if a voltage higher than the voltage that is applied to the Y point in Figure 3 as a steady power supply voltage is applied, a surge will occur. If the constant pressure exceeds XA (two-phase pressure) in Figure 5, the power supply pressure of the element will drop at voltage 1 corresponding to point Y and G due to the capturing phenomenon, and the element will be destroyed. There was also the problem that when avalanche breakdown occurred between the source and drain, electrons and holes were injected into the gate and photons were degraded.
この発明は以−ヒのよりな点に鑑みてなされたもので、
n−(p−) fil板上に作るp(r)−MoSTの
バルクを高(低)電位に接続するためのn+(p+)形
拡散域とp−(n−)形アイランド上に作るn(p)
−MGSTのバルクを低(高)電位に接続するだめのp
″−(nl)形拡散域とを接触させてツェナーダイオー
ドを形成させ、このツェナー′(社)圧をn(p)−M
GSTのソース・ドレイン耐圧(低電γにを域(こおけ
る)より低くして、振り込与現象をなくして、実菫、的
に↑ゼ源耐jJEの大きいcpAos ICを提供する
ものである。This invention was made in view of the following points,
An n+ (p+) type diffusion region to connect the bulk of p(r)-MoST made on the n-(p-) fil board to a high (low) potential and an n-type diffusion region made on the p-(n-) type island. (p)
-p for connecting the bulk of the MGST to a low (high) potential;
'-(nl) type diffusion region to form a Zener diode, and this Zener'(nl) pressure is n(p)-M
The GST source/drain breakdown voltage (low voltage γ) is lower than the range, eliminating the transfer phenomenon, and providing a cpAos IC with a high current breakdown voltage (JJE). .
第4図はこの発明の一実殊、例の構造を示す断面図で、
第2図の従来例と同等一部分は同一符号で示し、その説
明は省略する。FIG. 4 is a cross-sectional view showing the structure of an example of this invention.
Portions equivalent to those in the conventional example shown in FIG. 2 are designated by the same reference numerals, and their explanations will be omitted.
第4図において、(8a)はp−MO8TAのベルクを
高電位を源端子■IIDに接続するための、従来例Oこ
おける(8]に対応するn″形コンタクト層であるか、
この実施列では、このn+形コンタクト層(8a)は、
n−MO8TBのバルクを低電位電源端子vssに接続
するためのp+形コンタクト層(7)と接するように形
成されており、岡者間に形成されるツェナーダイオード
θ3)のツェナー電圧を、−n、−MGSTのソース・
ドレイン間のアバランシェ耐圧(第5図の1点)よ′り
低くしておくと、アバランシェ・ブレークダウン力)発
生しないので、従来例で述べた寄生npn )ランジス
タ(11)のBVCIOに電源制圧が振り込pことはな
く、実買上の0M06回路の電源制圧を上げることかで
きる。In FIG. 4, (8a) is an n'' type contact layer corresponding to (8) in the conventional example O for connecting the high potential of the p-MO8TA belt to the source terminal ■IID.
In this implementation, this n+ type contact layer (8a) is
It is formed so as to be in contact with the p+ type contact layer (7) for connecting the bulk of n-MO8TB to the low potential power supply terminal vss, and the Zener voltage of the Zener diode θ3) formed between the electrodes is set to -n , - MGST source
If the avalanche breakdown voltage is set lower than the avalanche breakdown voltage (point 1 in Figure 5) between the drains, avalanche breakdown force will not occur, so the power supply suppression will be applied to the BVCIO of the parasitic npn transistor (11) mentioned in the conventional example. There is no need to transfer money, and you can increase the power supply pressure of the 0M06 circuit actually purchased.
上記実施例ではn形基板にp−形アイランドを形成した
場合を示したか、p形基板にn−形アイランドを形成し
た場合についても、同様にこの発明は適用できる。Although the above embodiments have shown the case where a p-type island is formed on an n-type substrate, the present invention can be similarly applied to a case where an n-type island is formed on a p-type substrate.
以上詳述したように、この発明になるCMO8工Cでは
p −M OS T C7)バルクを高几7位点Gこ接
続するためのΩ1形領塚と、n−MGSTのバルクを低
電位点に接続するためのp+形領領域を接触させ、その
ツェナー電圧をM OS Tのソース・ドレイン耐圧よ
り低くなるよう(こしたので、実質上の成諒耐圧を太き
ぐすることかで!X、MO8Tの劣化を防止できる。As described in detail above, in the CMO 8 construction according to the present invention, the Ω1 type region for connecting the p-MOST C7) bulk to the high voltage point G7 and the bulk of the n-MGST to the low potential point are used. The p+ type regions for connection are brought into contact, and the Zener voltage is lower than the source/drain breakdown voltage of the MOST. can prevent deterioration.
第1図はCM OS回路の最小単位を示す回路図、第2
図はこの回路構成を実際(こ実現したCMO8工Cの従
来例を示す断面図、第3図はこの従来例におけるvDD
−759間の電圧・電流特性を示す図、第4図4jこ
の発明の一実施例の構造を示す断面図である。
図において、(])はn−形基板、(2)はp−形アイ
ランド、(7)はp4−影領域、(8a)はn+形領領
域(13)はツェナーダイオード、Aはp−MO6TX
Bはn−MO8Tである。
なお、図中同一符号は同一または相当部分を示す。
代理人 葛 野 信 −(外1名)
特許庁長官殿
16事件の表示 1.1脩i昭58−34157号
2 発明の名称 相補形MO8集積回路装置3 補
正をする者
代表者片山仁へ部
4代理人
5、補正の対象
明細書の発明の詳細な説明の欄および図面の第2図。
6、補正の内容
(1) 明細書の第2頁第12行に「nチャネルMO
8TJとあるのを「nチャネルMO8)シンジスタ」と
訂正する。
(2) 図面の渠2図を絵付図の通りに訂正する。
?、添添付部類目録
訂正後の第2図を示す図面 1通以上Figure 1 is a circuit diagram showing the minimum unit of a CMOS circuit;
The figure is a cross-sectional view showing a conventional example of CMO8-C that has actually realized this circuit configuration, and Figure 3 shows the vDD in this conventional example.
4j is a cross-sectional view showing the structure of an embodiment of the present invention. In the figure, (]) is an n-type substrate, (2) is a p-type island, (7) is a p4-shadow region, (8a) is an n+-type region (13) is a Zener diode, and A is a p-MO6TX.
B is n-MO8T. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Director of the Japan Patent Office Indication of Case 16 1.1 Shui No. 1983-34157 2 Title of invention Complementary MO8 integrated circuit device 3 Representative of the person making the amendment Hitoshi Katayama Department 4 Agent 5, Detailed explanation column of the invention of the specification subject to amendment and FIG. 2 of the drawings. 6. Contents of amendment (1) In the 2nd page, line 12 of the specification, “n-channel MO
8TJ is corrected to ``n-channel MO8) synister.'' (2) Correct the culvert 2 on the drawing to match the illustrated drawing. ? , one or more drawings showing Figure 2 after the correction of the attached catalog of categories
Claims (1)
たp(またはn)チャネルMO8)ランジスタと、上記
半導体基板内のp−(またはn−)形アイランドに形成
されたn(捷たはp)チャネルMO8)ランジスタとを
直列に接続されてなるものにおいて、上記p(tたはn
)チャネルMO8)ランジスタのバルクを高(または低
)電位点に接続するためのn+c−)、たはp+)影領
域と、上記n (またはp)チャネルMOSトランジス
タのバルクを低(′1:たは高)電位点に接続するため
のp+(iたはn+)影領域とを互いに接するように形
成してツェナーダイオードを構成せしめ、当該ツェナー
ダイオードのツェナー電圧を上記n(−f7こはp)チ
ャネルMOSトランジスタのソース・ドレイン間耐圧よ
り低くなるようにしたことを特徴とする相補形MO8果
績回路装置。11) A p (or n) channel MO8) transistor formed on an n- (or p-) type semiconductor substrate, and an n (or n) channel MO8) transistor formed on a p- (or n-) type island in the semiconductor substrate. or p) channel MO8) transistor connected in series, the above p(t or n
) Channel MO8) An n+c-) or p+) shadow region for connecting the bulk of the transistor to a high (or low) potential point and a low ('1: A Zener diode is constructed by forming p+ (i or n+) shadow regions in contact with each other to connect to a potential point (high), and the Zener voltage of the Zener diode is set to the above n(-f7). A complementary MO8 circuit device characterized in that the breakdown voltage between the source and drain of a channel MOS transistor is lower than that of a channel MOS transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58034157A JPS59158546A (en) | 1983-02-28 | 1983-02-28 | Complementary type metal oxide semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58034157A JPS59158546A (en) | 1983-02-28 | 1983-02-28 | Complementary type metal oxide semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59158546A true JPS59158546A (en) | 1984-09-08 |
JPH0532908B2 JPH0532908B2 (en) | 1993-05-18 |
Family
ID=12406364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58034157A Granted JPS59158546A (en) | 1983-02-28 | 1983-02-28 | Complementary type metal oxide semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59158546A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01122153A (en) * | 1987-11-05 | 1989-05-15 | Fuji Electric Co Ltd | Cmos semiconductor circuit device |
JPH02369A (en) * | 1987-11-24 | 1990-01-05 | Nec Corp | Semiconductor device |
EP0357410A2 (en) * | 1988-09-01 | 1990-03-07 | Fujitsu Limited | Semiconductor integrated circuit device |
WO2011104773A1 (en) * | 2010-02-25 | 2011-09-01 | パナソニック株式会社 | Non-volatile semiconductor storage device |
-
1983
- 1983-02-28 JP JP58034157A patent/JPS59158546A/en active Granted
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01122153A (en) * | 1987-11-05 | 1989-05-15 | Fuji Electric Co Ltd | Cmos semiconductor circuit device |
JPH02369A (en) * | 1987-11-24 | 1990-01-05 | Nec Corp | Semiconductor device |
JP2508826B2 (en) * | 1987-11-24 | 1996-06-19 | 日本電気株式会社 | Semiconductor device |
EP0357410A2 (en) * | 1988-09-01 | 1990-03-07 | Fujitsu Limited | Semiconductor integrated circuit device |
US5391904A (en) * | 1988-09-01 | 1995-02-21 | Fujitsu Limited | Semiconductor delay circuit device |
WO2011104773A1 (en) * | 2010-02-25 | 2011-09-01 | パナソニック株式会社 | Non-volatile semiconductor storage device |
JP2011176163A (en) * | 2010-02-25 | 2011-09-08 | Panasonic Corp | Nonvolatile semiconductor storage device |
US8928056B2 (en) | 2010-02-25 | 2015-01-06 | Panasonic Intellectual Property Management Co., Ltd. | Nonvolatile semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPH0532908B2 (en) | 1993-05-18 |
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