JP2021145026A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000010410 layer Substances 0.000 claims abstract description 412
- 238000002347 injection Methods 0.000 claims abstract description 125
- 239000007924 injection Substances 0.000 claims abstract description 125
- 230000001629 suppression Effects 0.000 claims abstract description 77
- 239000002344 surface layer Substances 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims description 128
- 239000000758 substrate Substances 0.000 claims description 44
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- 229910000838 Al alloy Inorganic materials 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 238000011084 recovery Methods 0.000 abstract description 51
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000000243 solution Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 23
- 239000011229 interlayer Substances 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000006378 damage Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- -1 for example Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Abstract
Description
図1から図4を用いて実施の形態1に係る半導体装置の構成を説明する。図1および図2は実施の形態1に係る半導体装置を示す平面図である。図2は、図1に記載のA部を拡大した図であり、半導体基板の第1主面側の構造を示す平面図である。図2において、半導体基板の第1主面より上側に設けられる電極等の記載は省略している。図3および図4は実施の形態1に係る半導体装置を示す断面図である。図3(a)は図2に記載のB−B線での断面図であり、図3(b)は図2に記載のC−C線での断面図である。図4は図2に記載のD−D線での断面図である。図1から図4には説明の便宜上のために方向を示すXYZ直交座標軸も示している。
図16および図17を用いて実施の形態2に係る半導体装置の構成を説明する。図16は実施の形態2に係る半導体装置を示す平面図である。図17は実施の形態2に係る半導体装置を示す平面図である。図17は、図16に記載のF部を拡大した図であり、半導体基板の第1主面側の構造を示す平面図である。図17において、半導体基板の第1主面より上側に設けられる電極等の記載は省略している。図16および図17には説明の便宜上のために方向を示すXYZ直交座標軸も示している。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図18および図19を用いて実施の形態3に係る半導体装置の構成を説明する。図18は実施の形態3に係る半導体装置を示す平面図である。図19は実施の形態3に係る半導体装置を示す平面図である。図19は、図18に記載のG部を拡大した図であり、半導体基板の第1主面側の構造を示す平面図である。図19において、半導体基板の第1主面の上に設けられる電極等の記載は省略している。図18および図19には説明の便宜上のために方向を示すXYZ直交座標軸も示している。なお、実施の形態3において、実施の形態1および実施の形態2で説明したものと同一の構成要素については同一符号を付して説明は省略する。
2 ダイオード領域
6a ゲート絶縁膜
7 ゲート電極
8 エミッタ層
9 ベース層
10 キャリア注入抑制層
11 アノード層
12 ドリフト層
13 コレクタ層
15 カソード層
20 ダイオード領域
21 キャリア注入抑制層
22 アノード層
30 ダイオード領域
31 キャリア注入抑制層
32 アノード層
S1 第1主面
S2 第2主面
W1 キャリア注入抑制層の幅
W2 エミッタ層の幅
W3 キャリア注入抑制層の幅
W4 キャリア注入抑制層の幅
P1 アノード層とキャリア注入抑制層とが繰り返し配置された1周期の幅
P2 ベース層とエミッタ層とが繰り返し配置された1周期の幅
Claims (11)
- 第1主面と前記第1主面に対向する第2主面との間に第1導電型のドリフト層を有する半導体基板に、絶縁ゲート型バイポーラトランジスタ領域とダイオード領域とが隣接して設けられた半導体装置であって、
前記絶縁ゲート型バイポーラトランジスタ領域は、
前記半導体基板の前記第1主面側の表層に設けられた第2導電型のベース層と、
前記ベース層の前記第1主面側の表層に選択的に設けられ、平面視にて第1方向に短手方向を有する第1導電型のエミッタ層と、
前記半導体基板の前記第1主面側に設けられ、ゲート絶縁膜を介して前記エミッタ層、前記ベース層および前記ドリフト層に面するゲート電極と、
前記半導体基板の前記第2主面側の表層に設けられた第2導電型のコレクタ層と、を備え、
前記ダイオード領域は、
前記半導体基板の前記第1主面側の表層に設けられた第2導電型のアノード層と、
前記アノード層の前記第1主面側の表層に選択的に設けられ、平面視にて第2方向に短手方向を有する第1導電型のキャリア注入抑制層と、
前記半導体基板の前記第2主面側の表層に設けられた第1導電型のカソード層と、を備え、
平面視において、前記第2方向における前記キャリア注入抑制層の幅は前記第1方向における前記エミッタ層の幅よりも狭い、
半導体装置。 - 前記ゲート電極は前記第1方向に長手方向を有し、
前記第2方向は前記第1方向と同じ方向である、
請求項1に記載の半導体装置。 - 前記ゲート電極は前記第1方向に長手方向を有し、
前記第2方向は前記第1方向と直交する方向である、
請求項1に記載の半導体装置。 - 平面視において、前記ベース層と前記エミッタ層とが前記第1方向に繰り返し配置され、前記アノード層と前記キャリア注入抑制層とが前記第2方向に繰り返し配置されており、
前記アノード層と前記キャリア注入抑制層とが繰り返し配置された1周期の幅は、前記ベース層と前記エミッタ層とが繰り返し配置された1周期の幅よりも狭い、
請求項1から3のいずれか1項に記載の半導体装置。 - 前記絶縁ゲート型バイポーラトランジスタ領域または前記ダイオード領域のいずれか一方または双方が二つ以上設けられ、
平面視において、一つまたは複数の前記絶縁ゲート型バイポーラトランジスタ領域の面積の和は、一つまたは複数の前記ダイオード領域の面積の和よりも広い、
請求項1から4のいずれか1項に記載の半導体装置。 - 前記絶縁ゲート型バイポーラトランジスタ領域の数は前記ダイオード領域の数よりも多い、
請求項5に記載の半導体装置。 - 前記絶縁ゲート型バイポーラトランジスタ領域の面積の和は、前記ダイオード領域の面積の和の1.1倍以上5倍以下である、
請求項1から6のいずれか1項に記載の半導体装置。 - 平面視において、前記第2方向における前記キャリア注入抑制層の幅は、前記第1方向における前記エミッタ層の幅に前記ダイオード領域の面積の和を掛けて、前記絶縁ゲート型バイポーラトランジスタ領域の面積の和で割った幅以下である、
請求項1から7のいずれか1項に記載の半導体装置。 - 前記ベース層は、
前記第1主面側の表層に高不純物濃度ベース層と、
前記高不純物濃度ベース層よりも前記第2主面側に設けられ、前記高不純物濃度ベース層よりも不純物濃度の低い低不純物濃度ベース層と、
を有する、
請求項1から8のいずれか1項に記載の半導体装置。 - 前記アノード層は、
前記第1主面側の表層に高不純物濃度アノード層と、
前記高不純物濃度アノード層よりも前記第2主面側に設けられ、前記高不純物濃度アノード層よりも不純物濃度の低い低不純物濃度アノード層と、
を有する、
請求項1から9のいずれか1項に記載の半導体装置。 - 前記第1主面上にアルミまたはアルミ合金で構成された電極を有し、前記キャリア注入抑制層はチタンもしくはチタン合金を介して前記電極と電気的に接続された、
請求項1から10のいずれか1項に記載の半導体装置。
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