JP2021044432A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2021044432A JP2021044432A JP2019166211A JP2019166211A JP2021044432A JP 2021044432 A JP2021044432 A JP 2021044432A JP 2019166211 A JP2019166211 A JP 2019166211A JP 2019166211 A JP2019166211 A JP 2019166211A JP 2021044432 A JP2021044432 A JP 2021044432A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 239000000463 material Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 230000005684 electric field Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
図1に示すように、本実施形態に係る半導体装置1は、LDMOS(Laterally Double-Diffused MOSFET:横型二重拡散MOSFET)である。半導体装置1においては、半導体部分10と、半導体部分10上に設けられた絶縁体部分20と、絶縁体部分20を介して半導体部分10から離隔したゲート電極30が設けられている。
図2(a)〜(c)並びに図3(a)及び(b)は、本実施形態に係る半導体装置の第1フィールド絶縁膜及び第2フィールド絶縁膜の形成方法を示す断面図である。
本実施形態に係る半導体装置1においては、ゲート電極30をゲート絶縁膜21上だけでなく、第1フィールド絶縁膜22上にも配置している。これにより、半導体部分10内における電界の集中を抑制することができる。
図5は、横軸にX方向における位置をとり、縦軸に電界強度をとって、電界強度分布のデバイスシミュレーション結果を示すグラフである。
図5に示すデバイスシミュレーションにおいては、比較例に係る半導体装置101と、本実施形態に係る半導体装置1に、同じソース・ドレイン間電圧を印加した場合を想定している。
図6に示すように、第2フィールド絶縁膜23を設けた本実施形態の実施例1〜3は、第2フィールド絶縁膜23を設けていない比較例1〜3と比較して、同等のオン抵抗を維持しつつ、耐圧が向上した。
10:半導体部分
11:ウェル層
12:ボディ層
13:ソース層
14:ソースエクステンション層
15:ドリフト層
16:ドレイン層
20:絶縁体部分
21:ゲート絶縁膜
22:第1フィールド絶縁膜
22a、22b:端部
22cx:第1フィールド絶縁膜の中央位置
23:第2フィールド絶縁膜
23a:端部
23cx:第2フィールド絶縁膜の中央位置
24:エッチングストッパ膜
25:サイドウォール
30:ゲート電極
51:レジストパターン
101:半導体装置
Claims (8)
- 第1半導体層と、
前記第1半導体層の一部上に設けられた第1導電形の第2半導体層と、
前記第2半導体層の一部上に設けられ、前記第1半導体層から離隔した第2導電形の第3半導体層と、
前記第1半導体層の他の一部上に設けられた前記第2導電形の第4半導体層と、
前記第3半導体層と前記第4半導体層との間の部分上、及び、前記第4半導体層における前記第2半導体層側の部分上に設けられた第1絶縁膜と、
前記第4半導体層上に設けられ、前記第1絶縁膜に接し、前記第1絶縁膜よりも厚い第2絶縁膜と、
前記第2絶縁膜上に設けられた第3絶縁膜と、
前記第1絶縁膜上、前記第2絶縁膜上、及び、前記第3絶縁膜上に設けられた電極と、
を備えた半導体装置。 - 前記第1絶縁膜から前記第2絶縁膜に向かう第1方向において、前記第3絶縁膜の長さは前記第2絶縁膜の長さよりも短い請求項1記載の半導体装置。
- 前記第3絶縁膜は、前記第2絶縁膜における前記第1絶縁膜側の端部から離隔している請求項2記載の半導体装置。
- 前記第1方向において、前記第3絶縁膜の中央と前記第2絶縁膜における前記第1絶縁膜の反対側の端部との第1距離は、前記第2絶縁膜の中央と前記第2絶縁膜における前記第1絶縁膜の反対側の端部との第2距離と等しいかより短い請求項2または3に記載の半導体装置。
- 前記第2絶縁膜と前記第3絶縁膜との間に設けられ、前記第2絶縁膜の材料及び前記第3絶縁膜の材料とは異なる材料からなる第4絶縁膜をさらに備えた請求項1〜4のいずれか1つに記載の半導体装置。
- 前記第1絶縁膜、前記第2絶縁膜、及び、前記第3絶縁膜はシリコン酸化物からなり、前記第4絶縁膜はシリコン窒化物からなる請求項5記載の半導体装置。
- 前記第2絶縁膜における前記第1絶縁膜側の端部は、前記第1絶縁膜に近いほど薄い請求項1〜6のいずれか1つに記載の半導体装置。
- 前記第3半導体層はソース層を有し、
前記第4半導体層は、
ドリフト層と、
不純物濃度が前記ドリフト層の不純物濃度よりも高いドレイン層と、
を有し、
前記第2絶縁膜の下部は、前記ソース層と前記ドレイン層との間に配置された請求項1〜7のいずれか1つに記載の半導体装置。
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JP2019166211A JP7216629B2 (ja) | 2019-09-12 | 2019-09-12 | 半導体装置 |
CN201911356238.7A CN112490288A (zh) | 2019-09-12 | 2019-12-25 | 半导体装置 |
US16/816,783 US11322608B2 (en) | 2019-09-12 | 2020-03-12 | Semiconductor device |
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JP2002270830A (ja) * | 2001-03-12 | 2002-09-20 | Fuji Electric Co Ltd | 半導体装置 |
JP2004152979A (ja) * | 2002-10-30 | 2004-05-27 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
US20070057293A1 (en) * | 2005-09-13 | 2007-03-15 | Ching-Hung Kao | Ultra high voltage mos transistor device |
JP2009117670A (ja) * | 2007-11-07 | 2009-05-28 | Oki Semiconductor Co Ltd | 半導体素子およびその製造方法 |
JP2009277741A (ja) * | 2008-05-13 | 2009-11-26 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
JP2009283784A (ja) * | 2008-05-23 | 2009-12-03 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
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JPS59161871A (ja) | 1983-02-16 | 1984-09-12 | ノ−ザン・テレコム・リミテツド | 高電圧金属オキサイド半導体トランジスタ |
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TWI476926B (zh) * | 2012-12-25 | 2015-03-11 | Richtek Technology Corp | 橫向雙擴散金屬氧化物半導體元件製造方法 |
US9184282B2 (en) * | 2013-08-09 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ultra-high voltage laterally-diffused MOS devices and methods of forming the same |
JP6688653B2 (ja) * | 2016-03-30 | 2020-04-28 | エイブリック株式会社 | 半導体装置および半導体装置の製造方法 |
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JP2002270830A (ja) * | 2001-03-12 | 2002-09-20 | Fuji Electric Co Ltd | 半導体装置 |
JP2004152979A (ja) * | 2002-10-30 | 2004-05-27 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
US20070057293A1 (en) * | 2005-09-13 | 2007-03-15 | Ching-Hung Kao | Ultra high voltage mos transistor device |
JP2009117670A (ja) * | 2007-11-07 | 2009-05-28 | Oki Semiconductor Co Ltd | 半導体素子およびその製造方法 |
JP2009277741A (ja) * | 2008-05-13 | 2009-11-26 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
JP2009283784A (ja) * | 2008-05-23 | 2009-12-03 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
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