JP7148440B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7148440B2 JP7148440B2 JP2019040448A JP2019040448A JP7148440B2 JP 7148440 B2 JP7148440 B2 JP 7148440B2 JP 2019040448 A JP2019040448 A JP 2019040448A JP 2019040448 A JP2019040448 A JP 2019040448A JP 7148440 B2 JP7148440 B2 JP 7148440B2
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- 239000004065 semiconductor Substances 0.000 title claims description 87
- 239000010410 layer Substances 0.000 claims description 247
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 description 49
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 28
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- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
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- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Insulated Gate Type Field-Effect Transistor (AREA)
Description
以下、本発明の実施形態について説明する。
図1は、本実施形態に係る半導体装置を示す平面図である。
図2は、図1に示すA-A’線による断面図である。
なお、各図は模式的なものであり、適宜誇張及び省略して描かれている。また、図間において、構成要素の寸法比等は必ずしも一致していない。後述する他の図についても、同様である。
図3~図14は、本実施形態に係る半導体装置の製造方法を示す断面図である。
図3~図14は、図2に示す断面に相当する断面を示す。
本実施形態においては、図12に示す工程において、LOCOS膜31におけるドレイン領域D側の端部31dを覆うように、レジストパターン66を形成する。そして、レジストパターン66をマスクとしてRIE等のエッチングを施すことにより、スペーサ絶縁膜65を選択的に除去して、スペーサ絶縁膜35を形成する。このため、スペーサ絶縁膜35は、レジストパターン66の直下域に形成される。また、LOCOS膜31の端部31dは、レジストパターン66によって保護されるため、エッチングされない。そして、図13に示す工程において、スペーサ絶縁膜35をマスクとして不純物を注入することにより、n+形ドレイン層25を形成する。これにより、n+形ドレイン層25は、n形LDD層24におけるスペーサ絶縁膜35によって覆われていない部分の上層部に形成される。
次に、比較例について説明する。
図15は、本比較例に係る半導体装置を示す断面図である。
10:半導体基板
11:p形基板
12:n形埋込層
13:p形エピタキシャル層
14:ディープn形ウェル
15:n形ドリフト層
16:p形ウェル
20:p+形層
21:n形LDD層
22:n+形ソース層
23:シリサイド層
24:n形LDD層
25:n+形ドレイン層
26:シリサイド層
27:n形LDD層
28:n+形コンタクト層
29:シリサイド層
31:LOCOS膜
31c:中央部
31d、31s:端部
32:ゲート電極
32d、32s:端部
33:ゲート絶縁膜
34:シリサイド層
35、36:スペーサ絶縁膜
37:シリコン酸化層
38:シリコン窒化層
39:シリコン酸化層
41:LOCOS膜
50:層間絶縁膜
51:ソースコンタクト
52:ドレインコンタクト
53:ボディコンタクト
55:ソース電極
56:ドレイン電極
57:ボディ電極
61:シリコン酸化層
62:ポリシリコン層
63:シリコン窒化層
63a:開口部
64:ダミー酸化層
65:スペーサ絶縁膜
66:レジストパターン
101:半導体装置
135:スペーサ絶縁膜
BC:ボディコンタクト領域
D:ドレイン領域
DR:ドリフト長
S:ソース領域
tc、td、ts:厚さ
x0:オーバーラップ量
X:水平方向の変位量
Y:垂直方向の変位量
Claims (7)
- ソース領域及びドレイン領域を有する半導体部分と、
前記ソース領域と前記ドレイン領域との間に配置され、下部が前記半導体部分内に設けられ、上部が前記半導体部分上に設けられた第1絶縁部と、
前記ソース領域側の端部が前記半導体部分における前記第1絶縁部に覆われていない部分上に配置され、前記ドレイン領域側の端部が前記第1絶縁部上に配置されたゲート電極と、
前記ゲート電極における前記ドレイン領域側の端部上、前記第1絶縁部における前記ゲート電極に覆われていない部分上、及び、前記ドレイン領域における前記第1絶縁部側の端部上に連続的に設けられ、前記ゲート電極、前記第1絶縁部及び前記ドレイン領域に接した第2絶縁部と、
を備え、
前記第2絶縁部は、
前記ゲート電極、前記第1絶縁部及び前記ドレイン領域に接し、シリコン酸化物からなる第1層と、
前記第1層上に設けられ、シリコン窒化物からなる第2層と、
前記第2層上に設けられ、シリコン酸化物からなる第3層と、
を有した半導体装置。 - 前記ゲート電極の前記ソース領域側の端面上、及び、前記ソース領域の前記ゲート電極側の端部上に設けられた第3絶縁部をさらに備え、
前記第3絶縁部は、
前記ゲート電極及び前記ソース領域に接し、シリコン酸化物からなる第4層と、
前記第4層に接し、シリコン窒化物からなる第5層と、
前記第5層に接し、シリコン酸化物からなる第6層と、
を有した請求項1に記載の半導体装置。 - ソース領域及びドレイン領域を有する半導体部分と、
前記ソース領域と前記ドレイン領域との間に配置され、下部が前記半導体部分内に設けられ、上部が前記半導体部分上に設けられた第1絶縁部と、
前記ソース領域側の端部が前記半導体部分における前記第1絶縁部に覆われていない部分上に配置され、前記ドレイン領域側の端部が前記第1絶縁部上に配置されたゲート電極と、
前記ゲート電極における前記ドレイン領域側の端部上、前記第1絶縁部における前記ゲート電極に覆われていない部分上、及び、前記ドレイン領域における前記第1絶縁部側の端部上に連続的に設けられ、前記ゲート電極、前記第1絶縁部及び前記ドレイン領域に接した第2絶縁部と、
前記ゲート電極の前記ソース領域側の端面上、及び、前記ソース領域の前記ゲート電極側の端部上に設けられた第3絶縁部と、
を備え、
前記第3絶縁部は、
前記ゲート電極及び前記ソース領域に接し、シリコン酸化物からなる第4層と、
前記第4層に接し、シリコン窒化物からなる第5層と、
前記第5層に接し、シリコン酸化物からなる第6層と、
を有した半導体装置。 - 前記第1絶縁部の前記ソース領域側の端部、及び、前記第1絶縁部の前記ドレイン領域側の端部は、前記第1絶縁部における前記ソース領域側の端部と前記ドレイン領域側の端部との間の中央部よりも薄い請求項1~3のいずれか1つに記載の半導体装置。
- 前記第1絶縁部の前記ソース領域側の端部及び前記ドレイン領域側の端部は、先端に向かうほど薄い請求項1~4のいずれか1つに記載の半導体装置。
- 前記ソース領域及び前記ドレイン領域は第1導電形であり、
前記半導体部分は、
前記ソース領域に接し、第2導電形である第1半導体層と、
前記ドレイン領域、前記第1絶縁部及び前記第1半導体層に接し、第1導電形である第2半導体層と、
をさらに有した請求項1~5のいずれか1つに記載の半導体装置。 - 前記半導体部分上、前記第1絶縁部上、前記ゲート電極上、及び、前記第2絶縁部上に設けられた層間絶縁膜を更に備え、
前記第1絶縁部は前記層間絶縁膜から離隔している請求項1~6のいずれか1つに記載の半導体装置。
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US16/551,493 US11362208B2 (en) | 2019-03-06 | 2019-08-26 | Semiconductor device having an insulator between source and drain regions and a gate electrode having a portion that covers the insulator and a portion that does not cover the insulator |
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US20080213965A1 (en) | 2006-12-27 | 2008-09-04 | Chul Jin Yoon | Method for manufacturing dmos device |
WO2011161748A1 (ja) | 2010-06-21 | 2011-12-29 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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WO2011161748A1 (ja) | 2010-06-21 | 2011-12-29 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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