JP2019532499A - 接合電界効果トランジスタと統合されたデバイスおよび該デバイスを製造するための方法 - Google Patents
接合電界効果トランジスタと統合されたデバイスおよび該デバイスを製造するための方法 Download PDFInfo
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Abstract
Description
Claims (18)
- 接合電界効果トランジスタ(JFET)と統合されたデバイスであって、前記デバイスが、JFET領域と電源デバイス領域とに分割されており、前記デバイスが、
第1の伝導型を有するドレインであり、一部分が前記JFET領域内に配置され、他の部分が前記電源デバイス領域内に配置されているドレインと、
前記ドレインの前面に配置された第1の伝導型領域であり、一部分が前記JFET領域内に配置され、他の部分が前記電源デバイス領域内に配置されている第1の伝導型領域と
を備え、前記JFET領域が、
前記第1の伝導型領域内に形成された、第2の伝導型を有する第1のウェルと、
前記第1の伝導型領域内に形成された、第2の伝導型を有する第2のウェルであり、イオン濃度が前記第1のウェルのイオン濃度よりも高く、前記第1の伝導型が前記第2の伝導型とは反対である第2のウェルと、
前記第1の伝導型を有するJFETソースと、
前記JFETソース上に形成された金属電極であり、前記JFETソースと接触した金属電極と、
前記JFETソースおよび前記第2のウェルの下に形成された第2の伝導型埋込み層と
を備えることを特徴とするデバイス。 - 請求項1に記載のデバイスであって、
前記JFET領域を前記電源デバイス領域から分離するために前記JFET領域と前記電源デバイス領域との間の境界に配置された分離ウェルをさらに備える
ことを特徴とするデバイス。 - 請求項2に記載のデバイスであって、前記JFET領域が、JFET金属ゲートおよびJFETゲートオーム接点をさらに備え、前記JFET金属ゲートが、前記JFETゲートオーム接点上に、前記JFETゲートオーム接点と接触して形成されており、前記JFETゲートオーム接点が、前記JFET領域の前記第1のウェルおよび前記第2のウェル内ならびに前記分離ウェル内に形成されており、それぞれの前記JFETゲートオーム接点が、前記JFET金属ゲートを介して互いに等電位で接続されていることを特徴とするデバイス。
- 請求項3に記載のデバイスであって、前記第2の伝導型埋込み層が、少なくとも前記JFET領域の前記第1のウェルと接触していることを特徴とするデバイス。
- 請求項1に記載のデバイスであって、前記JFETソースが、前記JFET領域の前記第2のウェルと前記JFET領域の前記第2のウェルと隣り合った前記JFET領域の前記第1のウェルとの間に形成されていることを特徴とするデバイス。
- 請求項1に記載のデバイスであって、垂直二重拡散金属酸化物半導体電界効果トランジスタ(VDMOS)であることを特徴とするデバイス。
- 請求項6に記載のデバイスであって、前記電源デバイス領域が、
ゲートと、
第2のウェルと、
前記電源デバイス領域の前記第2のウェル内に配置された、前記第1の伝導型を有するVDMOSソースと、
前記電源デバイス領域の前記第2のウェル内の前記VDMOSソースの下に配置された非クランプ誘導性スイッチング領域であり、前記第2の伝導型を有し、イオン濃度が前記電源デバイス領域の前記第2のウェルのイオン濃度よりも高い、非クランプ誘導性スイッチング領域と
を備えることを特徴とするデバイス。 - 請求項7に記載の接合電界効果トランジスタと統合されたデバイスであって、前記ゲートの下の2つのそれぞれの側に前記電源デバイス領域の1つの第2のウェルが存在し、前記電源デバイス領域の前記2つの第2のウェル内に前記VDMOSソースが形成されており、前記電源デバイス領域の前記2つの第2のウェルのうちのそれぞれのウェル内で前記VDMOSソースが2つのブロックに分割されており、前記デバイスがさらに、前記VDMOSソースの前記2つのブロック間に形成された前記第2の伝導型のオーム接点領域を備えることを特徴とするデバイス。
- 請求項1に記載のデバイスであって、前記第1の伝導型がN型であり、前記第2の伝導型がP型であり、前記第1の伝導型領域がN型エピタキシャル層であることを特徴とするデバイス。
- 請求項9に記載のデバイスであって、前記N型エピタキシャル層が、第1のN型領域と、前記第1のN型領域上の第2のN型領域とを含むことを特徴とするデバイス。
- 請求項10に記載のデバイスであって、前記N型エピタキシャル層の厚さが4ミクロンから7ミクロンの間であることを特徴とするデバイス。
- 接合電界効果トランジスタ(JFET)と統合されたデバイスを製造するための方法であって、前記デバイスが、JFET領域および電源デバイス領域を含み、前記方法が、
その上に第1の伝導型領域が形成された、第1の伝導型の基板を用意するステップと、
前記JFET領域の前記第1の伝導型領域内に第2の伝導型埋込み層を形成するステップであり、前記第1の伝導型が前記第2の伝導型とは反対であるステップと、
前記第1の伝導型領域に前記第2の伝導型のイオンを注入し、ドライブインにより前記第1の伝導型領域内に前記JFET領域の第1のウェルを形成するステップと、
前記第1の伝導型領域の表面にフィールド酸化物層およびゲート酸化物層を順番に成長させ、前記第1の伝導型領域の前記表面にポリシリコン層を形成するステップと、
前記第1の伝導型領域に前記第2の伝導型の前記イオンを注入し、ドライブインにより前記JFET領域の複数の第2のウェルを形成するステップと、
前記第1の伝導型のイオンを注入して、前記JFET領域にJFETソースを形成し、前記電源デバイス領域に電源デバイスソースを形成するステップと、
コンタクトホールをフォトエッチングおよびエッチングし、金属層を堆積させ、前記コンタクトホールに前記金属層を充填して、前記JFETソースの金属電極、JFET金属ゲートおよび前記電源デバイスソースの金属接点をそれぞれ形成するステップと
を含むことを特徴とする方法。 - 請求項12に記載の方法であって、前記第1の伝導型領域内に分離ウェルを形成する前記ステップが、前記JFET領域と前記電源デバイス領域との間の境界に、前記分離ウェルを、前記JFET領域と前記電源デバイス領域との分離物として形成することを含むことを特徴とする方法。
- 請求項12に記載の方法であって、前記第1の伝導型領域が、第1のエピタキシャル層および第2のエピタキシャル層を含み、前記JFET領域の前記第1の伝導型領域内に前記第2の伝導型埋込み層を形成する前記ステップが、前記第1のエピタキシャル層をフォトエッチングすること、前記第2の伝導型の前記イオンを注入すること、およびドライブインにより前記第2の伝導型埋込み層を形成することを含み、前記第1の伝導型領域に前記第2の伝導型の前記イオンを注入し、ドライブインにより前記第1の伝導型領域内に前記第1のウェルを形成する前記ステップの前に、前記方法がさらに、前記第1のエピタキシャル層の表面に前記第2のエピタキシャル層を形成するステップを含み、前記第2の伝導型埋込み層が少なくとも前記JFET領域の前記第1のウェルと接触することを特徴とする方法。
- 請求項12に記載の方法であって、前記第1の伝導型領域に前記第2の伝導型の前記イオンを注入し、ドライブインにより前記JFET領域の前記複数の第2のウェルを形成する前記ステップの後、前記第1の伝導型の前記イオンを注入する前記ステップの前に、注入障壁層を形成するステップと、前記JFET領域の前記第2のウェルに前記第2の伝導型の前記イオンを注入して、非クランプ誘導性スイッチング領域を形成するステップとをさらに含み、前記非クランプ誘導性スイッチング領域の注入エネルギーが、前記第1の伝導型の前記イオンを注入する前記ステップの注入エネルギーよりも大きいことを特徴とする方法。
- 請求項12に記載の方法であって、前記JFET領域に前記JFETソースを形成し、前記電源デバイス領域に前記電源デバイスソースを形成する前記ステップの後、前記コンタクトホールをフォトエッチングおよびエッチングする前記ステップの前に、前記第2の伝導型の前記イオンを注入して、前記JFET領域の前記第1のウェルおよび前記第2のウェル内にJFETゲートオーム接点を形成し、前記電源デバイス領域の前記第2のウェル内にオーム接点領域を形成するステップをさらに含むことを特徴とする方法。
- 請求項12に記載の方法であって、前記第1の伝導型がN型であり、前記第2の伝導型がP型であり、前記デバイスが、垂直二重拡散金属酸化物半導体電界効果トランジスタ(VDMOS)であることを特徴とする方法。
- 請求項12に記載の方法であって、前記第1の伝導型領域に前記第2の伝導型の前記イオンを注入し、ドライブインする前記ステップにおいて、注入濃度が1.5E13cm−2から2.2E13cm−2の間であり、
前記第1の伝導型領域内に前記第1のウェルを形成する前記ステップにおいて、形成された前記第1のウェルのウェル深さが8.5ミクロンから13.5ミクロンの間である
ことを特徴とする方法。
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