JP2019201228A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 239000002184 metal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
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- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
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Abstract
Description
図1は実施形態1に係る半導体装置に用いるスタンダードセルが複数個隣接して配置されたレイアウト構成例を示す平面図である。具体的には、それぞれにフィン型トランジスタを含む5個のスタンダードセル10,20A,20B,20C,30が、第1方向としての図面横方向(X方向)において隣接して配置されている。図1および他の平面図では、フィンとその上に形成されたゲートとによって、フィン型トランジスタが構成されている。ローカル配線は、平面視でフィンまたはゲートと重なる部分において、フィンまたはゲートの上層に接して形成されており、電気的に接続されている。メタル配線はローカル配線の上層に位置しており、コンタクトを介してローカル配線と接続されている。なお、図1では図の見やすさのために、フィンにハッチを付している。ただし、ゲートの下に位置する部分についてはハッチを省いている。また、ローカル配線およびメタル配線にも種類が異なるハッチを付しており、メタル配線とローカル配線とがコンタクトで接続された部分を黒く塗りつぶして示している。他の平面図においても同様である。
図5は実施形態2に係るスタンダードセルのレイアウトの一例を示す平面図である。
図6は実施形態3に係るスタンダードセルのレイアウトの一例を示す平面図である。
以上、本出願において開示する技術の例示として、実施形態1〜3を説明した。しかしながら本開示における技術はこれに限定されず、適宜、変更、置き換え、付加、省略などを行った実施形態にも適用可能である。以下、その他の実施形態を例示する。
20A,20B,20C,20D スタンダードセル(第1のスタンダードセル、第2のスタンダードセル)
40,50,50A,50B,50C スタンダードセル
11a,11b,11c,12a,12b,12c アクティブフィン(第1のフィン)
21a,21b,21c,22a,22b,22c,23a,23b,23c,24a,24b,24c ダミーフィン(第1のフィン、第2のフィン)
31a,31b,31c,32a,32b,32c アクティブフィン(第1のフィン)
41a,41b,41c アクティブフィン(第1のアクティブフィン)
43a,43b,43c アクティブフィン(第2のアクティブフィン)
51a,51b,52a,52b,52c ダミーフィン(第1のダミーフィン)
53a,53b,54a,54b,54c ダミーフィン(第2のダミーフィン)
61,62 容量素子
61a,61b,62a,62b,62c ダミーフィン(容量フィン)
71,72 オフトランジスタ
71a,71b,72a,72b,72c ダミーフィン(オフトランジスタフィン)
AR45,AR46 論理機能領域(導電型領域)
AR47 非アクティブフィン領域
AR53 論理機能領域
Claims (15)
- フィン型トランジスタを含むスタンダードセルを有する半導体装置であって、
前記スタンダードセルは、
第1方向に延びており、かつ前記スタンダードセルの前記第1方向における一方の端に沿って、前記第1方向と直交する第2方向に並べて配置された複数の第1のアクティブフィンと、
前記第1方向に延びており、かつ前記スタンダードセルの前記第1方向における他方の端に沿って、前記第2方向に並べて配置された複数の第2のアクティブフィンとを含んでおり、
前記第2方向において隣接して配置された2つの導電型領域を有し、一方の導電型領域において、前記複数の第1のアクティブフィンと、前記複数の第2のアクティブフィンとの間において、アクティブフィンが配置されていない非アクティブフィン領域が存在し、
他方の導電型領域において、前記非アクティブフィン領域と前記第1方向において同一位置に第3のアクティブフィンが配置されており、前記第3のアクティブフィンは前記第2方向に延びる少なくとも一つの第1のゲート配線と直交する、
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記一方の導電型領域において前記複数の第1のアクティブフィンと前記複数の第2のアクティブフィンは前記第2方向において対応する位置に配置されている、
ことを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記一方の導電型領域において前記複数の第1のアクティブフィンは前記第2方向に延びる少なくとも一つの第2のゲート配線と直交し、
前記一方の導電型領域において前記複数の第2のアクティブフィンは前記第2方向に延びる少なくとも一つの第3のゲート配線と直交する、
ことを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記第2のゲート配線、前記第1のゲート配線および前記第3のゲート配線は前記第1方向に所定のピッチで配置されている、
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記他方の導電型領域においてアクティブフィンが前記スタンダードセルの両端部間に延びている、
ことを特徴とする半導体装置。 - フィン型トランジスタを含むスタンダードセルを有する半導体装置であって、
前記スタンダードセルは、
第1方向に延びており、かつ前記スタンダードセルの前記第1方向における一方の端に沿って、前記第1方向と直交する第2方向に並べて配置された複数の第1のアクティブフィンと、
前記第1方向に延びており、かつ前記スタンダードセルの前記第1方向における他方の端に沿って、前記第2方向に並べて配置された複数の第2のアクティブフィンとを含んでおり、
前記第2方向において隣接して配置された2つの導電型領域を有し、一方の導電型領域において、前記複数の第1のアクティブフィンと、前記複数の第2のアクティブフィンとの間において、アクティブフィンが配置されていない非アクティブフィン領域が存在し、
他方の導電型領域において、前記非アクティブフィン領域と前記第1方向において同一位置に第3のアクティブフィンが配置されており、前記第3のアクティブフィンは前記第2方向に延びる少なくとも一つの第1のゲート配線と直交し、
前記非アクティブフィン領域に前記第2方向に延びる少なくとも一つの第2のゲート配線が配置される、
ことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記一方の導電型領域において前記複数の第1のアクティブフィンと前記複数の第2のアクティブフィンは前記第2方向において対応する位置に配置されている、
ことを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記一方の導電型領域において前記複数の第1のアクティブフィンは前記第2方向に延びる少なくとも一つの第3のゲート配線と直交し、
前記一方の導電型領域において前記複数の第2のアクティブフィンは前記第2方向に延びる少なくとも一つの第4のゲート配線と直交する、
ことを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記第3のゲート配線、前記第2のゲート配線および前記第4のゲート配線は前記第1方向に所定のピッチで配置されている、
ことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記他方の導電型領域においてアクティブフィンが前記スタンダードセルの両端部間に延びている、
ことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記非アクティブフィン領域に前記スタンダードセルの論理機能に寄与しないダミーフィンを備える、
ことを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
前記一方の導電型領域において前記複数の第1のアクティブフィンと前記複数の第2のアクティブフィンは前記第2方向において対応する位置に配置されている、
ことを特徴とする半導体装置。 - 請求項12記載の半導体装置において、
前記一方の導電型領域において前記複数の第1のアクティブフィンは前記第2方向に延びる少なくとも一つの第3のゲート配線と直交し、
前記一方の導電型領域において前記複数の第2のアクティブフィンは前記第2方向に延びる少なくとも一つの第4のゲート配線と直交する、
ことを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
前記第3のゲート配線、前記第2のゲート配線および前記第4のゲート配線は前記第1方向に所定のピッチで配置されている、
ことを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
前記他方の導電型領域においてアクティブフィンが前記スタンダードセルの両端部間に延びている、
ことを特徴とする半導体装置。
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US20160190138A1 (en) | 2016-06-30 |
US11114437B2 (en) | 2021-09-07 |
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JPWO2015033490A1 (ja) | 2017-03-02 |
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CN108922887A (zh) | 2018-11-30 |
US9871040B2 (en) | 2018-01-16 |
US20200235099A1 (en) | 2020-07-23 |
US10242985B2 (en) | 2019-03-26 |
WO2015033490A1 (ja) | 2015-03-12 |
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US10651175B2 (en) | 2020-05-12 |
JP6281572B2 (ja) | 2018-02-21 |
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