JP6495145B2 - 半導体装置 - Google Patents
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Description
[半導体装置の全体構成]
図1は、第1の実施形態による半導体装置の概略構成を示すブロック図である。図1では、半導体装置1の例としてマイクロコンピュータチップを例に挙げている。図1を参照して、半導体装置1は、CPU(Central Processing Unit)2と、メモリ回路3と、インターフェース(I/O:Input and Output)回路4と、図示しないその他の周辺回路と、これらの構成要素間を接続するための内部バス5とを含む。
図2は、図1のメモリ回路の構成を示すブロック図である。図2を参照して、メモリ回路3は、メモリセルアレイ10と、入出力回路11と、ワード線ドライバ12と、制御回路13とを含む。メモリ回路3を構成する各トランジスタはフィンFETで構成されている。
以下、図2のメモリ回路3の入出力回路11におけるタイミング制御の問題について説明する。
TH=delay(CLK)−delay(D) …(1)
TH=DLY(CLK;Tr)+DLY(CLK;wire)−n×DLY(D;Tr)−DLY(D;line) …(2)
まず最初に、フィンFETの構成およびその製造方法について簡単に説明する。
以上のフィンFETの構造に基づいて、図2のデータバッファ31,33、遅延線32、およびフリップフロップ34が構成される。
上記のようにデータ信号Dの経路に遅延線32を設け、ゲート配線Gを含んで遅延線32を構成することによって、データパスの配線長をより長くすることができる。従来のデータバッファのみで遅延時間を調整する場合に比べて全体の回路面積を小さくすることができる。
図11は、第2の実施形態の半導体装置においてメモリ回路の構成を示すブロック図である。図11のメモリ回路3における入出力回路11は、クロック信号CLKの伝送用のクロックパス25の途中に、リピーターバッファ21を挿入した点で図2の入出力回路11と異なる。具体的に図11では、データ信号D[63]用のフリップフロップ34[63]とデータ信号D[64]用のフリップフロップ34[64]との間にリピーターバッファ21が設けられている。リピーターバッファ21によってクロックバッファ20によって整形されたクロック信号CLKがさらに整形される。図11のその他の点は図2の場合と同様であるので、同一または相当する部分には同一の参照符号を付して説明を繰返さない。
図12は、第3の実施形態の半導体装置においてメモリ回路の構成を示すブロック図である。図12のメモリ回路3における入出力回路11は、クロックパス25がツリー状に構成されている点で図2の入出力回路11と異なる。すなわち、第3の実施形態の場合には、クロック信号CLKはツリー状の信号経路を通って複数のフリップフロップ34[0]〜34[127]に入力される。クロック信号CLKの分岐点にはリピーターバッファが設けられる。
図13は、第4の実施形態の半導体装置においてメモリ回路の構成を示すブロック図である。図13のメモリ回路3における入出力回路11は、クロックバッファ20のデータ出力ノードから各フリップフロップ34のクロック入力ノードに至るクロック信号の経路長が長くなるほど、データ出力ノードに接続される遅延線32の遅延時間を長くしている点で、図2の入出力回路11と異なる。具体的に図13の場合、データ信号D[127]用の遅延線32[127]の遅延時間が最も長く、データ信号D[0]用の遅延線32[0]の遅延時間が最も短い。遅延線32の遅延時間は、遅延線の経路長を長くするほど、もしくは、接続される容量素子の数または容量値が増加するほど増加する。図13のその他の点は図2の場合と同様であるので、同一または相当する部分には同一の参照符号を付して説明を繰返さない。
Claims (12)
- 半導体基板上に形成され、データ信号を受けるためのデータ入力ノードとクロック信号を受けるためのクロック入力ノードとを含み、フィン型電界効果トランジスタで構成された論理回路と、
前記半導体基板上に形成され、前記論理回路の前記データ入力ノードと接続されたデータ出力ノードを含み、フィン型電界効果トランジスタで構成されたデータバッファとを備え、
前記データバッファの前記データ出力ノードから前記論理回路の前記データ入力ノードに至る前記データ信号の経路は、前記論理回路および前記データバッファを構成するフィン型電界効果トランジスタのゲート電極と同層のゲート配線を含み、
前記半導体基板を平面視して、前記データ出力ノードから前記データ入力ノードに至る前記データ信号の経路長は、前記データ出力ノードと前記データ入力ノードとの間の直線距離よりも長い、半導体装置。 - 前記データ出力ノードから前記データ入力ノードに至る前記データ信号の経路に接続された容量素子をさらに備え、
前記容量素子は、フィン型電界効果トランジスタのゲート容量を利用して構成されている、請求項1に記載の半導体装置。 - 前記データ出力ノードから前記データ入力ノードに至る前記データ信号の経路は、
複数の前記ゲート配線と、
隣り合う前記ゲート配線間を接続するローカル配線とを含む、請求項1に記載の半導体装置。 - 前記論理回路は、D型フリップフロップまたはD型ラッチ回路を含む、請求項1に記載の半導体装置。
- 前記データバッファは、インバータを含む、請求項1に記載の半導体装置。
- 前記半導体装置は、
複数の前記論理回路と、
複数の前記論理回路にそれぞれ対応する複数の前記データバッファとを備え、
各前記データバッファは、個別に対応する前記データ信号を受けて、整形後の前記データ信号を対応する前記論理回路に出力し、
各前記論理回路は、共通の前記クロック信号を受ける、請求項1に記載の半導体装置。 - 前記半導体装置は、メモリ回路を備え、
複数の前記論理回路および複数の前記データバッファは、前記メモリ回路の入出力回路に設けられ、
前記入出力回路には、複数の前記データバッファに個別に対応する複数の前記データ信号と共通の前記クロック信号とが入力される、請求項6に記載の半導体装置。 - 前記半導体装置は、
前記クロック信号を整形する第1のクロックバッファと、
前記第1のクロックバッファによって整形された前記クロック信号をさらに整形する第2のクロックバッファとをさらに備え、
前記第1のクロックバッファによって整形された前記クロック信号は、複数の前記論理回路のうちの一部に入力され、
前記第2のクロックバッファによって整形された前記クロック信号は、複数の前記論理回路のうちの残余に入力される、請求項6に記載の半導体装置。 - 前記クロック信号は、ツリー状の信号経路を通って複数の前記論理回路に入力される、請求項6に記載の半導体装置。
- 前記半導体装置は、前記クロック信号を整形するクロックバッファをさらに備え、
各前記論理回路において、前記クロックバッファのクロック出力ノードから前記クロック入力ノードに至る前記クロック信号の経路長が長いほど、対応する前記データバッファの前記データ出力ノードから前記データ入力ノードに至る前記データ信号の経路長は長くなる、請求項6に記載の半導体装置。 - 前記半導体装置は、
前記クロック信号を整形するクロックバッファと、
各前記データバッファの前記データ出力ノードから対応する前記論理回路の前記データ入力ノードに至る前記データ信号の経路にそれぞれ接続された容量素子をさらに備え、
前記容量素子は、フィン型電界効果トランジスタのゲート容量を利用して構成され、
各前記論理回路において、前記クロックバッファのクロック出力ノードから前記クロック入力ノードに至る前記クロック信号の経路長が長いほど、対応する前記データバッファの前記データ出力ノードから前記データ入力ノードに至る前記データ信号の経路に接続された前記容量素子の容量値が大きいかまたは前記容量素子の数が多い、請求項6に記載の半導体装置。 - データ信号を受けるためのデータ入力ノードとクロック信号を受けるためのクロック入力ノードとを含み、フィン型電界効果トランジスタで構成された論理回路と、
前記論理回路の前記データ入力ノードと接続されたデータ出力ノードを含み、フィン型電界効果トランジスタで構成されたデータバッファと、
前記データバッファと前記論理回路との間に設けられた遅延線とを備え、
前記遅延線は、
前記論理回路および前記データバッファを構成するフィン型電界効果トランジスタのフィンと同層に形成され、第1方向に延在するフィン配線と、
前記第1方向と交差する第2方向に延在し、前記フィン型電界効果トランジスタのゲート電極と同層に形成され、前記第1方向に順に並ぶ、第1のゲート配線、第2のゲート配線、および第3のゲート配線とを含み、
前記第2のゲート配線は、前記フィン配線とゲート絶縁膜を介在して接続され、
前記遅延線は、さらに、
前記第1および第2のゲート配線間に設けられ、前記フィン配線と接続され、基準電位が与えられる第1のローカル配線と、
前記第2および第3のゲート配線間に設けられ、前記フィン配線と接続され、前記基準電位が与えられる第2のローカル配線とを含み、
前記論理回路の前記データ入力ノードと前記データバッファの前記データ出力ノードとは、前記第1〜第3のゲート配線を介して接続される、半導体装置。
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