JP2018022854A - 半導体装置および半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 238000004519 manufacturing process Methods 0.000 title claims description 18
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- 239000012535 impurity Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 50
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- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 69
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 68
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- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
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Abstract
【解決手段】炭化珪素半導体装置は、n+型炭化珪素基板1のおもて面に設けられた、n型ドリフト層2を有し、n型ドリフト層2の表面層に第1p+型領域3が設けられ、n+型炭化珪素基板1のおもて面側には、トレンチ16が形成される。第1p+型領域3は、トレンチ16の底部より深い位置にある深い第1p+型領域3aとトレンチ16の底部より浅い位置にある浅い第1p+型領域3bからなり、浅い第1p+型領域3bの不純物濃度は、深い第1p+型領域3aの不純物濃度よりも低い。
【選択図】図1
Description
図1は、実施の形態にかかる炭化珪素半導体装置の構成を示す断面図である。図1に示すように、実施の形態にかかる炭化珪素半導体装置は、n+型炭化珪素基板(第1導電型のワイドバンドギャップ半導体基板)1の第1主面(おもて面)、例えば(0001)面(Si面)に、n型ドリフト層(第1導電型の第1ワイドバンドギャップ半導体層)2が堆積されている。
次に、実施の形態にかかる炭化珪素半導体装置の製造方法について説明する。図5〜図10は、実施の形態にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。
2 n型ドリフト層
2a 第1n型ドリフト層
2b 第2n型ドリフト層
3 第1p+型領域
3a 深い第1p+型領域
3b 浅い第1p+型領域
4 第2p+型領域
5 n型エピタキシャル層
5a 第1n型エピタキシャル層
5b 第2n型エピタキシャル層
6 p型ベース層
7 n+型ソース領域
8 p++型コンタクト領域
9 ゲート絶縁膜
10 ゲート電極
11 層間絶縁膜
12 ソース電極
13 裏面電極(ドレイン電極)
14 ソース電極バッド
15 ドレイン電極パッド
16 トレンチ
Claims (5)
- シリコンよりもバンドギャップが広い半導体からなる第1導電型のワイドバンドギャップ半導体基板と、
前記ワイドバンドギャップ半導体基板のおもて面に設けられた、シリコンよりもバンドギャップが広い半導体からなる、前記ワイドバンドギャップ半導体基板より低不純物濃度の第1導電型のワイドバンドギャップ半導体層と、
前記第1導電型のワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板側に対して反対側の表面層に選択的に設けられた第2導電型の第1ベース領域と、
前記第1導電型のワイドバンドギャップ半導体層の内部に選択的に設けられた第2導電型の第2ベース領域と、
前記第1導電型のワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面に設けられた、シリコンよりもバンドギャップが広い半導体からなる、第2導電型のワイドバンドギャップ半導体層と、
前記第2導電型のワイドバンドギャップ半導体層の内部に選択的に設けられた第1導電型のソース領域と、
前記ソース領域および前記第2導電型のワイドバンドギャップ半導体層を貫通して前記第1導電型のワイドバンドギャップ半導体層に達するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第2導電型のワイドバンドギャップ半導体層および前記ソース領域に接触するソース電極と、
前記ワイドバンドギャップ半導体基板の裏面に設けられたドレイン電極と、
を備え、
前記第1ベース領域は、前記トレンチの底部よりも前記ドレイン電極側に深い位置にある深い第1ベース領域および前記トレンチの底部よりも前記ソース領域側に近い位置にある浅い第1ベース領域を有し、
前記浅い第1ベース領域の不純物濃度は、前記深い第1ベース領域の不純物濃度よりも低いことを特徴とする半導体装置。 - 前記浅い第1ベース領域の不純物濃度は、前記第2導電型のワイドバンドギャップ半導体層の不純物濃度以上であることを特徴とする請求項1に記載の半導体装置。
- 前記浅い第1ベース領域の不純物濃度は、2×1017/cm3以上、4.5×1018/cm3以下であることを特徴とする請求項2に記載の半導体装置。
- 前記浅い第1ベース領域の幅は、前記深い第1ベース領域の幅よりも広いことを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- シリコンよりもバンドギャップが広い半導体からなる第1導電型のワイドバンドギャップ半導体基板のおもて面に、シリコンよりもバンドギャップが広い半導体からなる、前記ワイドバンドギャップ半導体基板より低不純物濃度の第1導電型のワイドバンドギャップ半導体層を形成する工程と、
前記第1導電型のワイドバンドギャップ半導体層の表面層に、第2導電型の第1ベース領域を選択的に形成する工程と、
前記第1導電型のワイドバンドギャップ半導体層の内部に、第2導電型の第2ベース領域を選択的に形成する工程と、
前記第1導電型のワイドバンドギャップ半導体層の表面に、シリコンよりもバンドギャップが広い半導体からなる、第2導電型のワイドバンドギャップ半導体層を形成する工程と、
前記第2導電型のワイドバンドギャップ半導体層の内部に第1導電型のソース領域を選択的に形成する工程と、
前記ソース領域および前記第2導電型のワイドバンドギャップ半導体層を貫通して前記第1導電型のワイドバンドギャップ半導体層に達するトレンチを形成する工程と、
前記トレンチの内部にゲート絶縁膜を介してゲート電極を形成する工程と、
前記第2導電型のワイドバンドギャップ半導体層および前記ソース領域に接するソース電極を形成する工程と、
前記ワイドバンドギャップ半導体基板の裏面にドレイン電極を形成する工程と、
を含み、
前記第1ベース領域を選択的に形成する工程は、前記トレンチの底部よりも前記ドレイン電極側に深い位置にある深い第1ベース領域および前記トレンチの底部よりも前記ソース領域側に近い位置にある浅い第1ベース領域を、前記浅い第1ベース領域の不純物濃度が前記深い第1ベース領域の不純物濃度よりも低くなるように形成することを特徴とする半導体装置の製造方法。
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WO2019186785A1 (ja) * | 2018-03-28 | 2019-10-03 | 三菱電機株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP2020087956A (ja) * | 2018-11-15 | 2020-06-04 | トヨタ自動車株式会社 | スイッチング素子 |
JP2020141105A (ja) * | 2019-03-01 | 2020-09-03 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP6981585B1 (ja) * | 2020-08-25 | 2021-12-15 | 三菱電機株式会社 | 半導体装置、電力変換装置、および半導体装置の製造方法 |
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JP7057555B2 (ja) | 2017-11-29 | 2022-04-20 | 国立研究開発法人産業技術総合研究所 | 半導体装置 |
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