JP2017534187A - デュアルゲート構造の低温多結晶シリコン薄膜トランジスタ及びその製造方法 - Google Patents
デュアルゲート構造の低温多結晶シリコン薄膜トランジスタ及びその製造方法 Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 108
- 230000009977 dual effect Effects 0.000 title claims abstract description 33
- 239000010409 thin film Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 51
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 3
- 108091006146 Channels Proteins 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- -1 SiNx Chemical compound 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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Abstract
Description
Claims (10)
- 基板と、
前記基板上のバリア層内に位置し、ボトムゲートを構成する少なくとも1つのパターニングされたアモルファスシリコン層と、
前記バリア層に位置するN型金属酸化物半導体と、
前記バリア層に位置するP型金属酸化物半導体と、
を含み、
前記N型金属酸化物半導体は、パターニングされたゲート電極層をトップゲートとして有し、前記少なくとも1つのパターニングされたアモルファスシリコン層で構成する前記ボトムゲートと結合してデュアルゲート構造を形成するデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。 - 前記N型金属酸化物半導体は、
第1のパターニングされた多結晶シリコン層と、
内側がそれぞれ前記第1のパターニングされた多結晶シリコン層の2つの外側に接続される2つのN-型層と、
それぞれ前記N-型層の2つの外側に接続される2つのN+型層と、
前記第1のパターニングされた多結晶シリコン層、前記2つのN-型層、前記2つのN+型層、及び前記バリア層に位置するゲート絶縁層と、
を有する請求項1に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。 - 前記P型金属酸化物半導体は、
第2のパターニングされた多結晶シリコン層と、
それぞれ前記第2のパターニングされた多結晶シリコン層の2つの外側に接続される2つのP+型層と、
前記第2のパターニングされた多結晶シリコン層、及び前記2つのP+型層に位置するゲート絶縁層請と、
を有する求項2に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。 - 前記ゲート絶縁層が前記N型金属酸化物半導体の前記パターニングされたゲート電極層と前記第1のパターニングされた多結晶シリコン層とを絶縁して分離することにより、前記第1のパターニングされた多結晶シリコン層にNチャネルを形成させる請求項3に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。
- 前記P型金属酸化物半導体はパターニングされたゲート電極層を有し、前記ゲート絶縁層が前記P型金属酸化物半導体の前記パターニングされたゲート電極層と前記第2のパターニングされた多結晶シリコン層とを絶縁して分離することにより、前記第2のパターニングされた多結晶シリコン層にPチャネルを形成させる請求項4に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。
- 前記パターニングされたゲート電極層及び前記ゲート絶縁層に位置する内側誘電体層と、
前記内側誘電体層及び前記ゲート絶縁層に穿設されている複数のビアホールと、
をさらに含む請求項5に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。 - それぞれ前記ビアホールを介して、前記P型金属酸化物半導体の前記P+型層、及び前記N型金属酸化物半導体の前記N+型層に接続される複数のパターニングされたソース/ドレイン電極、をさらに含む請求項6に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。
- 前記パターニングされたゲート電極層は第1の金属からなり、垂直延伸部を有し、前記垂直延伸部は、前記接続チャネルにより前記第1のパターニングされたアモルファスシリコン層に接続された前記N+型層に接続され、デュアルゲート構造の薄膜トランジスタを形成する請求項7に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタ。
- 基板上に複数のパターニングされたアモルファスシリコン層を形成するステップと、
前記パターニングされたアモルファスシリコン層にバリア層を形成するステップと、
前記バリア層に第1のパターニングされた多結晶シリコン層及び第2のパターニングされた多結晶シリコン層を形成するするステップと、
前記第2のパターニングされた多結晶シリコン層の上面及び側面に第1のフォトレジスト層を塗布するステップと、
前記第1のパターニングされた多結晶シリコン層をドーピングして、Nチャネルを形成するステップと、
前記第2のパターニングされた多結晶シリコン層での前記第1のフォトレジスト層を除去するステップと、
形成されたNチャネルの前記第1のパターニングされた多結晶シリコン層及び前記第2のパターニングされた多結晶シリコン層にゲート絶縁層を形成するステップと、
前記ゲート絶縁層に第2のフォトレジスト層を形成し、前記第2のパターニングされた多結晶シリコン層にP+型層ドーピングを行うステップと、
前記ゲート絶縁層での第2のフォトレジスト層を除去し、前記ゲート絶縁層に第3のフォトレジスト層を塗布するステップと、
露光・現像により、一部の前記第3のフォトレジスト層、一部の前記ゲート絶縁層及び一部の前記バリア層を取り外すことにより、複数の接続チャネルを形成するステップと、
前記複数の接続チャネルにより、前記パターニングされたアモルファスシリコン層の露出部分及び前記第1のパターニングされた多結晶シリコン層の露出部分に、それぞれN+型層ドーピングを行うステップと、
前記ゲート絶縁層に複数のパターニングされたゲート電極層を形成するステップと、
前記複数のパターニングされたゲート電極層を第2の遮光層とし、前記第1のパターニングされた多結晶シリコン層及び前記第2のパターニングされた多結晶シリコン層に、それぞれN-型層ドーピングを行い、ここで、前記第1のパターニングされた多結晶シリコン層に対応するパターニングされたゲート電極層は前記パターニングされたアモルファスシリコン層の前記N+型層に接続して、デュアルゲート構造を形成するステップと、
前記複数のパターニングされたゲート電極層及び前記ゲート絶縁層に内側誘電体層を形成するステップと、
複数の前記内側誘電体層及び前記ゲート絶縁層を通過するビアホールを形成するステップと、
前記複数のビアホールを介して複数のパターニングされたソース/ドレイン電極を形成し、前記複数のパターニングされたソース/ドレイン電極は、それぞれ前記第2のパターニングされた多結晶シリコン層の前記P+型層に接続してP型金属酸化物半導体を形成し、且つ前記第1のパターニングされた多結晶シリコン層の前記N+型層に接続してN型金属酸化物半導体を形成するステップと、
を含むデュアルゲート構造の低温多結晶シリコン薄膜トランジスタの製造方法。 - 金属電極とオーム接触を形成するために、前記パターニングされたアモルファスシリコン層の露出部分にN+型層ドーピングを行う請求項9に記載のデュアルゲート構造の低温多結晶シリコン薄膜トランジスタの製造方法。
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PCT/CN2014/091057 WO2016074204A1 (zh) | 2014-11-11 | 2014-11-14 | 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法 |
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CN104900654B (zh) * | 2015-04-14 | 2017-09-26 | 深圳市华星光电技术有限公司 | 双栅极氧化物半导体tft基板的制作方法及其结构 |
CN106298952B (zh) * | 2015-06-04 | 2023-05-02 | 昆山工研院新型平板显示技术中心有限公司 | 一种oled器件 |
CN106298883B (zh) * | 2015-06-04 | 2020-09-15 | 昆山工研院新型平板显示技术中心有限公司 | 一种薄膜晶体管及其制备方法 |
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EA032825B1 (ru) | 2019-07-31 |
WO2016074204A1 (zh) | 2016-05-19 |
GB201709216D0 (en) | 2017-07-26 |
JP6513210B2 (ja) | 2019-05-15 |
EA201791045A1 (ru) | 2017-08-31 |
KR102080732B1 (ko) | 2020-02-24 |
CN104409512A (zh) | 2015-03-11 |
GB2548279A (en) | 2017-09-13 |
KR20170085070A (ko) | 2017-07-21 |
DE112014007160T5 (de) | 2017-09-21 |
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