WO2018223642A1 - 阵列基板及其制造方法、显示面板以及显示装置 - Google Patents

阵列基板及其制造方法、显示面板以及显示装置 Download PDF

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WO2018223642A1
WO2018223642A1 PCT/CN2017/115424 CN2017115424W WO2018223642A1 WO 2018223642 A1 WO2018223642 A1 WO 2018223642A1 CN 2017115424 W CN2017115424 W CN 2017115424W WO 2018223642 A1 WO2018223642 A1 WO 2018223642A1
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Prior art keywords
electrode
source
substrate
projection
gate electrode
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PCT/CN2017/115424
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English (en)
French (fr)
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李子华
刘静
刘祺
马群
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to JP2018548446A priority Critical patent/JP7403225B2/ja
Priority to US16/065,224 priority patent/US20210193694A9/en
Priority to EP17899227.7A priority patent/EP3640985A4/en
Publication of WO2018223642A1 publication Critical patent/WO2018223642A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present disclosure relates to the field of display technology. More specifically, it relates to an array substrate and a method of manufacturing the same, a display panel, and a display device.
  • TFTs Thin film transistors
  • MOS metal oxide semiconductor
  • An aging process has been proposed to reduce leakage current in the TFT.
  • the Aging process can have new adverse effects, such as burns, added highlights, anomalous displays, and the like.
  • LDD lightly doped drain region
  • a first aspect of the present disclosure provides an array substrate.
  • the array substrate includes: an active layer disposed on a substrate, the active layer including a channel region, source/drain regions disposed on both sides of the channel region, and a channel region disposed in the channel region a lightly doped drain region between the source/drain regions; a gate electrode and a first electrode disposed on the active layer; a first insulating layer disposed on the gate electrode and the first electrode; a blocking portion disposed on the first insulating layer and a second electrode, wherein a projection of the second electrode on the substrate at least partially overlaps a projection of the first electrode on the substrate, a projection coverage of the barrier on the substrate Projection of the lightly doped drain region on the substrate, the projection of the barrier on the substrate does not overlap with the projection of the source/drain region on the substrate, and Wherein, the blocking portion and the second electrode are disposed in the same layer.
  • the barrier has an opening, the projection of the opening on the substrate at least partially overlapping the projection of the gate electrode on the substrate.
  • the width of the lightly doped drain region ranges from about 0.5 um to 1 um.
  • the array substrate further includes: a second insulating layer disposed between the active layer and the gate electrode; passing through the first insulating layer and the second insulating layer a via hole; a source/drain electrode disposed on the first insulating layer, the source/drain electrode being in contact with the source/drain region via the via.
  • the source/drain regions have a doping concentration greater than a doping concentration of the lightly doped drain region, and wherein the source/drain regions have a doping concentration range of about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3 , and the doping concentration of the lightly doped drain region ranges from about 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions/cm 3 .
  • a second aspect of the present disclosure provides a display panel.
  • the display panel includes the array substrate as described above.
  • a third aspect of the present disclosure provides a display device.
  • the display device includes a display panel as described above.
  • a fourth aspect of the present disclosure provides a method of fabricating an array substrate.
  • the manufacturing method of the array substrate includes: forming an active layer on a substrate; forming a gate electrode and a first electrode on the active layer; forming a first on the gate electrode and the first electrode An insulating layer; forming a barrier material layer on the insulating layer; processing the barrier material layer by a patterning process to form a barrier portion and a second electrode, wherein a projection of the second electrode on the substrate At least partially overlapping a projection of the first electrode on the substrate, the barrier being remote from the gate a projection of a portion of the electrode electrode extending outwardly on the substrate is located within a projection of a portion of the active layer that extends outward from a side of the gate electrode on a substrate;
  • the blocking portion is used as a mask, and the active layer is first doped to form source/drain regions on both sides of the channel region of the active layer and disposed in the channel region and the source/ A lightly doped drain region between the
  • the barrier has an opening, the projection of the opening on the substrate at least partially overlapping the projection of the gate electrode on the substrate.
  • the width of the lightly doped drain region ranges from about 0.5 um to 1 um.
  • the doping energy of the first doping is between about 30 KeV and 40 KeV.
  • a doping concentration of the source/drain regions is greater than a doping concentration of the lightly doped drain region, and wherein a doping concentration of the source/drain regions of the source/drain regions The range is about 4.5 x 10 15 to 6 x 10 15 ions/cm 3 , and the doping concentration of the lightly doped drain (LDD) region ranges from about 5 x 10 12 to 4.5 x 10 15 ions/cm 3 .
  • the conductivity type of the channel region is N-type
  • the conductivity type of the lightly doped drain region and the conductivity type of the doped region of the source/drain region are P-type.
  • the method of fabricating the array substrate further includes: forming a second insulating layer on the active layer before forming the gate electrode and the first electrode; forming the source/ After the drain region, a via hole is formed through the first insulating layer and the second insulating layer; a source/drain electrode is formed on the first insulating layer, and the source/drain electrode passes through the via hole Contacting the source/drain regions.
  • forming the gate electrode and the first electrode includes: forming a gate electrode material layer on the second insulating layer; patterning the gate electrode material layer to form the a gate electrode and the first electrode.
  • the method of fabricating the array substrate further includes: doping the active layer with the gate electrode as a mask after forming the gate electrode and the first electrode, To define a channel region of the active layer.
  • FIG. 1(a) is a schematic illustration of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 1(b) is a schematic illustration of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a flow chart showing a method of fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • 6(A)-6(F) are process flow diagrams of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and Its derivatives should involve the public Open the text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • An embodiment of the present disclosure provides an array substrate comprising: an active layer disposed on a substrate, the active layer including a channel region, source/drain regions disposed on both sides of the channel region, and a trench disposed a lightly doped drain region between the track region and the source/drain region; a gate electrode and a first electrode disposed on the active layer; and a first insulating layer disposed on the gate electrode and the first electrode a barrier portion and a second electrode disposed on the first insulating layer, wherein a projection of the second electrode on the substrate at least partially overlaps with a projection of the first electrode on the substrate, the barrier portion being on the substrate a projection overlying the projection of the lightly doped drain region on the substrate, a projection of the barrier on the substrate and a projection of the source/drain region on the substrate Overlap, and wherein the barrier portion and the second electrode layer are disposed in the same layer.
  • the same layer arrangement means that it is formed of the same film layer.
  • FIG. 1(a) is a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • an array substrate according to an embodiment of the present disclosure includes an active layer 11 disposed on a substrate 10, the active layer 11 including a channel region 11C, and two disposed in the channel region 11C.
  • the projection at least partially overlaps the projection of the first electrode 122 on the substrate 10, the projection of the barrier portion 141 on the substrate 10 covers the projection of the lightly doped drain region 11L on the substrate 10, and the blocking portion 141 is on the substrate 10.
  • the projection on the substrate and the projection of the source/drain region 11SD on the substrate 10 do not overlap (in other words, the edge of the barrier portion 141 away from the gate electrode 121 and the gate electrode of the lightly doped drain region 11L
  • the edge of 121 is relatively aligned, and wherein the blocking portion 141 and the second electrode 142 are disposed in the same layer and are of the same material.
  • the edge of the blocking portion away from the gate electrode and the lightly doped drain region are remote from the gate.
  • the extreme edge of the pole means that the outer boundary of the projection of the barrier on the substrate substantially overlaps the outer boundary of the projection of the lightly doped drain region on the substrate.
  • the first electrode and the second electrode form a capacitance to maintain a stable voltage.
  • the capacitance including the first electrode and the second electrode can maintain the stability of the voltage of the driving transistor in one cycle, the current of the OLED in one cycle is also stabilized, thereby ensuring Luminous uniformity and stability of OLEDs.
  • a lightly doped drain region 11L is provided on both sides of the channel region as an example.
  • the position of the lightly doped drain region can be set according to actual needs.
  • the lightly doped drain region may be located only on one side of the channel region.
  • 1(b) shows a case where a region away from the first electrode in the source/drain region is used as a drain, in which case a lightly doped drain may be provided only on a side of the channel region away from the first electrode. Polar zone.
  • the lightly doped drain region only on the side of the channel region close to the first electrode.
  • the leakage current of the thin film transistor can be reduced by providing a lightly doped drain region. Due to the same layer arrangement of the second electrode and the barrier, the two can be formed by a single patterning process. Thus, when the second electrode and the barrier portion are formed, only one mask is used, so that the manufacturing process of the array substrate can be simplified, the yield of production is improved, and the cost is also saved.
  • the blocking portion may have an opening P.
  • the projection of the opening P on the substrate 10 at least partially overlaps the projection of the gate electrode 121 on the substrate 10.
  • the width of the lightly doped drain region (also corresponding to the projection of the edge of the barrier portion 141 away from the gate electrode 121 on the substrate 10 to the projection of the channel region 11C on the substrate 10)
  • the range of d is about 0.5 um to 1 um.
  • the array substrate according to an embodiment of the present disclosure further includes: a second insulating layer 15 disposed between the active layer 11 and the gate electrode 121; passing through the first insulating layer 13 and the second insulating layer Via hole V of layer 15; The source/drain electrodes 16 are disposed on the first insulating layer 13, and the source/drain electrodes 16 are in contact with the source/drain regions 11SD through the vias V.
  • the conductivity type of the channel region may be N-type
  • the doping type of the lightly doped drain region and the conductivity type of the doped region of the source/drain region may be P-type. It can be understood that the doping concentration of the source/drain regions is greater than the doping concentration of the lightly doped drain regions. In one embodiment, the doping concentration of the source/drain regions may range from about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3 , and the doping concentration range of the lightly doped drain (LDD) region may be about 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions / cm 3 .
  • Another aspect of the present disclosure provides a method of fabricating an array substrate.
  • a method of fabricating an array substrate according to an embodiment of the present disclosure includes:
  • S111 using a blocking portion as a mask, performing first doping on the active layer to form source/drain regions on both sides of the channel region of the active layer and disposed in the channel region and the source/drain regions Lightly doped drain region.
  • the barrier may have an opening.
  • the projection of the opening on the substrate at least partially overlaps the projection of the gate electrode on the substrate.
  • the lightly doped drain region (corresponding to the distance d from the projection of the barrier away from the gate electrode on the substrate onto the projection of the channel region on the substrate) is in the range of about 0.5 Um ⁇ 1um.
  • the doping energy of the first doping may be about 30 KeV to 40 KeV.
  • the conductivity type of the channel region may be N-type, and the doping type of the lightly doped drain region and the conductivity type of the doped region of the source/drain region may be P-type.
  • the doping concentration of the source/drain regions may range from about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3
  • the doping concentration of the lightly doped drain (LDD) region may range from about 5 ⁇ 10 12 to 4.5. ⁇ 10 15 ions/cm 3 .
  • the material of the second conductive layer may include at least one of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), and combination.
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • Al aluminum
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • FIG. 5 is a flow diagram of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 5, in an embodiment, the method of manufacturing the array substrate further includes:
  • forming the gate electrode and the first electrode includes: forming a gate electrode material layer on the second insulating layer; patterning the gate electrode material layer to form the gate electrode and the first electrode.
  • 6(A)-6(F) are process flow diagrams of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. A method of fabricating an array substrate according to an embodiment of the present disclosure will be further described below with reference to FIG.
  • a method of fabricating an array substrate according to an embodiment of the present disclosure includes:
  • the substrate may include a glass substrate, and may also include any material suitable for use as a substrate, such as a high molecular polymer, a metal foil, or the like.
  • the active layer may include a silicon material. Since the electron mobility of the low temperature polysilicon material is superior to the electron mobility of the amorphous silicon material, the active layer may be disposed to include a polysilicon material.
  • an amorphous silicon layer may be formed on the substrate, and then the amorphous silicon is subjected to an excimer laser annealing (ELA) process to cause the amorphous silicon to become polycrystalline silicon, and then the polycrystalline silicon is first.
  • ELA excimer laser annealing
  • the first conductivity type is N-type
  • a doping amount of 1 ⁇ 10 12 to 2 ⁇ 10 12 ions/cm 3 can be employed.
  • P-type silicon can be provided and then an N-well can be formed on the P-type silicon.
  • the upper surface of the N well is on the same surface as the upper surface of the P-type silicon.
  • the active layer having the first conductivity type can also be directly provided without the above doping step.
  • a second insulating layer 15 is formed on the active layer 11.
  • the material of the second insulating layer may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), AlOx and combination.
  • a gate electrode 121 and a first electrode 122 are formed on the second insulating layer 15.
  • a gate electrode material layer may be formed on the second insulating layer, and then the gate electrode material layer is patterned to form the gate electrode 121 and the first electrode 122.
  • the gate electrode material layer may include at least one of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), and combinations thereof . Doping of the second conductivity type is then performed using the gate electrode and the first electrode as a mask.
  • the second conductivity type is P-type.
  • a doping amount of 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions/cm 3 may be employed.
  • a first insulating layer 13 is further formed on the gate electrode 121 and the first electrode 122.
  • the material of the first insulating layer may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), AlOx and combination.
  • a barrier material layer 14 is further formed on the first insulating layer 13.
  • the barrier material layer may include at least one of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), and combinations thereof.
  • the barrier material layer 14 is processed by one patterning process to form the barrier portion 141 and the second electrode 142.
  • the specific step may be: forming a photoresist on the barrier material layer, exposing the photoresist with a mask including a pattern of the barrier portion and the second electrode, then performing development, and then using light
  • the resist acts as a protective layer to etch the resistor Block the material layer and finally remove the photoresist.
  • the projection of the second electrode on the substrate at least partially overlaps the projection of the first electrode on the substrate, and the portion of the barrier extending outward from the side of the gate electrode is lining
  • the projection on the bottom is located within the projection of the portion of the active layer that extends outwardly from the side of the gate electrode (in other words, the projection of the edge of the barrier away from the gate electrode on the substrate)
  • the blocking portion may have an opening P.
  • the projection of the opening P on the substrate 10 at least partially overlaps the projection of the gate electrode 121 on the substrate 10.
  • the extent of the distance of the edge of the barrier away from the gate electrode on the substrate projected onto the projection of the channel region on the substrate may be about 0.5 um ⁇ 1um.
  • the active layer 11 is first doped using the blocking portion as a mask 141 to form source/drain regions on both sides of the channel region 11C of the active layer 11.
  • 11SD and a lightly doped drain region 11L disposed between the channel region 11C and the source/drain region 11SD.
  • the conductivity type of the active layer is N-type
  • P-type doping may be employed, so that the conductivity type of the conductive region of the lightly doped drain region and the doped region of the source/drain region formed after the current doping is P type.
  • the doping energy of the doping may be about 30 KeV to 40 KeV.
  • the doping concentration of the source/drain regions is greater than the doping concentration of the lightly doped drain regions.
  • the formed source/drain regions may have a doping concentration ranging from about 4.5 ⁇ 10 15 to 6 ⁇ 10 15 ions/cm 3
  • the lightly doped drain regions may have a doping concentration range of about 5 ⁇ 10 12 to 4.5 ⁇ 10 15 ions / cm 3 .
  • via holes V are formed through the first insulating layer 13 and the second insulating layer 15, and source/drain electrodes 16 are formed on the first insulating layer 13. It can be seen that the source/drain electrodes 16 are in contact with the source/drain regions 11SD via vias V.
  • Embodiments of the present disclosure also provide a display panel and a display device.
  • the display panel in the embodiment of the present disclosure includes the array substrate as described above.
  • Appearance in an embodiment of the present disclosure The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板及其制造方法、显示面板以及显示装置。阵列基板，包括：设置在衬底（10）上的有源层（11），有源层（11）包括沟道区（11C）、设置在沟道区（11C）两侧的源/漏极区域（11SD）以及设置在沟道区（11C）与源/漏极区域（11SD）之间的轻掺杂漏极区（11L）；设置在有源层（11）上的栅极电极（121）和第一电极（122）；设置在栅极电极（121）和第一电极（122）上的第一绝缘层（13）；设置在第一绝缘层（13）上的阻挡部（141）和第二电极（142），第二电极（142）在衬底（10）上的投影与第一电极（122）在衬底（10）上的投影至少部分重叠，阻挡部（141）在衬底（10）上的投影覆盖轻掺杂漏极区（11L）在衬底（10）上的投影，阻挡部（141）在衬底（10）上的投影与源/漏极区域（11SD）在衬底（10）上的投影不交叠，阻挡部（141）和第二电极（142）同层设置。

Description

阵列基板及其制造方法、显示面板以及显示装置
相关申请的交叉引用
本申请要求于2017年06月08日递交的中国专利申请第201710426034.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域。更具体地，涉及一种阵列基板及其制造方法、显示面板以及显示装置。
背景技术
薄膜晶体管(TFT)被广泛应用于显示技术领域。然而，在TFT中会出现掺杂导致的晶体受损区域。该受损区域往往会导致热载流子应力，例如，当电子从源极区域到漏极区域加速时，其可能会穿透栅极绝缘层或金属氧化物半导体(MOS)界面。此外，热载流子应力可能会降低电子迁移率，还可能会增大截止电流。这都会对TFT带来不利影响。
已经提出了采用老化(Aging)工艺来减少TFT中的漏电流。然而，Aging工艺会带来新的不利影响，例如，会导致灼伤、新增亮点、异常显示等。
另外一种已知方案是采用轻掺杂漏极区(LDD)来减少TFT中的漏电流。然而，现有技术中的LDD方案工艺复杂并且设计难度大。
发明内容
本公开文本的第一方面提供了一种阵列基板。所述阵列基板包括：设置在衬底上的有源层，所述有源层包括沟道区、设置在所述沟道区两侧的源/漏极区域以及设置在所述沟道区与所述源/漏极区域之间的轻掺杂漏极区； 设置在所述有源层上的栅极电极和第一电极；设置在所述栅极电极和所述第一电极上的第一绝缘层；设置在所述第一绝缘层上的阻挡部和第二电极，其中，所述第二电极在所述衬底上的投影与所述第一电极在所述衬底上的投影至少部分重叠，所述阻挡部在所述衬底上的投影覆盖所述轻掺杂漏极区在所述衬底上的投影，所述阻挡部在所述衬底上的投影与所述源/漏极区域在所述衬底上的投影不交叠,并且其中，所述阻挡部和所述第二电极同层设置。
在一个实施例中，所述阻挡部具有开口，所述开口在所述衬底上的投影与所述栅极电极在所述衬底上的投影至少部分重叠。
在一个实施例中，所述轻掺杂漏极区的宽度的范围为约0.5um～1um。
在一个实施例中，所述阵列基板进一步包括：设置在所述有源层和所述栅极电极之间的第二绝缘层；穿过所述第一绝缘层和所述第二绝缘层的过孔；设置在所述第一绝缘层上的源/漏极电极，所述源/漏极电极经由所述过孔与所述源/漏极区域接触。
在一个实施例中，所述源/漏极区域的掺杂浓度大于所述轻掺杂漏极区的掺杂浓度，并且其中，所述源/漏极区域的掺杂浓度范围为约4.5×1015～6×1015离子/cm3，所述轻掺杂漏极区的掺杂浓度范围为约5×1012～4.5×1015离子/cm3。
本公开文本的第二方面提供了一种显示面板。所述显示面板包括如上所述的阵列基板。
本公开文本的第三方面提供了一种显示装置。所述显示装置包括如上所述的显示面板。
本公开文本的第四方面提供了一种阵列基板的制造方法。所述阵列基板的制造方法包括：在衬底上形成有源层；在所述有源层上形成栅极电极和第一电极；在所述栅极电极和所述第一电极上形成第一绝缘层；在所述绝缘层上形成阻挡材料层；通过一次构图工艺对所述阻挡材料层进行处理以形成阻挡部和第二电极，其中，所述第二电极在所述衬底上的投影与所述第一电极在所述衬底上的投影至少部分重叠，所述阻挡部的远离所述栅 极电极的一侧向外延伸的部分在所述衬底上的投影位于所述有源层的从所述栅极电极的一侧向外延伸的部分在衬底上的投影之内；利用所述阻挡部做掩膜，对所述有源层进行第一掺杂，以形成位于有源层的沟道区两侧的源/漏极区域和设置在所述沟道区与所述源/漏极区域之间的轻掺杂漏极区。
在一个实施例中，所述阻挡部具有开口，所述开口在所述衬底上的投影与所述栅极电极在所述衬底上的投影至少部分重叠。
在一个实施例中，所述轻掺杂漏极区的宽度的范围为约0.5um～1um。
在一个实施例中，所述第一掺杂的掺杂能量为约30Kev～40Kev。
在一个实施例中，所述源/漏极区域的掺杂浓度大于所述轻掺杂漏极区的掺杂浓度，并且其中，所述源/漏极区域源/漏极区域的掺杂浓度范围为约4.5×1015～6×1015离子/cm3，轻掺杂漏极(LDD)区的掺杂浓度范围为约5×1012～4.5×1015离子/cm3。
在一个实施例中，所述沟道区的导电类型为N型，所述轻掺杂漏极区的导电类型和所述源/漏极区域的掺杂区域的导电类型为P型。
在一个实施例中，所述阵列基板的制造方法进一步包括：在形成所述栅极电极和所述第一电极之前，在所述有源层上形成第二绝缘层；在形成所述源/漏极区域之后，形成穿过所述第一绝缘层和所述第二绝缘层的过孔；在所述第一绝缘层上形成源/漏极电极，所述源/漏极电极经由过孔与所述源/漏极区域接触。
在一个实施例中，形成所述栅极电极和所述第一电极包括：在所述第二绝缘层上形成栅极电极材料层；对所述栅极电极材料层进行构图，以形成所述栅极电极和所述第一电极。
在一个实施例中，所述阵列基板的制造方法还包括：在形成所述栅极电极和所述第一电极之后，利用所述栅极电极作为掩模对所述有源层进行掺杂，以限定所述有源层的沟道区。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1(a)为根据本公开文本的实施例的阵列基板的示意图；
图1(b)为根据本公开文本的实施例的阵列基板的示意图；
图2为根据本公开文本的实施例的阵列基板的示意图；
图3为根据本公开文本的实施例的阵列基板的示意图；
图4为根据本公开文本的实施例的阵列基板的制造方法的流程示意图；
图5为根据本公开文本的实施例的阵列基板的制造方法的流程示意图；
图6(A)-图6(F)为根据本公开文本的实施例的阵列基板的制造方法的工艺流程图。
具体实施方式
为了使本公开文本的实施例的目的、技术方案和优点更加清楚，下面将接合附图，对本公开文本的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开文本保护的范围。
当介绍本公开文本的元素及其实施例时，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公 开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
本公开文本的实施例提供了一种阵列基板，包括：设置在衬底上的有源层，有源层包括沟道区、设置在沟道区两侧的源/漏极区域以及设置在沟道区与所述源/漏极区域之间的轻掺杂漏极区；设置在有源层上的栅极电极和第一电极；设置在栅极电极和第一电极上的第一绝缘层；设置在第一绝缘层上的阻挡部和第二电极，其中，第二电极在衬底上的投影与第一电极在衬底上的投影至少部分重叠，所述阻挡部在所述衬底上的投影覆盖所述轻掺杂漏极区在所述衬底上的投影，所述阻挡部在所述衬底上的投影与所述源/漏极区域在所述衬底上的投影不交叠,并且其中，阻挡部和第二电极层同层设置。这里，同层设置是指由同一膜层形成。
下面将参考附图对本公开文本的实施例做进一步说明。
图1(a)为根据本公开文本的实施例的阵列基板的示意图。如图1(a)所述，根据本公开文本的实施例的阵列基板包括：设置在衬底10上的有源层11，有源层11包括沟道区11C、设置在沟道区11C两侧的源/漏极区域11SD以及设置在沟道区11C与源/漏极区域11SD之间的轻掺杂漏极区11L；设置在有源层11上的栅极电极121和第一电极122；设置在栅极电极121和第一电极122上的第一绝缘层13；设置在第一绝缘层13上的阻挡部141和第二电极142，其中，第二电极142在衬底10上的投影与第一电极122在衬底10上的投影至少部分重叠，阻挡部141在衬底10上的投影覆盖轻掺杂漏极区11L在衬底10上的投影，阻挡部141在衬底10上的投影与源/漏极区域11SD在衬底10上的投影不交叠(换而言之，阻挡部141的远离栅极电极121的边缘与轻掺杂漏极区11L的远离栅极电极121的边缘相对准),并且其中，阻挡部141和第二电极142同层设置且材料相同。这里的“阻挡部的远离栅极电极的边缘与轻掺杂漏极区的远离栅极电 极的边缘相对准”是指阻挡部在衬底上的投影的外侧边界与轻掺杂漏极区在衬底上的投影的外侧边界大体上重叠。
第一电极和第二电极会形成电容，从而保持稳定的电压。例如，当用于OLED结构时，由于包括了第一电极和第二电极的电容可以保持一个周期内的驱动晶体管的电压的稳定，从而使得一个周期内的OLED的电流也稳定，这样，能够保证OLED的发光均匀性和稳定性。
图1(a)中以沟道区的两侧均设置有轻掺杂漏极区11L为示例。然而，可以根据实际需要来设置轻掺杂漏极区的位置。例如，如图1(b)所示，轻掺杂漏极区可以仅位于沟道区的一侧。图1(b)示出以源/漏极区中的远离第一电极的一个区域用作漏极的情况，此时可以仅在沟道区的远离第一电极的一侧设置轻掺杂漏极区。当然，当将源/漏极区中的靠近第一电极的一个区域用作漏极时，也可以仅在沟道区的靠近第一电极的一侧设置轻掺杂漏极区。
通过设置轻掺杂漏极区，可以降低薄膜晶体管的漏电流。由于第二电极和阻挡部的同层设置，二者可以采用一次构图工艺形成。这样，在形成第二电极和阻挡部的时候，仅使用了一道掩模，从而阵列基板的制造工艺能够被简化，生产的良品率得到提高，成本也得到节省。
图2为根据本公开文本的实施例的阵列基板的示意图。如图2所示，阻挡部可以具有开口P。该开口P在衬底10上的投影与栅极电极121在衬底10上的投影至少部分重叠。通过在阻挡部设置这样的开口，可以防止或者减少阻挡部与栅极电极之间可能产生的寄生电容。
在一个实施例中，轻掺杂漏区的宽度(也对应于阻挡部141的远离栅极电极121的边缘在在衬底10上的投影到沟道区11C在衬底10上的投影的距离d)的范围为约0.5um～1um。通过这样的距离设置，可以较好地实现降低晶体管的漏电流。
图3为根据本公开文本的实施例的阵列基板的示意图。如图3所示，根据本公开文本的实施例的阵列基板还包括：设置在有源层11和栅极电极121之间的第二绝缘层15；穿过第一绝缘层13和第二绝缘层15的过孔V； 设置在第一绝缘层13上的源/漏极电极16，源/漏极电极16通过过孔V与源/漏极区域11SD接触。
在一个实施例中，沟道区的导电类型可以为N型，轻掺杂漏极区的掺杂类型和所述源/漏极区域的掺杂区域的导电类型可以为P型。可以理解，源/漏极区域的掺杂浓度大于所述轻掺杂漏极区的掺杂浓度。在一个实施例中，源/漏极区域的掺杂浓度范围可以为约4.5×1015～6×1015离子/cm3，轻掺杂漏极(LDD)区的掺杂浓度范围可以为约5×1012～4.5×1015离子/cm3。
本公开文本的另一方面提供了一种阵列基板的制造方法。
图4为根据本公开文本的实施例的阵列基板的制造方法的流程示意图。如图4所示，根据本公开文本的实施例的阵列基板的制造方法包括：
S101、在衬底上形成有源层；
S103、在有源层上形成栅极电极和第一电极；
S105、在栅极电极和所述第一电极上形成第一绝缘层；
S107、在第一绝缘层上形成阻挡材料层；
S109、通过一次构图工艺对阻挡材料层进行处理以形成阻挡部和第二电极，其中，第二电极在衬底上的投影与第一电极在衬底上的投影至少部分重叠，阻挡部的从栅极电极的一侧向外延伸的部分在衬底上的投影位于有源层的从栅极电极的一侧向外延伸的部分在衬底上的投影之内，
S111、利用阻挡部做掩膜，对有源层进行第一掺杂，以形成位于有源层的沟道区两侧的源/漏极区域和设置在沟道区与源/漏极区域之间的轻掺杂漏极区。
在一个实施例中，阻挡部可以具有开口。该开口在衬底上的投影与栅极电极在衬底上的投影至少部分重叠。通过在阻挡部设置这样的开口，可以防止或者减少阻挡部与栅极电极之间可能产生的寄生电容。
在一个实施例中，轻掺杂漏极区(对应于阻挡部的远离栅极电极的边缘在在衬底上的投影到沟道区在衬底上的投影的距离d)的范围为约0.5um～1um。通过这样的距离设置，可以较好地实现降低晶体管的漏电流。
在一个实施例中，第一掺杂的掺杂能量可以为约30Kev～40Kev。沟道 区的导电类型可以为N型，轻掺杂漏极区的掺杂类型和源/漏极区域的掺杂区域的导电类型可以为P型。源/漏极区域的掺杂浓度范围可以为约4.5×1015～6×1015离子/cm3，轻掺杂漏极(LDD)区的掺杂浓度范围可以为约5×1012～4.5×1015离子/cm3。
第二导电层的材料可以包括下列材料的至少一种：钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)以及其组合。
图5为根据本公开文本的实施例的阵列基板的制造方法的流程示意图。如图5所示在一个实施例中，阵列基板的制造方法进一步包括：
S102、在形成栅极电极和第一电极之前，在有源层上形成第二绝缘层；
S104、在形成栅极电极和第一电极之后，利用栅极电极作为掩模对有源层进行掺杂，以限定有源层的沟道区；
S113、在形成所述源/漏极区域之后，形成穿过第一绝缘层和第二绝缘层的过孔；
S115、在所述第一绝缘层上形成源/漏极电极，其中，源/漏极电极经由过孔与所述源/漏极区域接触。
在一个实施例中，形成栅极电极和所述第一电极包括：在第二绝缘层上形成栅极电极材料层；对栅极电极材料层进行构图，以形成栅极电极和第一电极。
图6(A)-图6(F)为根据本公开文本的实施例的阵列基板的制造方法的工艺流程图。下面将结合图6对根据本公开文本的一个实施例的阵列基板的制造方法做进一步说明。
如图6(A)所述，根据本公开文本的实施例的阵列基板的制造方法包括：
在衬底10上形成有源层11。衬底可以包括玻璃衬底，也可以包括高分子聚合物、金属薄片等适用于做基板的任何材料。有源层可以包括硅材料。由于低温多晶硅材料的电子迁移率优于非晶硅材料的电子迁移率，可以将有源层设置为包括多晶硅材料。在一种实施方式中，可以在衬底上形 成非晶硅层，然后对非晶硅进行准分子激光退火(ELA)处理，以使得非晶硅变成多晶硅，再接着对多晶硅进行具有第一导电类型的掺杂。例如，第一导电类型为N型时，可以采用1×1012～2×1012离子/cm3的掺杂剂量。在一种实施方式中，可以提供P型硅，然后在P型硅上形成N阱。其中该N阱的上表面与P型硅的上表面处于同一表面。当然，可以理解，也可以直接提供具有第一导电类型的有源层而无需上述的掺杂步骤。
接着，在有源层11上形成第二绝缘层15。第二绝缘层的材料可以包括下列的至少一种：硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx及其组合。
然后，在第二绝缘层15上形成栅极电极121和第一电极122。具体地，可以在第二绝缘层上形成栅极电极材料层，然后对栅极电极材料层进行构图，以形成栅极电极121和第一电极122。栅极电极材料层可以包括下列材料的至少一种：钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)以及其组合。然后以栅极电极和第一电极做掩模，进行第二导电类型的掺杂。例如，在有源层的第一导电类型为N型时，第二导电类型为P型。此时，对于P型的第二导电类型的掺杂，可以采用5×1012～4.5×1015离子/cm3的掺杂剂量。
如图6(B)所示，进一步在栅极电极121和第一电极122上形成第一绝缘层13。第一绝缘层的材料可以包括下列的至少一种：硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx及其组合。
如图6(C)所示，进一步在第一绝缘层13上形成阻挡材料层14。阻挡材料层可以包括下列材料的至少一种：钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)及其组合。
然后，如图6(D)所示，通过一次构图工艺对阻挡材料层14进行处理，以形成阻挡部141和第二电极142。例如，具体步骤可以为：在阻挡材料层上形成光致抗蚀剂，用包括阻挡部和第二电极的图形的掩模来曝光该光致抗蚀剂，然后进行显影，再通过用光致抗蚀剂作为保护层来刻蚀阻 挡材料层，最后去除光致抗蚀剂。从图6(D)可以看出，第二电极在衬底上的投影与第一电极在衬底上的投影至少部分重叠，阻挡部的从栅极电极的一侧向外延伸的部分在衬底上的投影位于有源层的从栅极电极的一侧向外延伸的部分在衬底上的投影之内(换而言之，阻挡部的远离栅极电极的边缘在衬底上的投影位于有源层的远离栅极电极的边缘在衬底上的投影与栅极电极的对应边缘在衬底上的投影之间)。在形成阻挡部和第二电极的过程中，仅使用了一道掩模，从而可以简化工艺，节省成本，提高良品率。
阻挡部可以具有开口P。该开口P在衬底10上的投影与栅极电极121在衬底10上的投影至少部分重叠。通过在阻挡部设置这样的开口，可以防止或者减少阻挡部与栅极电极之间可能产生的寄生电容。
阻挡部的远离栅极电极的边缘在在衬底上的投影到沟道区在衬底上的投影的距离的范围(对应于后续形成的轻掺杂漏极区的宽度)可以为约0.5um～1um。通过这样的距离设置，可以较好地实现降低晶体管的漏电流。
然后，如图6(E)所示，利用阻挡部做掩膜141，对有源层11进行第一掺杂，以形成位于有源层11的沟道区11C两侧的源/漏极区域11SD和设置在沟道区11C与源/漏极区域11SD之间的轻掺杂漏极区11L。对于有源层的导电类型为N型的情况，可以采用P型掺杂，从而本次掺杂后形成的轻掺杂漏极区的导电和源/漏极区域的掺杂区域的导电类型为P型。掺杂的掺杂能量可以为约30Kev～40Kev。可以理解，源/漏极区域的掺杂浓度大于所述轻掺杂漏极区的掺杂浓度。在一个实施例中，所形成的源/漏极区域的掺杂浓度范围可以为约4.5×1015～6×1015离子/cm3，轻掺杂漏极区的掺杂浓度范围可以为约5×1012～4.5×1015离子/cm3。
接着，如图6(F)所示，形成穿过第一绝缘层13和第二绝缘层15的过孔V，再在第一绝缘层13上形成源/漏极电极16。可以看出，源/漏极电极16经由过孔V与源/漏极区域11SD接触。
本公开文本的实施例还提供了显示面板和显示装置。本公开文本的实施例中的显示面板包括如上所述的阵列基板。本公开文本的实施例中的显 示装置可以为：手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开文本的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开文本的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开文本范围和精神内的此类形式或者修改。

Claims (17)

  1. 一种阵列基板，包括：设置在衬底上的有源层，所述有源层包括沟道区、设置在所述沟道区两侧的源/漏极区域以及设置在所述沟道区与所述源/漏极区域之间的轻掺杂漏极区；
    设置在所述有源层上的栅极电极和第一电极；
    设置在所述栅极电极和所述第一电极上的第一绝缘层；
    设置在所述第一绝缘层上的阻挡部和第二电极，其中，所述第二电极在所述衬底上的投影与所述第一电极在所述衬底上的投影至少部分重叠，所述阻挡部在所述衬底上的投影覆盖所述轻掺杂漏极区在所述衬底上的投影，所述阻挡部在所述衬底上的投影与所述源/漏极区域在所述衬底上的投影不交叠,并且其中，所述阻挡部和所述第二电极同层设置。
  2. 根据权利要求1所述的阵列基板，其中，所述阻挡部具有开口，所述开口在所述衬底上的投影与所述栅极电极在所述衬底上的投影至少部分重叠。
  3. 根据权利要求2所述的阵列基板，其中，所述轻掺杂漏极区的宽度的范围为约0.5um～1um。
  4. 根据权利要求1-3中任一项所述的阵列基板，所述阵列基板进一步包括：设置在所述有源层和所述栅极电极之间的第二绝缘层；
    穿过所述第一绝缘层和所述第二绝缘层的过孔；
    设置在所述第一绝缘层上的源/漏极电极，所述源/漏极电极经由所述过孔与所述源/漏极区域接触。
  5. 根据权利要求41所述的阵列基板，其中，所述源/漏极区域的掺杂浓度大于所述轻掺杂漏极区的掺杂浓度，并且其中，所述源/漏极区域的掺杂浓度范围为约4.5×1015～6×1015离子/cm3，所述轻掺杂漏极区的掺杂浓度范围为约5×1012～4.5×1015离子/cm3。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，所述有源层包括低温多晶硅。
  7. 一种显示面板，包括根据权利要求1-6中任一项所述的阵列基板。
  8. 一种显示装置，包括根据权利要求7所述的显示面板。
  9. 一种阵列基板的制造方法，包括：在衬底上形成有源层；
    在所述有源层上形成栅极电极和第一电极；
    在所述栅极电极和所述第一电极上形成第一绝缘层；
    在所述第一绝缘层上形成阻挡材料层；
    通过一次构图工艺对所述阻挡材料层进行处理以形成阻挡部和第二电极，其中，所述第二电极在所述衬底上的投影与所述第一电极在所述衬底上的投影至少部分重叠，所述阻挡部的从所述栅极电极的一侧向外延伸的部分在所述衬底上的投影位于所述有源层的从所述栅极电极的一侧向外延伸的部分在衬底上的投影之内；
    利用所述阻挡部做掩膜，对所述有源层进行第一掺杂，以形成位于有源层的沟道区两侧的源/漏极区域和设置在所述沟道区与所述源/漏极区域之间的轻掺杂漏极区。
  10. 根据权利要求9所述的阵列基板的制造方法，所述阻挡部具有开口，所述开口在所述衬底上的投影与所述栅极电极在所述衬底上的投影至少部分重叠。
  11. 根据权利要求10所述的阵列基板的制造方法，所述轻掺杂漏极区的宽度的范围约为0.5um～1um。
  12. 根据权利要求9所述的阵列基板的制造方法，其中，所述第一掺杂的掺杂能量约为30Kev～40Kev。
  13. 根据权利要求9所述的阵列基板的制造方法，其中，所述源/漏极区域的掺杂浓度大于所述轻掺杂漏极区的掺杂浓度，并且其中，所述源/漏极区域的掺杂浓度范围为约4.5×1015～6×1015离子/cm3，所述轻掺杂漏极区的掺杂浓度范围为约5×1012～4.5×1015离子/cm3。
  14. 根据权利要求9所述的阵列基板的制造方法，其中，所述沟道区的导电类型为N型，所述轻掺杂漏极区的导电类型和所述源/漏极区域的掺杂区域的导电类型为P型。
  15. 根据权利要求9-14中任一项所述的阵列基板的制造方法，其中， 所述阵列基板的制造方法进一步包括：在形成所述栅极电极和所述第一电极之前，在所述有源层上形成第二绝缘层；
    在形成所述源/漏极区域之后，形成穿过所述第一绝缘层和所述第二绝缘层的过孔；
    在所述第一绝缘层上形成源/漏极电极，所述源/漏极电极经由过孔与所述源/漏极区域接触。
  16. 根据权利要求15所述的阵列基板的制造方法，其中，形成所述栅极电极和所述第一电极包括：
    在所述第二绝缘层上形成栅极电极材料层；
    对所述栅极电极材料层进行构图，以形成所述栅极电极和所述第一电极。
  17. 根据权利要求9-14中任一项所述的阵列基板的制造方法，其中，所述阵列基板的制造方法还包括：
    在形成所述栅极电极和所述第一电极之后，利用所述栅极电极作为掩模对所述有源层进行掺杂，以限定所述有源层的沟道区。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150028341A1 (en) * 2013-07-12 2015-01-29 Boe Technology Group Co., Ltd. Array Substrate, Display Device, and Method for Manufacturing the Array Substrate
CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4187819B2 (ja) * 1997-03-14 2008-11-26 シャープ株式会社 薄膜装置の製造方法
KR100384672B1 (ko) * 1998-01-30 2003-05-22 가부시키가이샤 히타치세이사쿠쇼 액정 표시 장치
JP2000349297A (ja) 1999-03-10 2000-12-15 Matsushita Electric Ind Co Ltd 薄膜トランジスタ、パネル及びそれらの製造方法
JP5177923B2 (ja) * 2001-06-29 2013-04-10 株式会社半導体エネルギー研究所 半導体装置および電子機器
KR102081283B1 (ko) 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150028341A1 (en) * 2013-07-12 2015-01-29 Boe Technology Group Co., Ltd. Array Substrate, Display Device, and Method for Manufacturing the Array Substrate
CN104681628A (zh) * 2015-03-17 2015-06-03 京东方科技集团股份有限公司 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置

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