WO2019200824A1 - Ltps tft基板的制作方法及ltps tft基板 - Google Patents

Ltps tft基板的制作方法及ltps tft基板 Download PDF

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Publication number
WO2019200824A1
WO2019200824A1 PCT/CN2018/105578 CN2018105578W WO2019200824A1 WO 2019200824 A1 WO2019200824 A1 WO 2019200824A1 CN 2018105578 W CN2018105578 W CN 2018105578W WO 2019200824 A1 WO2019200824 A1 WO 2019200824A1
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Prior art keywords
layer
source
insulating layer
gate
polysilicon active
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PCT/CN2018/105578
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English (en)
French (fr)
Inventor
李立胜
刘广辉
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武汉华星光电技术有限公司
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Priority to US16/097,277 priority Critical patent/US10957713B2/en
Publication of WO2019200824A1 publication Critical patent/WO2019200824A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an LTPS TFT substrate and an LTPS TFT substrate.
  • flat panel display devices such as liquid crystal display (LCD) and active matrix organic light-emitting diode (AMOLED) displays have thin body and high image quality. Power saving, no radiation and many other advantages have been widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens.
  • LCD liquid crystal display
  • AMOLED active matrix organic light-emitting diode
  • Thin Film Transistor (TFT) Array (Array) substrate is the main component of current LCD devices and AMOLED devices. It is directly related to the development direction of high-performance flat panel display devices. It is used to provide driving circuits to displays.
  • the source and drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel electrode, thereby controlling the corresponding pixel region. display.
  • the structure of the thin film transistor on the array substrate further includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, and an insulating protective layer which are stacked on the substrate.
  • low temperature poly-Silicon (LTPS) thin film transistors are more complicated than traditional amorphous silicon (A-Si) thin film transistors, but they are widely used because of their high carrier mobility.
  • LTPS low temperature poly-Silicon
  • A-Si amorphous silicon
  • low-temperature polysilicon is regarded as an important material for low-cost full-color flat panel display.
  • the hot carrier effect is an important failure mechanism of Metal Oxide Semiconductor (MOS) devices. As the size of MOS devices shrinks, the hot carrier injection effect of devices becomes more and more serious.
  • MOS Metal Oxide Semiconductor
  • NMOS N-type metal oxide semiconductor
  • NMOS fabrication process generally adopts a Lightly Doped Drain (LDD) method in which a low-doped region is disposed in the vicinity of the source and drain electrodes in a poly-Poly (Poly-Si) channel to allow the low-doping region. The area is also subject to partial partial pressure.
  • LDD Lightly Doped Drain
  • the commonly used LDD process is MASK (mask) LDD technology and Re-etch (repeated etching) LDD technology.
  • the process of fabricating LTPS array substrate by MASK LDD technology includes the following steps:
  • Step S10 as shown in FIG. 1, a buffer layer 200 and a polysilicon active layer 300 are sequentially formed on the substrate 100, a photoresist is coated on the polysilicon active layer 300, and light is formed by exposure and development through a mask.
  • the resist pattern 980 is formed with the photoresist pattern 980 as a shielding layer, and a high dose of N-type ions (phosphorus ions P+, 1 ⁇ 10 14 to 1 ⁇ 10 15 ions/cm 2 ) is implanted into the polysilicon active layer 300 to form a source and drain.
  • Step S20 stripping and removing the photoresist pattern 980, depositing a gate insulating layer 400 covering the polysilicon active layer 300 on the buffer layer 200, depositing on the gate insulating layer 400 And patterning the first metal layer, forming a gate 500 above the polysilicon active layer 300 corresponding to the channel region to be formed, and using the gate 500 as a shielding layer, implanting a low dose to both ends of the polysilicon active layer 300 N-type ions (P+, 1x10 12 ⁇ 1x10 13 ions / cm 2 ), forming a channel region 320 and an LDD region 330 between the channel region 320 and the source and drain contact regions 310;
  • N-type ions P+, 1x10 12 ⁇ 1x10 13 ions / cm 2
  • Step S30 as shown in FIG. 3, an interlayer insulating layer 600 is deposited on the gate electrode 500 and the gate insulating layer 400, a photoresist is coated on the interlayer insulating layer 600, and a photoresist is formed by exposure and development processing.
  • Step S40 as shown in FIG. 4, the interlayer insulating layer 600 and the gate insulating layer 400 are etched by using the photoresist layer 900 as a shielding layer, and the interlayer insulating layer 600 and the gate insulating layer 400 are etched.
  • a via 650 is formed above the source and drain contact regions 310 corresponding to the two sides of the active layer 300;
  • Step S50 depositing and patterning a second metal layer on the interlayer insulating layer 600 to obtain a source drain 800, the source drain 800 and the active via the via 650
  • the source and drain contact regions 310 on both sides of the layer 300 are in contact.
  • the existing Re-etch LDD technology is compared with the MASK LDD technology described above, after the polysilicon active layer 300 is patterned, the active layer 300 is not heavily doped by the photoresist pattern 980, but the first metal layer is performed.
  • the etching is performed twice, and the heavily doped source-drain contact region 310 is defined by the first etched metal pattern, and the metal pattern is used as a shielding layer, and the polysilicon active layer 300 is heavily doped and implanted high.
  • a dose of N-type ions followed by a second etching of the first metal layer to obtain a gate 500, with the gate 500 as a shielding layer, lightly doping both ends of the polysilicon active layer 300 and implanting a low dose N-type ion.
  • the main advantage of Re-etch LDD technology is to reduce one lithography process, thereby reducing the production cost of a reticle and reducing the processing time of LTPS TFT substrate, increasing production capacity.
  • the main disadvantage is Re-etch.
  • the LDD technology is heavily doped, the N-type ions are required to pass through the gate insulating layer 400. In the range of the process capability of the machine, most of the N-type ions cannot be implanted into the polysilicon active layer 300, resulting in the active layer 300.
  • the ion content in the source and drain contact regions 310 on both sides is low, and the contact resistance with the source and drain electrodes 800 is abnormal, which affects device performance.
  • Another object of the present invention is to provide an LTPS TFT substrate, which can effectively improve the low contact impedance between the source-drain and source-drain contact regions in the Re-etch LDD technology.
  • the present invention first provides a method for fabricating an LTPS TFT substrate, comprising the following steps:
  • Step S1 providing a substrate on which a buffer layer, a polysilicon active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer are sequentially formed from bottom to top;
  • the polysilicon active layer has a source and drain contact region at both ends, a channel region in the middle, and an LDD region between the source and drain contact regions and the channel region;
  • the gate insulating layer is in the buffer layer Overlying the polysilicon active layer;
  • the gate is corresponding to the channel region of the polysilicon active layer on the gate insulating layer;
  • the interlayer insulating layer is on the gate insulating layer Covering the gate;
  • Step S2 applying a photoresist on the interlayer insulating layer, and obtaining a photoresist layer after exposure and development, wherein the photoresist layer has a via pattern corresponding to the source/drain contact region to expose the interlayer Insulation;
  • Step S3 dry etching the interlayer insulating layer and the gate insulating layer with the photoresist layer as a shielding layer, and corresponding to the source and drain electrodes on the interlayer insulating layer and the gate insulating layer Forming a via hole above the contact region to form an undercut structure between the via hole and the photoresist layer, the vertical cross section of the via hole is an inverted trapezoid, and the photoresist layer extends over the via hole to cover The top of the via hole wall;
  • Step S4 depositing a conductive material at the via position, the conductive material forming a conductive layer in contact with the source/drain contact region in the via hole through the photoresist layer, and peeling off the photoresist layer And a conductive material on the photoresist layer;
  • Step S5 depositing and patterning a source and a drain on the interlayer insulating layer, wherein the source and drain are in contact with the conductive layer in the via hole to be in conduction with the source and drain contact regions.
  • the conductive layer deposited in the step S4 is a metal material layer or a metal oxide material layer.
  • the conductive layer deposited in the step S4 is a metal molybdenum layer.
  • the conductive layer deposited in the step S4 is an N-type ion doped amorphous silicon layer.
  • the etching gas for dry etching the interlayer insulating layer and the gate insulating layer in the step S3 comprises oxygen, and the etching gas further comprises one of sulfur hexafluoride, pentafluoroethane and carbon tetrafluoride. Or a variety.
  • the step S1 specifically includes the following steps:
  • Step S11 providing a base substrate, forming a polysilicon layer on the base substrate, patterning the polysilicon layer to obtain a polysilicon active layer, and forming a gate covering the polysilicon active layer on the buffer layer Insulation;
  • Step S12 depositing a metal layer on the gate insulating layer, forming a photoresist pattern on the metal layer corresponding to a middle portion of the polysilicon active layer, wherein the photoresist pattern is a shielding layer, and the metal is The layer is first etched to form a quasi-gate, and the quasi-gate is used as a shielding layer, and a portion of the polysilicon active layer that is not covered by the quasi-gate is heavily doped with an N-type ion to form a polysilicon active layer. Source and drain contact regions at both ends;
  • Step S13 performing a second etching on the metal layer, causing both sides of the quasi-gate to be laterally etched and reduced in width to form a gate, stripping and removing the photoresist pattern, and using the gate as a shielding layer.
  • Step S14 forming an interlayer insulating layer covering the gate on the gate insulating layer.
  • the metal layer is first etched by dry etching, and the etching gas for performing the first etching on the metal layer includes sulfur hexafluoride, pentafluoroethane and carbon tetrafluoride. One or more.
  • the metal layer is etched a second time by dry etching, and the etching gas for performing the second etching on the metal layer contains oxygen and chlorine.
  • the ions doped in the polysilicon active layer in the step S12 and the step S13 are all phosphorus ions;
  • the dopant ion concentration when the polysilicon active layer is heavily doped with N-type ions is 1 ⁇ 10 14 -1 ⁇ 10 15 ions/cm 2 ;
  • the dopant ion concentration when the polysilicon active layer is lightly doped with N-type ions is 1 ⁇ 10 12 -1 ⁇ 10 13 ions/cm 2 .
  • the present invention also provides an LTPS TFT substrate, comprising: a base substrate, a buffer layer disposed on the base substrate, a polysilicon active layer disposed on the buffer layer, and the polysilicon active layer covering the buffer layer a gate insulating layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer covering the gate electrode on the gate insulating layer, and a source and drain provided on the interlayer insulating layer ;
  • the polysilicon active layer has a source-drain contact region at both ends, a channel region in the middle, and an LDD region between the source-drain contact region and the channel region;
  • the gate is located above the channel region of the polysilicon active layer on the gate insulating layer;
  • the interlayer insulating layer and the gate insulating layer are provided with a via hole corresponding to the source/drain contact region, the vertical cross section of the via hole is an inverted trapezoid, and the via hole is provided with a layer and the a conductive layer in contact with the source and drain contact regions and having a U-shaped longitudinal section;
  • the source drain is in contact with the conductive layer in the via and is in conduction with the source and drain contact regions.
  • the conductive layer is a metal material layer or a metal oxide material layer.
  • the LTPS TFT substrate of the present invention is formed by etching a via hole on the interlayer insulating layer and the gate insulating layer corresponding to the source/drain contact region by using a photoresist layer, and peeling off Before removing the photoresist layer, a conductive material is deposited at the via location to form a conductive layer in contact with the source and drain contact regions in the via, and subsequently the source drain is in contact with the conductive layer in the via Furthermore, it is electrically connected to the source-drain contact region, thereby effectively improving the insufficient contact resistance between the source-drain and source-drain contact regions in the Re-etch LDD technology, and further improving the product characteristics without affecting product characteristics.
  • the -etch LDD technology reduces the reticle process and forms an undercut structure between the via and the photoresist layer to prevent the deposited conductive material from affecting the stripping photoresist layer and ensuring the stripping efficiency of the photoresist layer.
  • a via layer in contact with the source/drain contact region is disposed in the via hole above the source/drain contact region, and the source and drain electrodes are in contact with the conductive layer in the via hole to The source-drain contact region is turned on, which can effectively improve the low contact impedance between the source-drain and source-drain contact regions in Re-etch LDD technology.
  • FIG. 1 is a schematic diagram of a step S10 of fabricating an LTPS TFT substrate using MASK LDD technology
  • FIG. 2 is a schematic diagram of a step S20 of fabricating an LTPS TFT substrate by using MASK LDD technology
  • FIG. 3 is a schematic diagram of a step S30 of fabricating an LTPS TFT substrate by using MASK LDD technology
  • FIG. 4 is a schematic diagram of a step S40 of fabricating an LTPS TFT substrate by using MASK LDD technology
  • FIG. 5 is a schematic diagram of a step S50 of fabricating an LTPS TFT substrate by using MASK LDD technology
  • FIG. 6 is a schematic flow chart of a method for fabricating an LTPS TFT substrate of the present invention.
  • step S12 is a schematic diagram of step S12 of the method for fabricating the LTPS TFT substrate of the present invention.
  • step S13 is a schematic diagram of step S13 of the method for fabricating the LTPS TFT substrate of the present invention.
  • step S2 is a schematic diagram of step S2 of the method for fabricating the LTPS TFT substrate of the present invention.
  • step S3 is a schematic diagram of step S3 of the method for fabricating the LTPS TFT substrate of the present invention.
  • 11-12 are schematic diagrams showing the step S4 of the method for fabricating the LTPS TFT substrate of the present invention.
  • FIG. 13 is a schematic view showing a step S5 of the method for fabricating the LTPS TFT substrate of the present invention and a schematic structural view of the LTPS TFT substrate of the present invention.
  • the present invention provides a method for fabricating an LTPS TFT substrate, including the following steps:
  • step S1 the base substrate 10 is provided, and the buffer layer 20, the polysilicon active layer 30, the gate insulating layer 40, the gate electrode 50, and the interlayer insulating layer 60 are sequentially formed on the base substrate 10 from bottom to top.
  • the LTPS TFT substrate is fabricated by using the Re-etch LDD technology, and the step S1 specifically includes the following steps:
  • Step S11 providing a base substrate 10, forming a polysilicon layer on the base substrate 10, patterning the polysilicon layer to obtain a polysilicon active layer 30, and forming a cover polysilicon active on the buffer layer 20.
  • the gate insulating layer 40 of layer 30 is provided.
  • the polysilicon layer is formed by depositing an amorphous silicon layer on the buffer layer 20, and converting the amorphous silicon layer into a polysilicon layer by a low temperature crystallization process.
  • the crystallization process is solid phase crystallization, excimer laser crystallization, rapid thermal annealing, or metal lateral induction.
  • Step S12 as shown in FIG. 7, a metal layer is deposited on the gate insulating layer 40, and a photoresist pattern 98 is formed on the metal layer corresponding to a middle portion of the polysilicon active layer 30, with the photoresist
  • the pattern 98 is a shielding layer, and the metal layer is first etched to form a quasi-gate 51, and the quasi-gate 51 is used as a shielding layer, and the two ends of the polysilicon active layer 30 are not covered by the quasi-gate 51.
  • the portion is heavily doped with N-type ions to form source-drain contact regions 31 across the polysilicon active layer 30.
  • the ions doped in the polysilicon active layer 30 in the step S12 are phosphorus ions, and the doping ion concentration when the polysilicon active layer 30 is heavily doped with N-type ions is 1 ⁇ 10 14 - 1x10 15 ions/cm 2 .
  • the metal layer is first etched by dry etching, and the etching gas for performing the first etching on the metal layer includes sulfur hexafluoride (SF 6 ) and pentafluoroethane.
  • SF 6 sulfur hexafluoride
  • pentafluoroethane One or more of alkane (C 2 HF 5 ) and carbon tetrafluoride (CF 4 ).
  • Step S13 as shown in FIG. 8, the metal layer is etched a second time, so that both sides of the quasi-gate 51 are laterally etched and the width is reduced to form a gate 50, and the photoresist pattern 98 is peeled off.
  • the gate 50 is used as a shielding layer, and N-type ions are lightly doped to a portion of the polysilicon active layer 30 that is not covered by the gate 50, and a corresponding portion of the central portion of the polysilicon active layer 30 is located at the gate.
  • the ions doped in the polysilicon active layer 30 in the step S13 are phosphorus ions, and the doping ion concentration when the polysilicon active layer 30 is lightly doped with N-type ions is 1 ⁇ 10 12 - 1x10 13 ions/cm 2 .
  • the metal layer is subjected to a second etching by dry etching, and the etching gas for performing the second etching on the metal layer contains oxygen (O 2 ) and chlorine.
  • Step S14 forming an interlayer insulating layer 60 covering the gate electrode 50 on the gate insulating layer 40.
  • Step S2 as shown in FIG. 9, a photoresist is applied on the interlayer insulating layer 60, and after exposure and development, a photoresist layer 90 is obtained.
  • the photoresist layer 90 corresponds to the source/drain contact region 31.
  • the upper side has a via pattern 95 to expose the interlayer insulating layer 60.
  • Step S3 dry etching the interlayer insulating layer 60 and the gate insulating layer 40 with the photoresist layer 90 as a shielding layer, and the interlayer insulating layer 60 and the gate electrode
  • a via hole 65 is formed on the insulating layer 40 corresponding to the source/drain contact region 31, so that the via hole 65 and the photoresist layer 90 are formed into an undercut structure, and a longitudinal section of the via hole 65 In an inverted trapezoidal shape, the photoresist layer 90 extends over the via 65 to cover the top of the via wall of the via 65.
  • the etching gas for dry etching the interlayer insulating layer 60 and the gate insulating layer 40 in the step S3 includes oxygen, and the etching gas further includes sulfur hexafluoride, pentafluoroethane, and tetrafluoride.
  • the etching gas is applied to the interlayer insulating layer 60 and the photoresist layer 90 by adjusting the content of oxygen in the etching gas or the denseness of the interlayer insulating layer 60.
  • the selection ratio is etched so that the via 65 and the photoresist layer 90 form an undercut structure as shown in FIG. 10, so that the subsequent photoresist layer 90 is easily peeled off.
  • Step S4 depositing a conductive material at a position of the via hole 64, and the conductive material passes through the photoresist layer 90 to form a contact with the source/drain contact region 31 in the via 65.
  • Contacting the conductive layer 70 peeling off the conductive material on the photoresist layer 90 and the photoresist layer 90, and forming an undercut structure between the via 65 and the photoresist layer 90, the conductive layer 70 and the conductive layer 70
  • the conductive material on the photoresist layer 90 is broken by the photoresist layer 90, so that the deposition of the conductive material does not affect the peeling of the photoresist layer 90.
  • the conductive layer 70 deposited in the step S4 is a metal material layer or a metal oxide material layer, such as a metal molybdenum layer or an N-type ion doped amorphous silicon layer.
  • Step S5 depositing and patterning a source and a drain 80 on the interlayer insulating layer 60, the source and drain electrodes 80 are in contact with the conductive layer 70 in the via 65 and the source and drain contact regions.
  • the 31 phase is turned on.
  • the method for fabricating the LTPS TFT substrate of the present invention is formed by etching the via hole 65 on the interlayer insulating layer 60 and the gate insulating layer 40 corresponding to the source/drain contact region 31 by using the photoresist layer 90, and removing the via hole 65.
  • a conductive material is deposited at the position of the via 65 to form a conductive layer 70 in contact with the source/drain contact region 31 in the via 65, and subsequently the source and drain electrodes 80 and the via 65 are formed.
  • the inner conductive layer 70 is in contact with the source/drain contact region 31, thereby effectively improving the insufficient contact impedance between the source and drain electrodes 80 and the source/drain contact region 31 in the Re-etch LDD technique.
  • a mask process can be reduced by Re-etch LDD technology, and an undercut structure is formed between the via 65 and the photoresist layer 90 to prevent the deposited conductive material from being generated on the stripped photoresist layer 90.
  • the effect is to ensure the peeling efficiency of the photoresist layer 90.
  • the present invention further provides an LTPS TFT substrate, comprising a base substrate 10 , a buffer layer 20 disposed on the base substrate 10 , and a buffer layer 20 disposed on the buffer layer 20 .
  • the polysilicon active layer 30 has a source and drain contact region 31 at both ends, a channel region 32 located in the middle, and an LDD region 33 between the source and drain contact regions 31 and the channel region 32;
  • the gate 50 is located above the channel region 32 of the polysilicon active layer 30 on the gate insulating layer 40;
  • the interlayer insulating layer 60 and the gate insulating layer 40 are provided with a via hole 65 above the source/drain contact region 31.
  • the vertical cross section of the via hole 65 is an inverted trapezoid, and the via hole 65 is inside. Is provided with a conductive layer 70 in contact with the source and drain contact regions 31 and having a U-shaped longitudinal section;
  • the source and drain electrodes 80 are in contact with the conductive layer 70 in the via 65 and are in conduction with the source and drain contact regions 31.
  • the conductive layer 70 is a metal material layer or a metal oxide material layer, such as a metal molybdenum layer or an N-type ion doped amorphous silicon layer.
  • a via layer 65 above the source-drain contact region 31 is provided with a conductive layer 70 in contact with the source-drain contact region 31, a source drain 80 and a conductive layer in the via 65.
  • the 70-phase contact is further conducted in the source-drain contact region 31, and the shortage of the contact impedance between the source-drain 80 and the source-drain contact region 31 in the Re-etch LDD technique can be effectively improved.
  • the LTPS TFT substrate of the present invention is formed by etching a via hole on the interlayer insulating layer and the gate insulating layer corresponding to the source/drain contact region by using a photoresist layer, and removing the via hole.
  • a conductive material is deposited at the via location to form a conductive layer in contact with the source and drain contact regions in the via, and then the source drain is contacted with the conductive layer in the via It is electrically connected to the source-drain contact region, which can effectively improve the low contact impedance between the source-drain and source-drain contact regions in Re-etch LDD technology, and can pass Re- without affecting product characteristics.
  • the etch LDD technology reduces a mask process and forms an undercut structure between the via and the photoresist layer, preventing the deposited conductive material from affecting the stripping photoresist layer and ensuring the stripping efficiency of the photoresist layer.
  • a via layer in contact with the source/drain contact region is disposed in the via hole above the source/drain contact region, and the source and drain electrodes are in contact with the conductive layer in the via hole to The source-drain contact region is turned on, which can effectively improve the low contact impedance between the source-drain and source-drain contact regions in Re-etch LDD technology.

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Abstract

本发明提供一种LTPS TFT基板的制作方法及LTPS TFT基板。本发明的LTPS TFT基板的制作方法，在利用光阻层在层间绝缘层和栅极绝缘层上对应于源漏极接触区的上方蚀刻形成过孔之后，并在剥离去除光阻层之前，在所述过孔位置处沉积导电材料而在过孔内形成与所述源漏极接触区相接触的导电层，后续使得源漏极与过孔内的导电层相接触进而与源漏极接触区相导通，从而能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足，进而在不影响产品特性的情况下，可通过Re-etch LDD技术减少一道光罩制程，并且使过孔与光阻层之间形成底切结构，避免所沉积的导电材料对剥离光阻层产生影响，保证光阻层的剥离效率。

Description

LTPS TFT基板的制作方法及LTPS TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种LTPS TFT基板的制作方法及LTPS TFT基板。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光(Active Matrix Organic Light-Emitting Diode，AMOLED)显示器等平板显示装置因具有机身薄、高画质、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本屏幕等。
薄膜晶体管(Thin Film Transistor，TFT)阵列(Array)基板是目前LCD装置和AMOLED装置中的主要组成部件，直接关系到高性能平板显示装置的发展方向，用于向显示器提供驱动电路，通常设置有数条栅极扫描线和数条数据线，该数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅极扫描线相连，当栅极扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。通常阵列基板上薄膜晶体管的结构又包括层叠设置于衬底基板上的栅极、栅极绝缘层、有源层、源漏极及绝缘保护层。
其中，低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管与传统非晶硅(A-Si)薄膜晶体管相比，虽然制作工艺复杂，但因其具有更高的载流子迁移率，被广泛用于中小尺寸高分辨率的LCD和AMOLED显示面板的制作，低温多晶硅被视为实现低成本全彩平板显示的重要材料。
热载流子效应是金属氧化物半导体(Metal Oxide Semiconductor，MOS)器件的一个重要失效机理，随着MOS器件尺寸的日益缩小，器件的热载流子注入效应越来越严重。在LTPS阵列技术中，为了有效抑制LTPS N型金属氧化物半导体(NMOS)器件的热载流子效应，提高器件工作的稳定性及改善器件在负偏置条件下的漏电流，现有的LTPS NMOS制作工艺通常采取轻掺杂漏区(Lightly Doped Drain，LDD)方式，即是在多晶硅(Poly-Si)沟道中靠近源漏极的附近设置一个低掺杂的区域，让该低掺杂的区域也承受部分分压。
目前通常被应用的LDD工艺为MASK(光罩)LDD技术及Re-etch(重复蚀刻)LDD技术，其中采用MASK LDD技术制作LTPS阵列基板的过程包括如下步骤：
步骤S10、如图1所示，在基板100上依次形成缓冲层200和多晶硅有源层300，在所述多晶硅有源层300上涂覆光阻，并通过一道光罩经曝光显影处理形成光阻图案980，以所述光阻图案980为遮蔽层，向多晶硅有源层300两端植入高剂量的N型离子(磷离子P+，1x10 14～1x10 15ions/cm 2)，形成源漏极接触区310；
步骤S20、如图2所示，剥离去除所述光阻图案980，在所述缓冲层200上沉积形成覆盖多晶硅有源层300的栅极绝缘层400，在所述栅极绝缘层400上沉积并图案化第一金属层，在多晶硅有源层300对应欲形成沟道区的上方形成栅极500，以所述栅极500为遮蔽层，向多晶硅有源层300两端植入低剂量的N型离子(P+，1x10 12～1x10 13ions/cm 2)，形成沟道区320以及沟道区320和源漏极接触区310之间的LDD区330；
步骤S30、如图3所示，在栅极500与栅极绝缘层400上沉积形成层间绝缘层600，在所述层间绝缘层600上涂覆光阻，并经曝光显影处理形成光阻层900；
步骤S40、如图4所示，以所述用光阻层900为遮蔽层，对所述层间绝缘层600和栅极绝缘层400进行蚀刻，在层间绝缘层600和栅极绝缘层400上对应所述有源层300两侧的源漏极接触区310的上方形成过孔650；
步骤S50、如图5所示，在所述层间绝缘层600上沉积并图案化第二金属层，得到源漏极800，所述源漏极800经由所述过孔650与所述有源层300两侧的源漏极接触区310相接触。
现有Re-etch LDD技术与上述MASK LDD技术相比，在图案化形成多晶硅有源层300后，不通过光阻图案980对有源层300进行重掺杂，而是对第一金属层进行两次蚀刻，以第一次蚀刻后的金属图案来定义重掺杂的源漏极接触区域310，以该金属图案为遮蔽层，向多晶硅有源层300两端进行重掺杂而植入高剂量的N型离子，接着对第一金属层进行第二次蚀刻得到栅极500，以栅极500为遮蔽层，向多晶硅有源层300两端进行轻掺杂而植入低剂量的N型离子。相比于MASK LDD技术，Re-etch LDD技术的主要优点为减少一道光刻制程，从而降低一道光罩的生产成本和减少LTPS TFT基板的制程时间，提高生产产能，其缺点主要为Re-etch LDD技术进行重掺杂时需将N型离子穿过栅极绝缘层400，在机台制程能力范围内，大部分的N型离子无法植入到多晶硅有源层300内，导致有源层300两侧 的源漏极接触区310内的离子含量较低，与源漏极800的接触阻抗异常，影响器件性能。
发明内容
本发明的目的在于提供一种LTPS TFT基板的制作方法，能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足。
本发明的目的还在于提供一种LTPS TFT基板，能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足。
为实现上述目的，本发明首先提供一种LTPS TFT基板的制作方法，包括如下步骤：
步骤S1、提供衬底基板，在所述衬底基板上由下至上依次形成缓冲层、多晶硅有源层、栅极绝缘层、栅极及层间绝缘层；
所述多晶硅有源层具有位于两端的源漏极接触区、位于中间的沟道区及位于源漏极接触区与沟道区之间的LDD区；所述栅极绝缘层在所述缓冲层上覆盖所述多晶硅有源层；所述栅极在所述栅极绝缘层上对应位于所述多晶硅有源层的沟道区的上方；所述层间绝缘层在所述栅极绝缘层上覆盖所述栅极；
步骤S2、在所述层间绝缘层上涂布光阻，经曝光、显影后得到光阻层，所述光阻层对应于所述源漏极接触区的上方具有过孔图案而露出层间绝缘层；
步骤S3、以所述光阻层为遮蔽层，对所述层间绝缘层和栅极绝缘层进行干法蚀刻，在所述层间绝缘层和栅极绝缘层上对应于所述源漏极接触区的上方形成过孔，使形成的所述过孔和光阻层之间形成底切结构，所述过孔的纵截面呈倒置梯形，所述光阻层伸到所述过孔上方而遮盖所述过孔孔壁的顶部；
步骤S4、在所述过孔位置处沉积导电材料，该导电材料穿过所述光阻层在过孔内形成与所述源漏极接触区相接触的导电层，剥离去除所述光阻层及光阻层上的导电材料；
步骤S5、在所述层间绝缘层上沉积并图案化形成源漏极，所述源漏极与所述过孔内的导电层相接触进而与所述源漏极接触区相导通。
所述步骤S4中所沉积形成的导电层为金属材料层或金属氧化物材料层。
所述步骤S4中所沉积形成的导电层为金属钼层。
所述步骤S4中所沉积形成的导电层为N型离子掺杂的非晶硅层。
所述步骤S3中对所述层间绝缘层和栅极绝缘层进行干法蚀刻的蚀刻气体包含氧气，该蚀刻气体还包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种。
所述步骤S1具体包括如下步骤：
步骤S11、提供衬底基板，在所述衬底基板上形成多晶硅层，对所述多晶硅层进行图案化处理，得到多晶硅有源层，在所述缓冲层上形成覆盖多晶硅有源层的栅极绝缘层；
步骤S12、在所述栅极绝缘层沉积金属层，在所述金属层上对应于所述多晶硅有源层中部的上方形成光阻图案，以所述光阻图案为遮蔽层，对所述金属层进行第一次蚀刻形成准栅极，以所述准栅极为遮蔽层，对所述多晶硅有源层两端没有被准栅极遮盖的部分进行N型离子重掺杂，形成多晶硅有源层两端的源漏极接触区；
步骤S13、对所述金属层进行第二次蚀刻，使所述准栅极两侧被横向蚀刻而宽度减小，形成栅极，剥离去除所述光阻图案，以所述栅极为遮蔽层，对所述多晶硅有源层两端没有被栅极遮盖的部分进行N型离子轻掺杂，得到多晶硅有源层中部的对应位于所述栅极下方的沟道区以及所述源漏极接触区和沟道区之间的LDD区；
步骤S14、在所述栅极绝缘层上形成覆盖所述栅极的层间绝缘层。
所述步骤S12中，通过干法蚀刻对所述金属层进行第一次蚀刻，对所述金属层进行第一次蚀刻的蚀刻气体包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种。
所述步骤S13中，通过干法蚀刻对所述金属层进行第二次蚀刻，对所述金属层进行第二次蚀刻的蚀刻气体包含氧气和氯气。
所述步骤S12和步骤S13中对所述多晶硅有源层中掺入的离子均为磷离子；
所述步骤S12中，对所述多晶硅有源层进行N型离子重掺杂时的掺杂离子浓度为1x10 14-1x10 15ions/cm 2；
所述步骤S13中，对所述多晶硅有源层进行N型离子轻掺杂时的掺杂离子浓度为1x10 12-1x10 13ions/cm 2。
本发明还提供一种LTPS TFT基板，包括衬底基板、设于衬底基板上的缓冲层、设于缓冲层上的多晶硅有源层、在所述缓冲层上覆盖所述多晶硅有源层的栅极绝缘层、设于所述栅极绝缘层上的栅极、在所述栅极绝缘层上覆盖所述栅极的层间绝缘层及设于所述层间绝缘层上的源漏极；
所述多晶硅有源层具有位于两端的源漏极接触区、位于中间的沟道区 及位于源漏极接触区与沟道区之间的LDD区；
所述栅极在所述栅极绝缘层上对应位于所述多晶硅有源层的沟道区的上方；
所述层间绝缘层和栅极绝缘层在对应于所述源漏极接触区的上方设有过孔，所述过孔的纵截面呈倒置梯形，所述过孔内设有一层与所述源漏极接触区相接触的且纵截面呈U形的导电层；
所述源漏极与所述过孔内的导电层相接触进而与所述源漏极接触区相导通。
所述导电层为金属材料层或金属氧化物材料层。
本发明的有益效果：本发明的LTPS TFT基板的制作方法，在利用光阻层在层间绝缘层和栅极绝缘层上对应于源漏极接触区的上方蚀刻形成过孔之后，并在剥离去除光阻层之前，在所述过孔位置处沉积导电材料而在过孔内形成与所述源漏极接触区相接触的导电层，后续使得源漏极与过孔内的导电层相接触进而与源漏极接触区相导通，从而能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足，进而在不影响产品特性的情况下，可通过Re-etch LDD技术减少一道光罩制程，并且使过孔与光阻层之间形成底切结构，避免所沉积的导电材料对剥离光阻层产生影响，保证光阻层的剥离效率。本发明的LTPS TFT基板，源漏极接触区上方的过孔内设有一层与源漏极接触区相接触的导电层，源漏极与所述过孔内的导电层相接触进而与所述源漏极接触区相导通，能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为采用MASK LDD技术制作LTPS TFT基板的步骤S10的示意图；
图2为采用MASK LDD技术制作LTPS TFT基板的步骤S20的示意图；
图3为采用MASK LDD技术制作LTPS TFT基板的步骤S30的示意图；
图4为采用MASK LDD技术制作LTPS TFT基板的步骤S40的示意图；
图5为采用MASK LDD技术制作LTPS TFT基板的步骤S50的示意图；
图6为本发明的LTPS TFT基板的制作方法的流程示意图；
图7为本发明的LTPS TFT基板的制作方法的步骤S12的示意图；
图8为本发明的LTPS TFT基板的制作方法的步骤S13的示意图；
图9为本发明的LTPS TFT基板的制作方法的步骤S2的示意图；
图10为本发明的LTPS TFT基板的制作方法的步骤S3的示意图；
图11-12为本发明的LTPS TFT基板的制作方法的步骤S4的示意图；
图13为本发明的LTPS TFT基板的制作方法的步骤S5的示意图暨本发明的LTPS TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6，本发明提供一种LTPS TFT基板的制作方法，包括如下步骤：
步骤S1、提供衬底基板10，在所述衬底基板10上由下至上依次形成缓冲层20、多晶硅有源层30、栅极绝缘层40、栅极50及层间绝缘层60。
具体地，本实施例采用Re-etch LDD技术制作LTPS TFT基板，所述步骤S1具体包括如下步骤：
步骤S11、提供衬底基板10，在所述衬底基板10上形成多晶硅层，对所述多晶硅层进行图案化处理，得到多晶硅有源层30，在所述缓冲层20上形成覆盖多晶硅有源层30的栅极绝缘层40。
具体地，所述步骤11中，所述多晶硅层的制作过程为：在所述缓冲层20上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，所述低温结晶工艺为固相晶化、准分子激光晶化、快速热退火、或金属横向诱导法。
步骤S12、如图7所示，在所述栅极绝缘层40沉积金属层，在所述金属层上对应于所述多晶硅有源层30中部的上方形成光阻图案98，以所述光阻图案98为遮蔽层，对所述金属层进行第一次蚀刻形成准栅极51，以所述准栅极51为遮蔽层，对所述多晶硅有源层30两端没有被准栅极51遮盖的部分进行N型离子重掺杂，形成多晶硅有源层30两端的源漏极接触区31。
具体地，所述步骤S12中对所述多晶硅有源层30中掺入的离子为磷离子，对所述多晶硅有源层30进行N型离子重掺杂时的掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
具体地，所述步骤S12中，通过干法蚀刻对所述金属层进行第一次蚀刻，对所述金属层进行第一次蚀刻的蚀刻气体包含六氟化硫(SF 6)、五氟乙烷(C 2HF 5)及四氟化碳(CF 4)中的一种或多种。
步骤S13、如图8所示，对所述金属层进行第二次蚀刻，使所述准栅极51两侧被横向蚀刻而宽度减小，形成栅极50，剥离去除所述光阻图案98，以所述栅极50为遮蔽层，对所述多晶硅有源层30两端没有被栅极50遮盖的部分进行N型离子轻掺杂，得到多晶硅有源层30中部的对应位于所述栅极50下方的沟道区32以及所述源漏极接触区31和沟道区32之间的LDD区33。
具体地，所述步骤S13中对所述多晶硅有源层30中掺入的离子为磷离子，对所述多晶硅有源层30进行N型离子轻掺杂时的掺杂离子浓度为1x10 12-1x10 13ions/cm 2。
具体地，所述步骤S13中，通过干法蚀刻对所述金属层进行第二次蚀刻，对所述金属层进行第二次蚀刻的蚀刻气体包含氧气(O 2)和氯气。
步骤S14、在所述栅极绝缘层40上形成覆盖所述栅极50的层间绝缘层60。
步骤S2、如图9所示，在所述层间绝缘层60上涂布光阻，经曝光、显影后得到光阻层90，所述光阻层90对应于所述源漏极接触区31的上方具有过孔图案95而露出层间绝缘层60。
步骤S3、如图10所示，以所述光阻层90为遮蔽层，对所述层间绝缘层60和栅极绝缘层40进行干法蚀刻，在所述层间绝缘层60和栅极绝缘层40上对应于所述源漏极接触区31的上方形成过孔65，使形成的所述过孔65和光阻层90形成底切(under cut)结构，所述过孔65的纵截面呈倒置梯形，所述光阻层90伸到所述过孔65上方而遮盖所述过孔65孔壁的顶部。
具体地，所述步骤S3中对所述层间绝缘层60和栅极绝缘层40进行干法蚀刻的蚀刻气体包含氧气，该蚀刻气体还包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种；从而所述步骤S3中，通过调节蚀刻气体中氧气的含量、或者层间绝缘层60的致密性，来提高蚀刻气体对层间绝缘层60和光阻层90的蚀刻选择比，进而使得过孔65和光阻层90形成如图10所示的底切结构，以使得后续光阻层90易于剥离。
步骤S4、如图11-12所示，在所述过孔64位置处沉积导电材料，该导电材料穿过所述光阻层90在过孔65内形成与所述源漏极接触区31相接触的导电层70，剥离去除所述光阻层90及光阻层90上的导电材料，由于所述过孔65和光阻层90之间形成了底切结构，所述导电层70与所述光阻层90上的导电材料由所述光阻层90所断开，因此沉积导电材料后并不会对光阻层90的剥离造成影响。
具体地，所述步骤S4中所沉积形成的导电层70为金属材料层或金属 氧化物材料层，例如金属钼层或N型离子掺杂的非晶硅层。
步骤S5、在所述层间绝缘层60上沉积并图案化形成源漏极80，所述源漏极80与所述过孔65内的导电层70相接触进而与所述源漏极接触区31相导通。
本发明的LTPS TFT基板的制作方法，在利用光阻层90在层间绝缘层60和栅极绝缘层40上对应于源漏极接触区31的上方蚀刻形成过孔65之后，并在剥离去除光阻层90之前，在所述过孔65位置处沉积导电材料而在过孔65内形成与所述源漏极接触区31相接触的导电层70，后续使得源漏极80与过孔65内的导电层70相接触进而与源漏极接触区31相导通，从而能够有效改善Re-etch LDD技术中源漏极80与源漏极接触区31接触阻抗偏高的不足，进而在不影响产品特性的情况下，可通过Re-etch LDD技术减少一道光罩制程，并且使过孔65与光阻层90之间形成底切结构，避免所沉积的导电材料对剥离光阻层90产生影响，保证光阻层90的剥离效率。
请参阅图13，基于上述的LTPS TFT基板的制作方法，本发明还提供一种LTPS TFT基板，包括衬底基板10、设于衬底基板10上的缓冲层20、设于缓冲层20上的多晶硅有源层30、在所述缓冲层20上覆盖所述多晶硅有源层30的栅极绝缘层40、设于所述栅极绝缘层40上的栅极50、在所述栅极绝缘层40上覆盖所述栅极50的层间绝缘层60及设于所述层间绝缘层60上的源漏极80；
所述多晶硅有源层30具有位于两端的源漏极接触区31、位于中间的沟道区32及位于源漏极接触区31与沟道区32之间的LDD区33；
所述栅极50在所述栅极绝缘层40上对应位于所述多晶硅有源层30的沟道区32的上方；
所述层间绝缘层60和栅极绝缘层40在对应于所述源漏极接触区31的上方设有过孔65，所述过孔65的纵截面呈倒置梯形，所述过孔65内设有一层与所述源漏极接触区31相接触的且纵截面呈U形的导电层70；
所述源漏极80与所述过孔65内的导电层70相接触进而与所述源漏极接触区31相导通。
具体地，所述导电层70为金属材料层或金属氧化物材料层，例如金属钼层或N型离子掺杂的非晶硅层。
本发明的LTPS TFT基板，源漏极接触区31上方的过孔65内设有一层与源漏极接触区31相接触的导电层70，源漏极80与所述过孔65内的导电层70相接触进而与所述源漏极接触区31相导通，能够有效改善Re-etch LDD技术中源漏极80与源漏极接触区31接触阻抗偏高的不足。
综上所述，本发明的LTPS TFT基板的制作方法，在利用光阻层在层间绝缘层和栅极绝缘层上对应于源漏极接触区的上方蚀刻形成过孔之后，并在剥离去除光阻层之前，在所述过孔位置处沉积导电材料而在过孔内形成与所述源漏极接触区相接触的导电层，后续使得源漏极与过孔内的导电层相接触进而与源漏极接触区相导通，从而能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足，进而在不影响产品特性的情况下，可通过Re-etch LDD技术减少一道光罩制程，并且使过孔与光阻层之间形成底切结构，避免所沉积的导电材料对剥离光阻层产生影响，保证光阻层的剥离效率。本发明的LTPS TFT基板，源漏极接触区上方的过孔内设有一层与源漏极接触区相接触的导电层，源漏极与所述过孔内的导电层相接触进而与所述源漏极接触区相导通，能够有效改善Re-etch LDD技术中源漏极与源漏极接触区接触阻抗偏高的不足。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种LTPS TFT基板的制作方法，包括如下步骤：
    步骤S1、提供衬底基板，在所述衬底基板上由下至上依次形成缓冲层、多晶硅有源层、栅极绝缘层、栅极及层间绝缘层；
    所述多晶硅有源层具有位于两端的源漏极接触区、位于中间的沟道区及位于源漏极接触区与沟道区之间的LDD区；所述栅极绝缘层在所述缓冲层上覆盖所述多晶硅有源层；所述栅极在所述栅极绝缘层上对应位于所述多晶硅有源层的沟道区的上方；所述层间绝缘层在所述栅极绝缘层上覆盖所述栅极；
    步骤S2、在所述层间绝缘层上涂布光阻，经曝光、显影后得到光阻层，所述光阻层对应于所述源漏极接触区的上方具有过孔图案而露出层间绝缘层；
    步骤S3、以所述光阻层为遮蔽层，对所述层间绝缘层和栅极绝缘层进行干法蚀刻，在所述层间绝缘层和栅极绝缘层上对应于所述源漏极接触区的上方形成过孔，使形成的所述过孔和光阻层之间形成底切结构，所述过孔的纵截面呈倒置梯形，所述光阻层伸到所述过孔上方而遮盖所述过孔孔壁的顶部；
    步骤S4、在所述过孔位置处沉积导电材料，该导电材料穿过所述光阻层在过孔内形成与所述源漏极接触区相接触的导电层，剥离去除所述光阻层及光阻层上的导电材料；
    步骤S5、在所述层间绝缘层上沉积并图案化形成源漏极，所述源漏极与所述过孔内的导电层相接触进而与所述源漏极接触区相导通。
  2. 如权利要求1所述的LTPS TFT基板的制作方法，其中，所述步骤S4中所沉积形成的导电层为金属材料层或金属氧化物材料层。
  3. 如权利要求2所述的LTPS TFT基板的制作方法，其中，所述步骤S4中所沉积形成的导电层为金属钼层。
  4. 如权利要求2所述的LTPS TFT基板的制作方法，其中，所述步骤S4中所沉积形成的导电层为N型离子掺杂的非晶硅层。
  5. 如权利要求2所述的LTPS TFT基板的制作方法，其中，所述步骤S3中对所述层间绝缘层和栅极绝缘层进行干法蚀刻的蚀刻气体包含氧气，该蚀刻气体还包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种。
  6. 如权利要求1所述的LTPS TFT基板的制作方法，其中，所述步骤 S1具体包括如下步骤：
    步骤S11、提供衬底基板，在所述衬底基板上形成多晶硅层，对所述多晶硅层进行图案化处理，得到多晶硅有源层，在所述缓冲层上形成覆盖多晶硅有源层的栅极绝缘层；
    步骤S12、在所述栅极绝缘层沉积金属层，在所述金属层上对应于所述多晶硅有源层中部的上方形成光阻图案，以所述光阻图案为遮蔽层，对所述金属层进行第一次蚀刻形成准栅极，以所述准栅极为遮蔽层，对所述多晶硅有源层两端没有被准栅极遮盖的部分进行N型离子重掺杂，形成多晶硅有源层两端的源漏极接触区；
    步骤S13、对所述金属层进行第二次蚀刻，使所述准栅极两侧被横向蚀刻而宽度减小，形成栅极，剥离去除所述光阻图案，以所述栅极为遮蔽层，对所述多晶硅有源层两端没有被栅极遮盖的部分进行N型离子轻掺杂，得到多晶硅有源层中部的对应位于所述栅极下方的沟道区以及所述源漏极接触区和沟道区之间的LDD区；
    步骤S14、在所述栅极绝缘层上形成覆盖所述栅极的层间绝缘层。
  7. 如权利要求6所述的LTPS TFT基板的制作方法，其中，所述步骤S12中，通过干法蚀刻对所述金属层进行第一次蚀刻，对所述金属层进行第一次蚀刻的蚀刻气体包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种；
    所述步骤S13中，通过干法蚀刻对所述金属层进行第二次蚀刻，对所述金属层进行第二次蚀刻的蚀刻气体包含氧气和氯气。
  8. 如权利要求6所述的LTPS TFT基板的制作方法，其中，所述步骤S12和步骤S13中对所述多晶硅有源层中掺入的离子均为磷离子；
    所述步骤S12中，对所述多晶硅有源层进行N型离子重掺杂时的掺杂离子浓度为1x10 14-1x10 15ions/cm 2；
    所述步骤S13中，对所述多晶硅有源层(30)进行N型离子轻掺杂时的掺杂离子浓度为1x10 12-1x10 13ions/cm 2。
  9. 一种LTPS TFT基板，包括衬底基板、设于衬底基板上的缓冲层、设于缓冲层上的多晶硅有源层、在所述缓冲层上覆盖所述多晶硅有源层的栅极绝缘层、设于所述栅极绝缘层上的栅极、在所述栅极绝缘层上覆盖所述栅极的层间绝缘层及设于所述层间绝缘层上的源漏极；
    所述多晶硅有源层具有位于两端的源漏极接触区、位于中间的沟道区及位于源漏极接触区与沟道区之间的LDD区；
    所述栅极在所述栅极绝缘层上对应位于所述多晶硅有源层的沟道区的上方；
    所述层间绝缘层和栅极绝缘层在对应于所述源漏极接触区的上方设有过孔，所述过孔的纵截面呈倒置梯形，所述过孔内设有一层与所述源漏极接触区相接触的且纵截面呈U形的导电层；
    所述源漏极与所述过孔内的导电层相接触进而与所述源漏极接触区相导通。
  10. 如权利要求9所述的LTPS TFT基板，其中，所述导电层为金属材料层或金属氧化物材料层。
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