JP2015032729A - 電子部品内蔵多層配線基板及びその製造方法 - Google Patents
電子部品内蔵多層配線基板及びその製造方法 Download PDFInfo
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- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2924/191—Disposition
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Abstract
【解決手段】複数の第1のプリント配線基板を積層して構成され、電子部品パッケージを内蔵する電子部品内蔵多層配線基板であって、電子部品パッケージは、第1の電子部品を内蔵し、この第1の電子部品の電極ピッチよりも広いピッチで第1のプリント配線基板の配線ピッチと同等のピッチの電極をパッケージの最表層に有するように複数の第2のプリント配線基板を積層して構成され、電子部品パッケージの高さと、第1のプリント配線基板又は複数の第1のプリント配線基板の積層体の厚さとが同等である。
【選択図】図1
Description
まず、図3に示すように、多層配線基板1に内蔵される電子部品パッケージ100を作製する(ステップS100)。ここで、電子部品パッケージ100は、例えば次のように製造される。すなわち、図4に示すように、電子部品パッケージ100を構成する各部材、この電子部品パッケージ100に内蔵される第1の電子部品60を作製する(ステップS200)。
7 貫通穴
8a,8b 開口部
10 第1プリント配線基板
20 第2プリント配線基板
30 第3プリント配線基板
40 第4プリント配線基板
50 第5プリント配線基板
60 第1の電子部品
100 電子部品パッケージ
110 第1層の配線基板
120 第2層の配線基板
130 第3層の配線基板
140 第4層の配線基板
200 第2の電子部品
300 第3の電子部品
Claims (8)
- 複数の第1のプリント配線基板を積層して構成され、電子部品パッケージを内蔵する電子部品内蔵多層配線基板であって、
前記電子部品パッケージは、第1の電子部品を内蔵し、この第1の電子部品の電極ピッチよりも広いピッチで前記第1のプリント配線基板の配線ピッチと同等のピッチの電極をパッケージの最表層に有するように複数の第2のプリント配線基板を積層して構成され、
前記電子部品パッケージの高さと、前記第1のプリント配線基板又は複数の前記第1のプリント配線基板の積層体の厚さとが同等である
ことを特徴とする電子部品内蔵多層配線基板。 - 前記電子部品パッケージは、
前記複数の第2のプリント配線基板のうち、
前記第1の電子部品の電極形成面側とは反対側の裏面側に配置される第1層の配線基板、前記第1の電子部品が収容される開口部が形成された第2層の配線基板、前記第1の電子部品の電極ピッチと同等のピッチの導電性ペーストビアが形成され一方の面に前記第1の電子部品の電極ピッチから前記第1のプリント配線基板の配線ピッチへとピッチを拡大させる電極が形成された第3層の配線基板、及び一方の面に前記第1のプリント配線基板の配線ピッチと同等のピッチの電極が形成され導電性ペーストビアが形成された第4層の配線基板を、
前記第2層の配線基板の開口部に前記第1の電子部品を前記第3層の配線基板の導電性ペーストビアと前記第1の電子部品の電極とが対向するように収容した上で、前記第4層の配線基板の導電性ペーストビアと前記第3層の配線基板の電極とが対向するように配置して一括積層してなる
ことを特徴とする請求項1記載の電子部品内蔵多層配線基板。 - 前記電子部品パッケージは、その高さが前記積層体に形成されたパッケージ搭載用の開口部の深さと同等である
ことを特徴とする請求項1又は2記載の電子部品内蔵多層配線基板。 - 前記第2のプリント配線基板は、前記第1のプリント配線基板と同一の材料で形成されている
ことを特徴とする請求項1〜3のいずれか1項記載の電子部品内蔵多層配線基板。 - 前記積層体は、前記第1の電子部品よりも厚さが厚い第2の電子部品を搭載可能な開口部を更に備え、
前記第2の電子部品を前記電子部品パッケージと共に各開口部に搭載した上で、前記積層体及び前記第1のプリント配線基板を一括積層してなる
ことを特徴とする請求項1〜4のいずれか1項記載の電子部品内蔵多層配線基板。 - 前記第1及び第2の電子部品とは異なる第3の電子部品を、前記電子部品パッケージの内蔵箇所の直上又は直下に、前記第1のプリント配線基板の配線ピッチと同等のピッチで形成された前記第3の電子部品の電極と前記電子部品パッケージの電極とが電気的に最短経路で接続されるように表面実装してなる
ことを特徴とする請求項1〜5のいずれか1項記載の電子部品内蔵多層配線基板。 - 複数の第1のプリント配線基板を積層して構成され、電子部品パッケージを内蔵する電子部品内蔵多層配線基板の製造方法であって、
第1の電子部品を内蔵し、この第1の電子部品の電極ピッチよりも広いピッチで前記第1のプリント配線基板の配線ピッチと同等のピッチの電極をパッケージの最表層に有するように複数の第2のプリント配線基板を積層して前記電子部品パッケージを形成する工程と、
前記電子部品パッケージを搭載可能な開口部を有するように前記第1のプリント配線基板を積層した積層体を形成する工程と、
前記開口部に前記電子部品パッケージを搭載した上で、前記積層体と少なくとも一つの前記第1のプリント配線基板とを前記開口部を塞ぐように積層する工程とを備えた
ことを特徴とする電子部品内蔵多層配線基板の製造方法。 - 前記電子部品パッケージを形成する工程では、
前記複数の第2のプリント配線基板のうち、
前記第1の電子部品の電極形成面側とは反対側の裏面側に配置される第1層の配線基板、前記第1の電子部品が収容される開口部が形成された第2層の配線基板、前記第1の電子部品の電極ピッチと同等のピッチの導電性ペーストビアが形成され一方の面に前記第1の電子部品の電極ピッチから前記第1のプリント配線基板の配線ピッチへとピッチを拡大させる電極が形成された第3層の配線基板、及び一方の面に前記第1のプリント配線基板の配線ピッチと同等のピッチの電極が形成され導電性ペーストビアが形成された第4層の配線基板を、
前記第2層の配線基板の開口部に前記第1の電子部品を前記第3層の配線基板の導電性ペーストビアと前記第1の電子部品の電極とが対向するように収容した上で、前記第4層の配線基板の導電性ペーストビアと前記第3層の配線基板の電極とが対向するように配置して一括積層する
ことを特徴とする請求項7記載の電子部品内蔵多層配線基板の製造方法。
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