JP2013247252A - 炭化珪素半導体装置およびその製造方法 - Google Patents
炭化珪素半導体装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 135
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 49
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000002344 surface layer Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 5
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- 230000015556 catabolic process Effects 0.000 description 23
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000005259 measurement Methods 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 10
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- 239000000463 material Substances 0.000 description 9
- 229910052757 nitrogen Inorganic materials 0.000 description 9
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- 238000011156 evaluation Methods 0.000 description 7
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- 239000013078 crystal Substances 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
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Abstract
【解決手段】炭化珪素半導体装置は、第1導電型の半導体基板1と、半導体基板1上に形成された低不純物濃度の第1導電型の半導体層2と、第1導電型の半導体層2に選択的に形成された高不純物濃度の第2導電型の半導体層3と、第2導電型の半導体層3の表面に形成された低不純物濃度の第2導電型のベース層4と、ベース層4の表面層に選択的に形成された第1導電型のソース領域7と、表面からベース層4を貫通して第1導電型の半導体層2に達するように形成された第1導電型のウェル領域6と、ソース領域7とウェル領域6とに挟まれたベース層4の表面にゲート絶縁膜を介して形成されたゲート電極9とを有する。そして、異なるセルのそれぞれの第2導電型の半導体層3の一部同士を、ウェル領域6の下の領域で互いに結合部3aにより結合させる。
【選択図】図1
Description
図1は、本発明の第1実施例のSiC−MOSFETの製造工程を示す断面図である。図1の(a)はp+層が結合していない部分の断面図、(b)は、p+層が結合している部分の断面図である。
本発明の実施例2では、実施例1と同様の製造工程にて1200V、25AのSiC−MOSFETを作成した。この実施例2ではn型半導体基板1の結晶学的面指数は(0001)面に対して4度傾いた面の上に、窒素を1.8×1016cm-3程度含むn型SiC層2を10μm程度エピタキシャル成長させている。その他の工程、およびセル構造は全く同一である。実施例2の素子の電気特性評価結果は、上記図3に示されており、オン抵抗は、実施例1に対し、55%ほど増加するが、通常のSiC−MOSFETに対しては十分低いオン抵抗特性を示していることがわかる。なお、n型半導体基板1の結晶学的面指数は(0001)面に対して0度、2度、8度、10度傾いた面上に、n型SiC層2を同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。
本発明の実施例3では、実施例1と同様の製造工程にて1200V、25AのSiC−MOSFETを作製した。n型半導体基板1の結晶学的面指数は(000−1)面に対して4度傾いた面の上に窒素を1.8×1016cm-3程度含むn型SiC層2を10μm程度エピタキシャル成長させている。
本発明の実施例4の製造方法について説明する。まず、n型のSiC半導体基板1を用意する。不純物として窒素を2×1019cm-3程度含む低抵抗のSiC半導体基板1を用いた。次に、n型半導体基板1の結晶学的面指数は(000−1)面に対して4度傾いた面の上に窒素を1.8×1016cm-3程度含むn型SiC層2を10μm程度エピタキシャル成長させる。つぎに、n型SiC層2の上に幅13μm、厚さ0.5μmのp+層3をエピタキシャル法で形成する。その際の不純物イオンにアルミニウムを用いた。また、不純物濃度は、1.0×1018cm-3となるようにドーズ量を設定した。その際、実施例1と同様、n打ち返し層6の下でp+層3の一部を互いに結合するようにする(図2参照)。実施例4では、6角形セルパターンにて作成したが、4角形セルなどでも問題ない。また、p+層3間において結合していない箇所のp+層3間の距離は2μmとした。
実施例5では、実施例4と同様の製造工程にて1200V、25AのSiC−MOSFETを作製した。ただし、実施例5では、n型半導体基板1の結晶学的面指数は(0001)面に対して4度傾いた面の上に窒素を1.8×1016cm-3程度含むn型SiC層2を10μm程度エピタキシャル成長させた。その他の工程は全く同一である。作製した素子の電気特性評価結果を図4に示す。オン抵抗は、実施例4に対し、50%ほど増加するものの、通常のSiC−MOSFETに対しては十分低いオン抵抗特性を示していることがわかる。なお、n型半導体基板1の結晶学的面指数は(0001)面に対して0度、2度、8度、10度傾いた面上同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。
2 SiC層
3 p+層
4 ベース層
6 n打ち返し層
7 ソース層
8 コンタクト層
11 ソース電極
12 裏面電極
20 セル
Claims (9)
- 半導体基板内部に半導体装置構造が作り込まれ、前記半導体装置構造に電気的接触をとるための電極と、外部から前記電極と電気的接触をとるための電極パッドとを備え、前記電極パッドの下部の前記半導体基板にも前記半導体装置構造が作成された炭化珪素半導体装置であって、
前記半導体装置構造は、
第1導電型の半導体基板と、前記半導体基板上に形成された低不純物濃度の第1導電型の半導体層と、前記第1導電型の半導体層に選択的に形成された高不純物濃度の第2導電型の半導体層と、前記第2導電型の半導体層の表面に形成された低不純物濃度の第2導電型のベース層と、前記ベース層の表面層に選択的に形成された第1導電型のソース領域と、表面から前記ベース層を貫通して前記第1導電型の半導体層に達するように形成された第1導電型のウェル領域と、前記ソース領域と前記ウェル領域とに挟まれた前記ベース層の表面にゲート絶縁膜を介して形成された制御電極とを具備し、
異なるセルのそれぞれの前記第2導電型の半導体層の一部同士が、前記ウェル領域の下の領域で互いに結合されていることを特徴とする炭化珪素半導体装置。 - 前記電極パッドがゲートパッドであることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記第1導電型の半導体基板の結晶学的面指数は(000−1)面に対して平行な面もしくは10度以内に傾いた面であることを特徴とする請求項1または2に記載の炭化珪素半導体装置。
- 前記第1導電型の半導体基板の結晶学的面指数は(0001)面に対して平行な面もしくは10度以内に傾いた面であることを特徴とする請求項1または2に記載の炭化珪素半導体装置。
- 前記ゲートパッド部分の前記ソース領域が前記ウェル領域によって、前記ゲートパッドの部分以外の前記半導体装置構造のソース領域と電気的に結合されていることを特徴とする請求項1〜4のいずれか一つに記載の炭化珪素半導体装置。
- 前記ソース領域が第2導電型領域に挟まれてなることを特徴とする請求項5に記載の炭化珪素半導体装置。
- 前記ゲートパッド部分の前記ソース領域が直線状に形成されたことを特徴とする請求項5に記載の炭化珪素半導体装置。
- 前記ゲートパッド部分の前記ソース領域が多角形の網の目状に形成されたことを特徴とする請求項5に記載の炭化珪素半導体装置。
- 第1導電型の半導体基板と、前記半導体基板上に形成された低不純物濃度の第1導電型の半導体層と、前記第1導電型の半導体層に選択的に形成された高不純物濃度の第2導電型の半導体層と、前記第2導電型の半導体層の表面に形成された低不純物濃度の第2導電型のベース層と、前記ベース層の表面層に選択的に形成された第1導電型のソース領域と、表面から前記ベース層を貫通して前記第1導電型の半導体層に達するように形成された第1導電型のウェル領域と、前記ソース領域と前記ウェル領域とに挟まれた前記ベース層の表面にゲート絶縁膜を介して形成された制御電極と、を具備し、異なるセルのそれぞれの前記第2導電型の半導体層の一部同士が、前記ウェル領域の下の領域で互いに結合された炭化珪素半導体装置であって、
前記半導体基板上に前記第1導電型の半導体層をエピタキシャル成長により形成し、
前記第1導電型の半導体層の表面に前記第2導電型の半導体層をイオン注入法により選択的に形成し、
前記第1導電型の半導体層と前記第2導電型の半導体層の上に、前記ベース層をエピタキシャル成長法により形成し、
前記ベース層の表面層に前記ソース領域と、表面から前記ベース層を貫通して前記第1導電型の半導体層に達する前記ウェル領域とをイオン注入法により選択的に形成した
ことを特徴とする炭化珪素半導体装置の製造方法。
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