JP2011192954A - 半導体ウェハ、及び半導体装置の製造方法 - Google Patents
半導体ウェハ、及び半導体装置の製造方法 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
【解決手段】シリコン基板とシリコン基板より硬度の高い化合物半導体層を含む積層体とを積層した半導体ウェハ1を準備するステップと、積層体をシリコン基板が露出するまでエッチングして、平行に延伸するストライプ状の複数の溝が形成されたトレンチ領域21を格子状に形成するステップと、溝の内部に化合物半導体層よりも硬度の低い材料を埋め込むステップと、トレンチ領域21に周囲を囲まれた素子配置領域に半導体装置22を形成するステップと、トレンチ領域21の内側に定義されるダイシングライン300をブレードを用いてダイシングして、半導体ウェハ1を半導体装置22毎に複数のチップに分割するステップとを含む。
【選択図】図1
Description
図1に本発明の第1の実施形態に係る半導体ウェハ1の上面図を示す。図2は、図1に一点鎖線で示した領域Aを拡大した図であり、図3は半導体ウェハ1の断面図である。
第1の実施形態の変形例に係る半導体装置22は、図13に示すように、積層体20の底面と側面とのなす角θが90°以下になるように、積層体20の側面を底面に対して傾斜させる。例えば、積層体20の底面と側面とのなす角θは60°〜80°程度である。
本発明の第2の実施形態に係る半導体装置22の断面図を図14に示す。図14に示した半導体装置22は、埋め込み領域100の側面及び底面に沿って高抵抗領域120が配置されていることが、図4に示した半導体装置22と異なる。高抵抗領域120の抵抗値は、絶縁膜の抵抗値と同程度である。高抵抗領域120の内側は、例えば、非結晶(アモルファス)シリコンなどの導電性の材料により埋め込まれている。図14に示した半導体装置22の製造方法の例を以下に説明する。
本発明の第3の実施形態に係る半導体装置22は、図17に示すように、埋め込み領域100内部に空洞101が存在する点が、図4に示した半導体装置22と異なる。例えばボイドが発生するように溝110を埋め込むことにより、埋め込み領域100内部に空洞101を形成することができる。図17に示した半導体装置22の製造方法の例を以下に説明する。
上記のように、本発明は第1乃至第3の実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
10…シリコン基板
20…積層体
21…トレンチ領域
22…半導体装置
30…保護膜
40…マスク酸化膜
40a…開口部
41、42…酸化膜
41a、42a…開口部
51、52…金属膜
60…ブレード
100…埋め込み領域
101…空洞
110…溝
120…高抵抗領域
200…素子配置領域
201…バッファ層
202…キャリア走行層
203…キャリア供給層
205…二次元キャリアガス層
211…ソース電極
212…ドレイン電極
213…ゲート電極
300…ダイシングライン
Claims (6)
- シリコン基板と前記シリコン基板より硬度の高い化合物半導体層を含む積層体とを積層した半導体ウェハを準備するステップと、
前記積層体の一部を厚さ方向に前記シリコン基板が露出するまでエッチング除去して、互いに平行に延伸するストライプ状の複数の溝が形成されたトレンチ領域を格子状に形成するステップと、
前記溝の内部に前記化合物半導体層よりも硬度の低い材料を埋め込んで埋め込み領域を形成するステップと、
前記トレンチ領域に周囲を囲まれた前記積層体の素子配置領域のそれぞれに、半導体装置を形成するステップと、
前記トレンチ領域の内側に定義される複数の前記埋め込み領域を含むダイシングラインを、ブレードを用いてダイシングすることによって、前記半導体ウェハを前記半導体装置毎に複数のチップに分割するステップと
を含むことを特徴とする半導体装置の製造方法。 - 前記埋め込み領域の上面が前記積層体の上面と同一平面レベルになるように、前記溝を埋め込むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記溝の延伸する方向に直交する方向に沿った前記溝の断面形状が、底部が狭く上部が広いテーパ形状になるように、前記溝を形成することを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記埋め込み領域の側面及び底面に高抵抗領域を形成する工程を更に含むことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。
- 前記埋め込み領域の内部に空洞を形成するように、前記溝の内部に前記化合物半導体層よりも硬度の低い材料を埋め込むことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- シリコン基板と、
前記シリコン基板上に配置され、互いに平行に延伸し且つ底部が前記シリコン基板に接するストライプ状の複数の埋め込み領域が配置されたトレンチ領域が格子状に形成された、前記シリコン基板よりも硬度の高い化合物半導体層を含む積層体と
を備えることを特徴とする半導体ウェハ。
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JP2010155572A JP5625558B2 (ja) | 2010-02-22 | 2010-07-08 | 半導体ウェハ、及び半導体装置の製造方法 |
US13/023,861 US8642447B2 (en) | 2010-02-22 | 2011-02-09 | Semiconductor wafer and manufacturing method of semiconductor device |
TW100105387A TWI443731B (zh) | 2010-02-22 | 2011-02-18 | Semiconductor wafers, and semiconductor devices |
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US9196731B2 (en) | 2013-09-03 | 2015-11-24 | Renesas Electronics Corporation | Semiconductor device |
JP2017041616A (ja) * | 2015-08-21 | 2017-02-23 | サンケン電気株式会社 | 化合物半導体素子 |
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JP2015517217A (ja) * | 2012-04-16 | 2015-06-18 | コーニンクレッカ フィリップス エヌ ヴェ | W字形メサを作成する方法及び装置 |
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US9711404B2 (en) | 2015-03-16 | 2017-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP2017041616A (ja) * | 2015-08-21 | 2017-02-23 | サンケン電気株式会社 | 化合物半導体素子 |
JP2018157022A (ja) * | 2017-03-16 | 2018-10-04 | 三菱電機株式会社 | 半導体装置 |
JP2020004881A (ja) * | 2018-06-29 | 2020-01-09 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP2021141273A (ja) * | 2020-03-09 | 2021-09-16 | キオクシア株式会社 | 半導体ウェハおよび半導体チップ |
JP7443097B2 (ja) | 2020-03-09 | 2024-03-05 | キオクシア株式会社 | 半導体ウェハおよび半導体チップ |
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US20110204488A1 (en) | 2011-08-25 |
US8642447B2 (en) | 2014-02-04 |
JP5625558B2 (ja) | 2014-11-19 |
TW201218261A (en) | 2012-05-01 |
TWI443731B (zh) | 2014-07-01 |
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