JP2011138812A - 電源モジュール - Google Patents
電源モジュール Download PDFInfo
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- JP2011138812A JP2011138812A JP2009296007A JP2009296007A JP2011138812A JP 2011138812 A JP2011138812 A JP 2011138812A JP 2009296007 A JP2009296007 A JP 2009296007A JP 2009296007 A JP2009296007 A JP 2009296007A JP 2011138812 A JP2011138812 A JP 2011138812A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】電源モジュールとしてのDCDCコンバータは、ICチップ7が内蔵された電子部品内蔵基板と、その上に載置された入力側キャパシタC1等とを備えるものである。電子部品内蔵基板は、入力側キャパシタC1とは反対側に、入力電圧が入力される入力電圧端子VINを有し、ICチップ7は、入力電圧端子VINからの入力電圧が、所定の接地電位に接続される入力側キャパシタC1を経由して入力される入力電圧端子71を有するものである。そして、入力電圧端子71と入力側キャパシタC1とが接続される配線に、ビア導体(抵抗R3)が形成されるものである。
【選択図】図19
Description
図1は、本発明による電源モジュールの好適な一実施形態であるDCDCコンバータ1(電源モジュール)の構造を概略的に示す断面図であり、図2は、DCDCコンバータ1の等価回路図である。
Claims (5)
- 電子部品が内蔵された基板と、
前記基板上に載置され、且つ、所定の接地電位に接続される入力側キャパシタと、
前記基板に設けられ、且つ、入力電圧が入力される第1入力端子と、
を備え、
前記第1入力端子は、前記入力側キャパシタと電気的に接続され、
前記電子部品は、前記基板に設けられた第1ビア導体を介して前記入力側キャパシタと電気的に接続されている、
電源モジュール。 - 前記第1入力端子は、前記基板に設けられた第2ビア導体を介して前記入力側キャパシタと電気的に接続されている、
請求項1記載の電源モジュール。 - 前記第1入力端子及び前記電子部品は、前記入力側キャパシタを構成する一対の電極のうち接地されていない方の電極に接続されている、
請求項1又は2記載の電源モジュール。 - 前記電子部品は、前記入力電圧に応じた電圧が入力される第2入力端子を有し、
前記第1入力端子及び前記入力側キャパシタが接続される配線、並びに、前記第2入力端子及び前記入力側キャパシタが接続される配線は、前記第2入力端子が形成される層とは異なる層で短絡されている、
請求項1乃至3のいずれか1項記載の電源モジュール。 - 前記基板上に載置され、且つ、前記基板に内蔵された電子部品とは異なる電子部品を備え、
前記電子部品は、前記第2入力端子は、前記異なる電子部品とは反対側を向くように配置される、
請求項1乃至4のいずれか1項記載の電源モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009296007A JP5190811B2 (ja) | 2009-12-25 | 2009-12-25 | 電源モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009296007A JP5190811B2 (ja) | 2009-12-25 | 2009-12-25 | 電源モジュール |
Publications (2)
Publication Number | Publication Date |
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JP2011138812A true JP2011138812A (ja) | 2011-07-14 |
JP5190811B2 JP5190811B2 (ja) | 2013-04-24 |
Family
ID=44349984
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Application Number | Title | Priority Date | Filing Date |
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JP2009296007A Active JP5190811B2 (ja) | 2009-12-25 | 2009-12-25 | 電源モジュール |
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JP (1) | JP5190811B2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020511110A (ja) * | 2017-02-08 | 2020-04-09 | ファラデー セミ, インコーポレイテッド | チップ埋め込み型電力変換器 |
US11557962B2 (en) | 2016-02-09 | 2023-01-17 | Faraday Semi, Inc. | Chip embedded power converters |
US11621230B2 (en) | 2019-04-17 | 2023-04-04 | Faraday Semi, Inc. | Electrical devices and methods of manufacture |
US11652062B2 (en) | 2019-02-19 | 2023-05-16 | Faraday Semi, Inc. | Chip embedded integrated voltage regulator |
US11855534B2 (en) | 2020-07-29 | 2023-12-26 | Faraday Semi, Inc. | Power converters with bootstrap |
US11990839B2 (en) | 2022-06-21 | 2024-05-21 | Faraday Semi, Inc. | Power converters with large duty cycles |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188302A (ja) * | 2001-12-20 | 2003-07-04 | Kyocera Corp | 複合電子部品 |
JP2005045013A (ja) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 回路モジュールとその製造方法 |
JP2009049046A (ja) * | 2007-08-13 | 2009-03-05 | Tdk Corp | 電子部品モジュール |
-
2009
- 2009-12-25 JP JP2009296007A patent/JP5190811B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188302A (ja) * | 2001-12-20 | 2003-07-04 | Kyocera Corp | 複合電子部品 |
JP2005045013A (ja) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 回路モジュールとその製造方法 |
JP2009049046A (ja) * | 2007-08-13 | 2009-03-05 | Tdk Corp | 電子部品モジュール |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11557962B2 (en) | 2016-02-09 | 2023-01-17 | Faraday Semi, Inc. | Chip embedded power converters |
US11996770B2 (en) | 2016-02-09 | 2024-05-28 | Faraday Semi, Inc. | Chip embedded power converters |
JP2020511110A (ja) * | 2017-02-08 | 2020-04-09 | ファラデー セミ, インコーポレイテッド | チップ埋め込み型電力変換器 |
JP7221221B2 (ja) | 2017-02-08 | 2023-02-13 | ファラデー セミ, インコーポレイテッド | チップ埋め込み型電力変換器 |
US11652062B2 (en) | 2019-02-19 | 2023-05-16 | Faraday Semi, Inc. | Chip embedded integrated voltage regulator |
US11621230B2 (en) | 2019-04-17 | 2023-04-04 | Faraday Semi, Inc. | Electrical devices and methods of manufacture |
US11855534B2 (en) | 2020-07-29 | 2023-12-26 | Faraday Semi, Inc. | Power converters with bootstrap |
US11990839B2 (en) | 2022-06-21 | 2024-05-21 | Faraday Semi, Inc. | Power converters with large duty cycles |
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JP5190811B2 (ja) | 2013-04-24 |
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