JP5105106B2 - 電子部品内蔵モジュール - Google Patents
電子部品内蔵モジュール Download PDFInfo
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- JP5105106B2 JP5105106B2 JP2009295991A JP2009295991A JP5105106B2 JP 5105106 B2 JP5105106 B2 JP 5105106B2 JP 2009295991 A JP2009295991 A JP 2009295991A JP 2009295991 A JP2009295991 A JP 2009295991A JP 5105106 B2 JP5105106 B2 JP 5105106B2
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- electronic component
- substrate
- signal line
- component built
- wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1は、本発明による電子部品内蔵モジュールの好適な一実施形態であるDCDCコンバータ1(電子部品内蔵モジュール)の構造を概略的に示す断面図であり、図2は、DCDCコンバータ1の等価回路図である。
Claims (7)
- 第1電子部品が内蔵された基板と、前記基板上に載置された第2電子部品と、を有する電子部品内蔵モジュールであって、
前記基板には、前記第2電子部品を経由して当該電子部品内蔵モジュールから出力される出力信号を監視するフィードバック用の信号ラインが設けられており、
前記フィードバック用の信号ラインの少なくとも一部は、前記第1電子部品に対して前記第2電子部品とは反対側に形成されており、且つ、前記基板の面方向において、前記第1電子部品の実装領域と重なり合うように配置される、
電子部品内蔵モジュール。 - 前記基板には、当該電子部品内蔵モジュールを駆動する駆動用の信号ラインが設けられており、
前記フィードバック用の信号ラインの少なくとも一部は、前記基板の面方向において、前記駆動用の信号ラインの少なくとも一部を横断する方向に形成される、
請求項1記載の電子部品内蔵モジュール。 - 前記フィードバック用の信号ラインと前記駆動用の信号ラインが同層に設けられている、
請求項2記載の電子部品内蔵モジュール。 - 前記基板には、前記フィードバック用の信号ラインと前記第2電子部品との間に、所定の接地電位に接続された第1グラウンド層が設けられている、
請求項1から3のいずれか1項記載の電子部品内蔵モジュール。 - 前記第1グラウンド層は、前記基板の面方向において、前記第1電子部品の実装領域を覆い、且つ、前記第1電子部品の実装領域よりも大きい面積を有するように形成される、
請求項4記載の電子部品内蔵モジュール。 - 前記基板には、前記フィードバック用の信号ラインに近接して、所定の接地電位に接続された第2グラウンド層が設けられている、
請求項1から5のいずれか1項記載の電子部品内蔵モジュール。 - 前記第1電子部品は、該第1電子部品の出力端子が、前記第2電子部品とは反対側を向くように配置される、
請求項1から6のいずれか1項記載の電子部品内蔵モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009295991A JP5105106B2 (ja) | 2009-12-25 | 2009-12-25 | 電子部品内蔵モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009295991A JP5105106B2 (ja) | 2009-12-25 | 2009-12-25 | 電子部品内蔵モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011138810A JP2011138810A (ja) | 2011-07-14 |
JP5105106B2 true JP5105106B2 (ja) | 2012-12-19 |
Family
ID=44349982
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009295991A Active JP5105106B2 (ja) | 2009-12-25 | 2009-12-25 | 電子部品内蔵モジュール |
Country Status (1)
Country | Link |
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JP (1) | JP5105106B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5338875B2 (ja) * | 2011-08-25 | 2013-11-13 | 株式会社村田製作所 | Dc−dcコンバータ |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2682477B2 (ja) * | 1994-11-16 | 1997-11-26 | 日本電気株式会社 | 回路部品の実装構造 |
JP2001291817A (ja) * | 2000-04-05 | 2001-10-19 | Sony Corp | 電子回路装置および多層プリント配線板 |
JP4217438B2 (ja) * | 2002-07-26 | 2009-02-04 | Fdk株式会社 | マイクロコンバータ |
JP4182140B2 (ja) * | 2005-12-14 | 2008-11-19 | 新光電気工業株式会社 | チップ内蔵基板 |
JP2008147573A (ja) * | 2006-12-13 | 2008-06-26 | Nec System Technologies Ltd | 多層基板装置 |
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2009
- 2009-12-25 JP JP2009295991A patent/JP5105106B2/ja active Active
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JP2011138810A (ja) | 2011-07-14 |
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