JP2010245290A - 半導体装置の製造方法 - Google Patents
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
【解決手段】半導体層3を貫通する貫通電極4と、集積回路7と、を有する半導体チップの製造方法であって、分離層2と分離層上に形成された半導体層3とを有する第1の基板1を用意する工程と、半導体層に集積回路を形成する工程と、半導体層に分離層には到達しない深さを有する穴又は溝4を形成する工程と、穴又は溝に導電体を充填する工程と、半導体層に第2の基板11を貼り合わせて貼り合わせ構造体を得る工程と、貼り合せ構造体を分離層で分離することにより、半導体層が移設された第2の基板を得る工程と、分離されて露出した半導体層の裏面側部分の少なくとも一部を除去して、導電体の底部を露出させる工程と、を含む。
【選択図】図1
Description
を含む半導体チップの製造方法が記載されている。
分離層2と前記分離層2の上に形成された半導体層3とを有する第1の基板(半導体基板)1を用意する工程と、
前記半導体層に集積回路7を形成する工程と、
前記半導体層に前記分離層には到達しない深さを有する溝4を形成する工程と、
前記溝に導電体を充填する工程と、
前記半導体層に第2の基板11を貼り合わせて貼り合わせ構造体を得る工程と、
前記貼り合せ構造体を前記分離層に沿って分離することにより、前記半導体層が移設された前記第2の基板を得る工程と、
分離されて露出した前記半導体層の裏面側の少なくとも一部を除去して、前記導電体の底部を露出させる工程と、
を含み、
前記半導体層の前記溝内に設けられ前記半導体層を貫通する貫通電極4と、前記集積回路7と、を有する半導体チップの製造方法である。
図1(a)に示すように、半導体基板1の表面には、分離層2と、転写される半導体層3とが形成されたものを用意する。更に、半導体層3には、その表面側に集積回路7が形成される。第1の基板1としては、バルクシリコンウエハなどの単結晶半導体基板が好ましく用いられる。
また、先に説明したように必要に応じて分離層の一部を残存させて電磁波等のノイズからチップを保護するシールドとして機能させることもできる。この場合には貫通電極を形成する部分の分離層のみを選択的に除去すれば良い。分離層を選択的に除去する方法としては残存させる分離層部分にマスクを形成し選択的にエッチングする方法や、インクジェット等によりエッチングする部分に選択的にエッチャントを供給する方法を用いることができる。
実施形態1はいわゆるウエハレベルでチップを積層する場合に好適な方法を示した。
2 分離層
3 半導体層
7 集積回路
11 第2の基板又は第3の基板
Claims (5)
- 半導体層を貫通する貫通電極と、集積回路と、を有する半導体チップの製造方法であって、
分離層と前記分離層の上に形成された半導体層とを有する第1の基板を用意する工程と、
前記半導体層に集積回路を形成する工程と、
前記半導体層に前記分離層には到達しない深さを有する穴又は溝を形成する工程と、
前記穴又は溝に導電体を充填する工程と、
前記半導体層に第2の基板を貼り合わせて貼り合わせ構造体を得る工程と、
前記貼り合せ構造体を前記分離層で分離することにより、前記半導体層が移設された前記第2の基板を得る工程と、
分離されて露出した前記半導体層の裏面側の少なくとも一部を除去して、前記導電体の底部を露出させる工程と、
を含む半導体チップの製造方法。 - 前記第2の基板は集積回路と接合パッドとを有し、前記第1の基板の前記半導体層の表面に形成された前記貫通電極と前記第2の基板の接合パッドとを電気的に接続し、前記半導体チップを前記集積回路の上に積層する工程を含み、3次元実装された半導体チップを得ることを特徴とする請求項1に記載の半導体チップの製造方法。
- 前記第2の基板は前記集積回路と前記接合パッドとを有する半導体チップ領域が複数並置して作製されたウエハであり、前記第1の基板は前記半導体層に集積回路と前記貫通電極となる導電体を有する半導体チップ領域が複数並置して作製されたウエハであり、
前記第1の基板と前記第2の基板とを、前記半導体チップ領域同士が対向するように貼り合わせて貼り合わせ構造体を得る工程と、
前記集積回路を有する半導体チップが積層されたウエハを各集積回路領域毎に分離独立させるためにダイシングする工程と、を含み、
3次元実装された半導体チップを得ることを特徴とする請求項1に記載の半導体チップの製造方法。 - 前記半導体層を基板は一時的な支持基板である第3の基板に転写する工程と、
前記第3の基板に転写後の前記半導体層を、前記集積回路毎に分離独立させるために、ダイシングする工程と、
ダイシングされた、集積回路を含む半導体チップを、貫通電極が重なるように積層する工程と、を含み、
3次元実装された半導体チップを得ることを特徴とする請求項1に記載の半導体チップの製造方法。 - 前記半導体層の裏面側の少なくとも一部をエッチング及び研磨の少なくともいずれか一方により除去して、前記導電体の底部を露出する請求項1乃至4のいずれか一項に記載の半導体チップの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009092319A JP5409084B2 (ja) | 2009-04-06 | 2009-04-06 | 半導体装置の製造方法 |
TW099108710A TW201110311A (en) | 2009-04-06 | 2010-03-24 | Method of manufacturing semiconductor chip |
PCT/JP2010/002446 WO2010116698A2 (en) | 2009-04-06 | 2010-04-02 | Method of manufacturing semiconductor chip |
US13/262,830 US8871640B2 (en) | 2009-04-06 | 2010-04-02 | Method of manufacturing semiconductor chip |
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JP2009092319A JP5409084B2 (ja) | 2009-04-06 | 2009-04-06 | 半導体装置の製造方法 |
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Publication Number | Publication Date |
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JP2010245290A true JP2010245290A (ja) | 2010-10-28 |
JP5409084B2 JP5409084B2 (ja) | 2014-02-05 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009092319A Expired - Fee Related JP5409084B2 (ja) | 2009-04-06 | 2009-04-06 | 半導体装置の製造方法 |
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Country | Link |
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US (1) | US8871640B2 (ja) |
JP (1) | JP5409084B2 (ja) |
TW (1) | TW201110311A (ja) |
WO (1) | WO2010116698A2 (ja) |
Cited By (3)
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JP2012134231A (ja) * | 2010-12-20 | 2012-07-12 | Disco Abrasive Syst Ltd | 積層デバイスの製造方法及び積層デバイス |
CN102693923A (zh) * | 2011-03-25 | 2012-09-26 | 株式会社迪思科 | 半导体器件晶片的接合方法 |
KR101907907B1 (ko) * | 2014-01-27 | 2018-10-15 | 고쿠리츠켄큐카이하츠호진 상교기쥬츠 소고켄큐쇼 | 패키지 형성 방법 및 mems용 패키지 |
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FR2980919B1 (fr) * | 2011-10-04 | 2014-02-21 | Commissariat Energie Atomique | Procede de double report de couche |
KR101946005B1 (ko) * | 2012-01-26 | 2019-02-08 | 삼성전자주식회사 | 그래핀 소자 및 그 제조방법 |
CN104198079A (zh) * | 2014-07-30 | 2014-12-10 | 肇庆爱晟电子科技有限公司 | 一种高精度高可靠快速响应热敏芯片及其制作方法 |
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- 2009-04-06 JP JP2009092319A patent/JP5409084B2/ja not_active Expired - Fee Related
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- 2010-03-24 TW TW099108710A patent/TW201110311A/zh unknown
- 2010-04-02 WO PCT/JP2010/002446 patent/WO2010116698A2/en active Application Filing
- 2010-04-02 US US13/262,830 patent/US8871640B2/en not_active Expired - Fee Related
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JP2006019429A (ja) * | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置および半導体ウエハならびにそれらの製造方法 |
JP2006287118A (ja) * | 2005-04-04 | 2006-10-19 | Canon Inc | 半導体装置及びその製造方法 |
JP2008135553A (ja) * | 2006-11-28 | 2008-06-12 | Fujitsu Ltd | 基板積層方法及び基板が積層された半導体装置 |
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TW201110311A (en) | 2011-03-16 |
JP5409084B2 (ja) | 2014-02-05 |
WO2010116698A2 (en) | 2010-10-14 |
US8871640B2 (en) | 2014-10-28 |
US20120028414A1 (en) | 2012-02-02 |
WO2010116698A3 (en) | 2011-01-06 |
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