JP2009032804A - 半導体装置及びその製造方法 - Google Patents
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- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000015654 memory Effects 0.000 abstract description 53
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- 238000009825 accumulation Methods 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 12
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- 230000001681 protective effect Effects 0.000 description 4
- 101100309717 Arabidopsis thaliana SD22 gene Proteins 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 101100309712 Arabidopsis thaliana SD11 gene Proteins 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- -1 Silicon Oxide Nitride Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
【解決手段】本発明は、半導体基板10内に設けられた溝部30と、溝部30の両側面に設けられた絶縁膜からなる電荷蓄積層20と、溝部30内に電荷蓄積層を介し埋め込まれたワード線22と、溝部30の両側の半導体基板10内に設けられたソース・ドレイン領域12と、溝部30の両側に設けられたソース・ドレイン領域12のうち一方SD13に接続する第1配線層ML1と、ソース・ドレイン領域12のうち他方SD12に接続する第2配線層ML2と、を具備する半導体装置及びその製造方法である。
【選択図】図2
Description
12 ソース・ドレイン領域
14 チャネル
17 トラップ層
20 ONO膜
22 ワード線
30 溝部
32 層間絶縁膜
34 プラグ金属
36 配線層
38 保護膜
C1〜C4 電荷蓄積領域
Claims (10)
- 半導体層内に設けられた溝部と、
該溝部の両側面に設けられた絶縁膜からなる電荷蓄積層と、
前記溝部内に前記電荷蓄積層を介し埋め込まれたワード線と、
前記溝部の両側の前記半導体層内に設けられたソース・ドレイン領域と、
前記溝部の両側に設けられた前記ソース・ドレイン領域のうち一方に接続する第1配線層と、
前記ソース・ドレイン領域のうち他方に接続する第2配線層と、を具備することを特徴とする半導体装置。 - 前記ソース・ドレイン領域は前記溝部の長手方向に複数設けられていることを特徴とする請求項1記載の半導体装置。
- 前記溝部の長手方向に隣接する前記ソース・ドレイン領域の一方をソース、他方をドレインとし、前記ソースと前記ドレインとを入れ替えることにより、前記電荷蓄積層内の前記溝部の長手方向に2つの電荷蓄積領域を形成することが可能なことを特徴とする請求項2記載の半導体装置。
- 前記第1配線層は前記ソース・ドレイン領域に接続するための第1パッド部を有し、
前記第2配線層は前記ソース・ドレイン領域に接続するための第2パッド部を有し、
前記第1パッド部は前記第1配線層が延在する配線部に対し前記第2配線層側に設けられ、
前記第2パッド部は前記第2配線層が延在する配線部に対し前記第1配線層側に設けられていることを特徴とする請求項1から3のいずれか一項記載の半導体装置。 - 前記半導体層は半導体基板であることを特徴とする請求項1から4のいずれか一項記載の半導体装置。
- 前記半導体層は多結晶シリコン層であることを特徴とする請求項1から4のいずれか一項記載の半導体装置。
- 前記溝部の両側に設けられた電荷蓄積層は、前記溝部の底面上で接続されていることを特徴とする請求項1から6のいずれか一項記載の半導体装置。
- 前記電荷蓄積層は窒化シリコン膜であることを特徴とする請求項1から7のいずれか一項記載の半導体装置。
- 半導体層内の溝部を形成する工程と、
前記溝部の両側面に絶縁膜からなる電荷蓄積層を形成する工程と、
前記溝部の両側の前記半導体層内にソース・ドレイン領域を形成する工程と、
前記溝部内に前記電荷蓄積層を介しワード線を埋め込む工程と、
前記溝部の両側に設けられた前記ソース・ドレイン領域のうち一方に接続する第1配線層を形成する工程と、
前記ソース・ドレイン領域のうち他方に接続する第2配線層を形成する工程と、を具備することを特徴とする半導体装置の製造方法。 - 前記第1配線層を形成する工程と、前記第2配線層を形成する工程と、は同時に行われることを特徴とする請求項9記載の半導体装置の製造方法。
Priority Applications (3)
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JP2007193555A JP5301123B2 (ja) | 2007-07-25 | 2007-07-25 | 半導体装置及びその製造方法 |
US12/180,306 US9269828B2 (en) | 2007-07-25 | 2008-07-25 | Lateral charge storage region formation for semiconductor wordline |
US15/048,886 US10622487B2 (en) | 2007-07-25 | 2016-02-19 | Lateral charge storage region formation for semiconductor wordline |
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JP2007193555A JP5301123B2 (ja) | 2007-07-25 | 2007-07-25 | 半導体装置及びその製造方法 |
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JP2009032804A true JP2009032804A (ja) | 2009-02-12 |
JP5301123B2 JP5301123B2 (ja) | 2013-09-25 |
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JP (1) | JP5301123B2 (ja) |
Cited By (1)
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WO2021005432A1 (ja) * | 2019-07-05 | 2021-01-14 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
Families Citing this family (1)
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US10566334B2 (en) * | 2018-05-11 | 2020-02-18 | Micron Technology, Inc. | Methods used in forming integrated circuitry including forming first, second, and third contact openings |
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JPH05102436A (ja) * | 1991-10-09 | 1993-04-23 | Ricoh Co Ltd | 半導体メモリ装置とその製造方法 |
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- 2007-07-25 JP JP2007193555A patent/JP5301123B2/ja not_active Expired - Fee Related
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05102436A (ja) * | 1991-10-09 | 1993-04-23 | Ricoh Co Ltd | 半導体メモリ装置とその製造方法 |
JP2001501034A (ja) * | 1996-09-23 | 2001-01-23 | シーメンス アクチエンゲゼルシヤフト | 不揮発性メモリセル |
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Cited By (1)
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WO2021005432A1 (ja) * | 2019-07-05 | 2021-01-14 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
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JP5301123B2 (ja) | 2013-09-25 |
US10622487B2 (en) | 2020-04-14 |
US20090184361A1 (en) | 2009-07-23 |
US20160204280A1 (en) | 2016-07-14 |
US9269828B2 (en) | 2016-02-23 |
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