JP2009004650A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2009004650A JP2009004650A JP2007165488A JP2007165488A JP2009004650A JP 2009004650 A JP2009004650 A JP 2009004650A JP 2007165488 A JP2007165488 A JP 2007165488A JP 2007165488 A JP2007165488 A JP 2007165488A JP 2009004650 A JP2009004650 A JP 2009004650A
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- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】電極パッド18、配線20、貫通電極28、ランド30、及びソルダレジスト42が形成されたコア材16に、銅箔を貼り付ける。この銅箔を数段階にわたってウエットエッチングすることで、配線20上に略垂直に立てられ、側面に周方向に沿って全周にわたり形成された複数の突条(周方向に連続した凸部)を備えた表面側端子36を形成する。表面側端子36の周囲を封止樹脂で封止し、封止樹脂層50から表面側端子36の端面36Aを露出させて、封止樹脂層50の表面で再配線を行う。
【選択図】図1
Description
[両面電極パッケージ]
図1は本発明の第1の実施の形態に係る両面電極パッケージの構成を示す概略断面図である。第1の実施の形態に係る両面電極パッケージ10は、樹脂やセラミクスなどの絶縁体で構成された平板状のコア材16を備えている。コア材16には、コア材16を貫通するビア24が複数形成されている。各々のビア24内に、導電性材料26が充填されて、貫通電極28とされている。貫通電極28の一端はコア材16の表面に露出し、貫通電極28の他端はコア材16の裏面に露出している。
次に、上述した両面電極パッケージ10を製造する製造方法について説明する。図5〜図12は第1の実施の形態に係る両面電極パッケージ10の製造工程を示す図である。この製造工程では、図5に示すように、複数のパッケージ基板12が形成された単一の基板フレーム60が用いられる。この基板フレーム60上には、パッケージ基板毎に、両面電極パッケージの構造が形成される。最後に、基板フレーム60をダイシングすることにより、個々の両面電極パッケージに分割(個片化)される。以下、両面電極パッケージ10の製造工程を、順を追って説明する。
まず、複数のパッケージ基板12が形成された単一の基板フレーム60を用意する。図5、図6及び図7は基板フレーム60の準備工程を示す図である。図5は基板フレーム60を表面側から見た平面図である。図6は基板フレーム60の部分断面図である。
次に、個々のパッケージ基板12のチップ配置領域14に、半導体チップ44を配置する。図8は半導体チップの配置工程を示す基板フレームの部分断面図である。ICチップやLSIチップなどの半導体チップ44は、同じ回路を複数形成した半導体ウェーハを、個々の回路に分割(ダイシング)して作製されている。半導体チップ44の表面には、図示はしていないが、複数の電極が設けられている。
次に、半導体チップ44を封止樹脂により封止する。
図9(A)及び(B)は半導体チップの封止工程を示す図である。図9(A)は樹脂封止された基板フレームの部分断面図であり、図9(B)は樹脂封止された基板フレームを表面側から見た平面図である。
次に、封止樹脂50Mを表面側から研削する。
図10は封止樹脂の研削工程を示す図であり、研削後の基板フレームの部分断面図である。基板フレーム60の表面を封止樹脂50Mで被覆した後に、グラインダー等の研削装置を用いて、表面側端子36の端面36Aが露出するまで、封止樹脂50Mを表面側から研削(グラインド)する。こうして封止樹脂層50は、表面側端子36と同じ高さに形成され、封止樹脂層50の表面50Aは端面36Aと同一表面となる。また、表面50Aは、コア材16の表面に平行となる。
次に、封止樹脂層50の表面50A上で再配線を行う。
図11は再配線工程を示す図であり、再配線後の基板フレームの部分断面図である。
最後に、基板フレーム60をダイシングして各パッケージを個片化する。
図12(A)及び(B)はダイシング工程を示す図である。図12(A)はダイシング時の基板フレームの部分断面図であり、図12(B)はダイシング時の基板フレームを表面側から見た平面図である。図12(B)の平面図は、1組(9個)のパッケージ基板12に対応した基板フレーム60の一部を図示する。
[両面電極パッケージ]
図13は本発明の第2の実施の形態に係る両面電極パッケージの構成を示す概略断面図である。第2の実施の形態に係る両面電極パッケージ10Bは、配線20と電気的に接続される表面側端子36Sの一端側(ポストの根元部分)が、他端側より細くなっている以外は、第1の実施の形態に係る両面電極パッケージ10と同じ構造であるため、同じ構成部分には同じ符号を付して説明を省略する。
次に、上述した両面電極パッケージ10Bの製造方法について説明する。両面電極パッケージ10Bは、表面側端子36Sの形成工程以外は、第1の実施の形態に係る両面電極パッケージ10と同様にして製造できるため、相違点以外は説明を省略する。
[両面電極パッケージ]
図14は本発明の第3の実施の形態に係る両面電極パッケージの構成を示す概略断面図である。第3の実施の形態に係る両面電極パッケージ10Cは、配線20と電気的に接続される表面側端子36Wの一端側(ポストの根元部分)に段差部36Pを備え、段差部36Pが半導体チップ44を接続するためのボンディングパッド(図1の外側電極パッド18out)の役目を果す以外は、第1の実施の形態に係る両面電極パッケージ10と同じ構造であるため、同じ構成部分には同じ符号を付して説明を省略する。
次に、上述した両面電極パッケージ10Cの製造方法について説明する。両面電極パッケージ10Cは、表面側端子36Wの形成工程以外は、第1の実施の形態に係る両面電極パッケージ10と同様にして製造できるため、相違点以外は説明を省略する。また、電極パッド18及び配線20の個数や配置は、第1の実施の形態に係る両面電極パッケージ10とは異なるが、電極パッド18及び配線20の個数や配置は製造工程で適宜変更できるので、ここでは説明を省略する。
第4の実施の形態として、2個の両面電極パッケージを積層してマザーボード上に実装したPOPモジュールの一例を示す。両面電極パッケージの構成は、第1の実施の形態と同じであるため、同じ構成部分には同じ符号を付して説明を省略する。
図17は本発明の第4の実施の形態に係るPOPモジュールの構成を示す概略断面図である。第4の実施の形態に係るPOPモジュール70は、マザーボード72と、両面電極パッケージ10Aと、両面電極パッケージ10と、で構成されている。第1の実施の形態で説明した通り、再配線パッド52と配線54とが形成されたパッケージが「両面電極パッケージ10」であり、再配線パッド52と配線54とが形成される前のパッケージが「両面電極パッケージ10A」である。
両面電極パッケージ10Aの裏面側のランド30に、半田ボール76を溶接する。また、両面電極パッケージ10Aの表面に露出した端面36Aに、半田ペースト(図示せず)を塗布し、この半田ペーストを介して半田ボール76を溶接する。こうして、両面電極パッケージ10Aには、半田ボール76、78が外部端子として形成される。両面電極パッケージ10Aの半田ボール76をマザーボード72表面の接続パッド74に圧接し、半田ボール78を両面電極パッケージ10の裏面側のランド30に圧接する。これにより、マザーボード72上に、両面電極パッケージ10A及び両面電極パッケージ10が実装され、POPモジュール70が完成する。
以下、変形例について説明する。
2 パッケージ
3 半田ボール
10 両面電極パッケージ
10A 両面電極パッケージ
10B 両面電極パッケージ
10C 両面電極パッケージ
12 パッケージ基板
14 チップ配置領域
16 コア材
18 電極パッド
18in 内側電極パッド
18out 外側電極パッド
20 配線
20in 内側配線
20out 外側配線
22 領域
24 ビア
26 導電性材料
28 貫通電極
30 ランド
32 領域
36 表面側端子
36S 表面側端子
36W 表面側端子
36A 端面
36B、36C、36D 側面
36P 段差部
42 ソルダレジスト
44 半導体チップ
46 ダイボンド材
48 金属ワイヤ
50 封止樹脂層
50A 表面
50M 封止樹脂
52 再配線パッド
54 配線
56 銅箔
56A、56B、56C 表面
58A、58B、58C、58D マスク
60 基板フレーム
62 領域
64 両面電極パッケージ構造
66 通過領域
70 POPモジュール
72 マザーボード
74 接続パッド
76 半田ボール
78 半田ボール
Claims (13)
- 表面に半導体チップの電極と電気的に接続される電極パッドが形成されると共に、裏面に前記電極パッドと電気的に接続された外部接続パッドが形成されたパッケージ基板と、
前記パッケージ基板の表面に載置され、前記電極が前記電極パッドに電気的に接続された半導体チップと、
側面に周方向に沿って全周にわたり形成された複数の突条を備え、一端が前記電極パッドと電気的に接続された柱状の表面側端子と、
前記半導体チップを封止樹脂で封止すると共に、前記表面側端子の他端が表面に露出するように前記表面側端子の周囲を覆う封止樹脂層と、
を含むことを特徴とする半導体装置。 - 前記表面側端子は、前記パッケージ基板に対し垂直に立てられていることを特徴とする請求項1に記載の半導体装置。
- 前記表面側端子は、円柱状又は円錐状であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記表面側端子は、前記電極パッドと電気的に接続される一端側が、前記封止樹脂層の表面に露出する他端側よりも細くなっていることを特徴とする請求項1から3までのいずれか1項に記載の半導体装置。
- 前記表面側端子は、前記電極パッドと電気的に接続される一端側に、前記半導体チップが配置される方向に突き出した段差部を備えたことを特徴とする請求項1又は2に記載の半導体装置。
- 前記表面側端子は、前記パッケージ基板上に積層した金属膜を複数回に分けてエッチングして形成されたことを特徴とする請求項1から5までのいずれか1項に記載の半導体装置。
- 前記突条は、エッチング時のサイドエッチにより形成されたことを特徴とする請求項6に記載の半導体装置。
- 前記封止樹脂層の表面に形成された再配線パッドと、
前記封止樹脂層の表面に形成され、前記表面側端子の他端と前記再配線パッドとを電気的に接続する接続配線と、
を更に含むことを特徴とする請求項1から7までのいずれか1項に記載の半導体装置。 - 複数のパッケージ基板に分割されるフレーム基板に、パッケージ毎に、パッケージ基板の表面に半導体チップの電極と電気的に接続される電極パッドを形成すると共に、パッケージ基板の裏面に前記電極パッドと電気的に接続された外部接続パッドを形成する工程と、
前記フレーム基板上に金属膜を積層し、一端が各々対応する前記電極パッドと電気的に接続される柱状の表面側端子が複数形成されるように、前記金属膜の表面に所定パターンの第1のマスクを形成する工程と、
前記第1のマスクを用いて前記金属膜が所定厚さになるまで第1のエッチングを行う工程と、
前記第1のエッチングにより形成された柱状部の側面を保護する第2のマスクを形成し、前記第1のマスク及び前記第2のマスクを用いて前記パッケージ基板が露出するまで第2のエッチングを行う工程と、
パッケージ毎に、前記パッケージ基板の表面に前記半導体チップを載置し、前記電極を前記電極パッドに電気的に接続する工程と、
前記表面側端子の一端が露出するように、前記フレーム基板上に前記表面側端子と同じ高さの封止樹脂層を形成し、前記半導体チップの各々を封止樹脂で封止する工程と、
前記半導体チップの各々がパッケージ毎に収納されると共に、前記電極パッド、前記外部接続パッド、前記表面側端子、及び前記封止樹脂層の各々がパッケージ毎に形成された前記フレーム基板をスクライビングして、個々のパッケージに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項8に記載の半導体装置を製造する半導体装置の製造方法であって、
複数のパッケージ基板に分割されるフレーム基板に、パッケージ毎に、パッケージ基板の表面に半導体チップの電極と電気的に接続される電極パッドを形成すると共に、パッケージ基板の裏面に前記電極パッドと電気的に接続された外部接続パッドを形成する工程と、
前記フレーム基板上に金属膜を積層し、一端が各々対応する前記電極パッドと電気的に接続される柱状の表面側端子が複数形成されるように、前記金属膜の表面に所定パターンの第1のマスクを形成する工程と、
前記第1のマスクを用いて前記金属膜が所定厚さになるまで第1のエッチングを行う工程と、
前記第1のエッチングにより形成された柱状部の側面を保護する第2のマスクを形成し、前記第1のマスク及び前記第2のマスクを用いて前記パッケージ基板が露出するまで第2のエッチングを行う工程と、
パッケージ毎に、前記パッケージ基板の表面に前記半導体チップを載置し、前記電極を前記電極パッドに電気的に接続する工程と、
前記表面側端子の他端が露出するように、前記フレーム基板上に前記表面側端子と同じ高さの封止樹脂層を形成し、前記半導体チップの各々を封止樹脂で封止する工程と、
前記封止樹脂層の表面に、パッケージ毎に、再配線パッドを形成すると共に、前記表面側端子の他端と前記再配線パッドとを電気的に接続する接続配線を形成する工程と、
前記半導体チップの各々がパッケージ毎に収納されると共に、前記電極パッド、前記外部接続パッド、前記表面側端子、前記封止樹脂層、前記再配線パッド、及び前記接続配線の各々がパッケージ毎に形成された前記フレーム基板をスクライビングして、個々のパッケージに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記金属膜の表面に形成される前記第1のマスクは、前記電極パッドの前記表面側端子と接続される接続パッド部の各々に対向する位置に小円形のマスクが複数配置されたパターンで形成されたことを特徴とする請求項9又は10に記載の半導体装置の製造方法。
- 第2のエッチングを、第1のエッチングよりもサイドエッチが大きくなる条件で行うことにより、前記表面側端子の前記電極パッドと電気的に接続される一端側を、前記封止樹脂層の表面に露出する他端側よりも細くすることを特徴とする請求項9から11までのいずれか1項に記載の半導体装置の製造方法。
- 前記第2のマスクと共に、前記第1のエッチング後に残った金属膜の表面に前記第2のマスクから前記半導体チップが配置される方向に延びる第3のマスクを更に形成し、前記第1のマスク、前記第2のマスク、及び前記第3のマスクを用いて前記パッケージ基板が露出するまで第2のエッチングを行い、前記表面側端子の前記電極パッドと電気的に接続される一端側に、前記半導体チップが配置される方向に突き出した段差部を形成することを特徴とする請求項9から11までのいずれか1項に記載の半導体装置の製造方法。
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US20080315415A1 (en) | 2008-12-25 |
JP5179787B2 (ja) | 2013-04-10 |
US8659151B2 (en) | 2014-02-25 |
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