JP2008500734A - 集積回路を積重ねる方法およびシステム - Google Patents
集積回路を積重ねる方法およびシステム Download PDFInfo
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Abstract
Description
I.第1の実施形態による集積回路対の形成
図1Aは第1の集積回路102の上面図を示し、図1Bは第2の集積回路104の上面図を示す。第1および第2の集積回路102、104は、表面および裏面を有してよい。表面は、電気的接続ができる「アクティブ」面でよい。裏面は、接続ができないであろう「非アクティブ」面でよい。図1Aおよび図1Bは、集積回路102、104のアクティブ面を示す。
II.第2の実施形態による集積回路対の形成
図4Aは第1の集積回路402の上面図を示し、図4Bは第2の集積回路404の上面図を示す。第1および第2の集積回路402、404は、表面および裏面を有してよい。表面は電気的接続が行われることができる「アクティブ」面でよい。裏面は接続ができないであろう「非アクティブ」面でよい。図4Aおよび図4Bは集積回路402、404のアクティブ面を示す。
III.集積回路スタックの形成
図7は集積回路対のスタック700の側面図を示す。図7は3つの集積回路対702〜706を示す。しかし、スタック700には3つより多いまたは少ない集積回路対があってよい。第1の集積回路対702は、フリップチップボンディングを使用して第2の集積回路710に接続された第1の集積回路708を含んでよい。第2の集積回路対704は、フリップチップボンディングを使用して第2の集積回路714に接続された第1の集積回路712を含んでよい。第3の集積回路対706は、フリップチップボンディングを使用して第2の集積回路718に接続された第1の集積回路716を含んでよい。3つの集積回路対702〜706は、図1〜6に関して説明された方法のいかなる組み合わせを使用することによってでも形成されることができる。
Claims (10)
- 第1の集積回路を第2の集積回路にフリップチップ接合することによって第1の集積回路対を作成するステップと、
第3の集積回路を第4の集積回路にフリップチップ接合することによって第2の集積回路対を作成するステップと、
前記第1の集積回路対を基板に取付けるステップと、
前記第2の集積回路対を前記第1の集積回路対上に積み重ねるステップと、
ワイヤボンディングを使用して前記第2の集積回路を前記基板に接続するステップと、
ワイヤボンディングを使用して前記第4の集積回路を前記基板に接続するステップと、
を組み合わせて備える、集積回路を積み重ねる方法。 - 前記第1、第2、第3、および第4の集積回路は長方形でほぼ同じ大きさである、請求項1に記載の方法。
- 前記第1の集積回路対を作成する前記ステップは、前記第1の集積回路を前記第2の集積回路に対して90度回転するステップと、前記第1および第2の集積回路のアクティブ面を前記フリップチップボンディングの前に互いに向き合うように配置するステップとを含む、請求項1に記載の方法。
- 前記第2の集積回路対を作成する前記ステップは、前記第3の集積回路を前記第4の集積回路に対して90度回転するステップと、前記第3および第4の集積回路のアクティブ面を前記フリップチップボンディングの前に互いに向き合うように配置するステップとを含む、請求項1に記載の方法。
- 第1の集積回路対を作成する前記ステップは、ワイヤボンドパッドを前記第1の集積回路から除去するステップと、前記第1および第2の集積回路のアクティブ面をフリップチップボンディングの前に互いに向き合うように配置するステップとを含む、請求項1に記載の方法。
- 第2の集積回路対を作成する前記ステップは、ワイヤボンドパッドを前記第3の集積回路から除去するステップと、前記第3のおよび第4の集積回路のアクティブ面をフリップチップボンディングの前に互いに向き合うように配置するステップとを含む、請求項1に記載の方法。
- 前記第1の集積回路対を前記基板に接着する前記ステップは、接着剤を使用して前記第2の集積回路の非アクティブ面を前記基板に接着するステップを含み、前記第2の集積回路対を前記第1の集積回路対上に積み重ねるステップは、前記接着剤を使用して前記第4の集積回路の非アクティブ面を前記第1の集積回路の非アクティブ面に接着するステップを含む、請求項1に記載の方法。
- ワイヤボンディングを使用して前記第2の集積回路を前記基板に接続するステップは、前記第2の集積回路と前記基板の間にボンディングワイヤを接着するステップを含み、ワイヤボンディングを使用して前記第4の集積回路を前記基板に接続するステップは、前記第4の集積回路と前記基板の間に前記ボンディングワイヤを接着するステップを含む、請求項1に記載の方法。
- 第1の再分配層を前記第1の集積回路上に、および第2の再分配層を前記第2の集積回路上に堆積するステップをさらに備え、前記第1および第2の再分配層は前記第1の集積回路上で必要な信号が前記第2の集積回路上のワイヤボンドパッドを通して供給される、請求項1に記載の方法。
- 第3の再分配層を前記第3の集積回路上に、および第4の再分配層を前記第4の集積回路上に堆積するステップをさらに備え、前記第3のおよび第4の再分配層は前記第3の集積回路上で必要な信号が前記第4の集積回路上のワイヤボンドパッドを通して供給される、請求項1に記載の方法。
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US10/852,378 | 2004-05-24 | ||
US10/852,378 US7863720B2 (en) | 2004-05-24 | 2004-05-24 | Method and system for stacking integrated circuits |
PCT/US2005/018089 WO2005117117A1 (en) | 2004-05-24 | 2005-05-24 | Method and system for stacking integrated circuits |
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JP2008500734A true JP2008500734A (ja) | 2008-01-10 |
JP4717067B2 JP4717067B2 (ja) | 2011-07-06 |
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US7786562B2 (en) * | 1997-11-11 | 2010-08-31 | Volkan Ozguz | Stackable semiconductor chip layer comprising prefabricated trench interconnect vias |
US7700409B2 (en) | 2004-05-24 | 2010-04-20 | Honeywell International Inc. | Method and system for stacking integrated circuits |
EP1701384A1 (en) * | 2005-03-08 | 2006-09-13 | Sun Microsystems France S.A. | Network chip design for grid communication |
US20090305463A1 (en) * | 2008-06-06 | 2009-12-10 | International Business Machines Corporation | System and Method for Thermal Optimized Chip Stacking |
US8637983B2 (en) * | 2008-12-19 | 2014-01-28 | Ati Technologies Ulc | Face-to-face (F2F) hybrid structure for an integrated circuit |
JP2012015398A (ja) * | 2010-07-02 | 2012-01-19 | Toshiba Corp | 半導体装置 |
JP2012049175A (ja) * | 2010-08-24 | 2012-03-08 | Toshiba Corp | 半導体装置の製造方法 |
US8476720B2 (en) * | 2011-06-29 | 2013-07-02 | Honeywell International Inc. | Systems and methods for vertically stacking a sensor on an integrated circuit chip |
CN110265292B (zh) * | 2019-04-26 | 2021-07-27 | 芯盟科技有限公司 | 三维存储器以及制作方法 |
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Also Published As
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US20050258528A1 (en) | 2005-11-24 |
WO2005117117A1 (en) | 2005-12-08 |
JP4717067B2 (ja) | 2011-07-06 |
EP1756867A1 (en) | 2007-02-28 |
US7863720B2 (en) | 2011-01-04 |
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