JP2008305833A - ウェーハの加工方法 - Google Patents
ウェーハの加工方法 Download PDFInfo
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- JP2008305833A JP2008305833A JP2007149082A JP2007149082A JP2008305833A JP 2008305833 A JP2008305833 A JP 2008305833A JP 2007149082 A JP2007149082 A JP 2007149082A JP 2007149082 A JP2007149082 A JP 2007149082A JP 2008305833 A JP2008305833 A JP 2008305833A
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- 238000003672 processing method Methods 0.000 title claims 4
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 20
- 238000004140 cleaning Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 7
- 230000032258 transport Effects 0.000 description 6
- 230000003028 elevating effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000003825 pressing Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H01L2924/01—Chemical elements
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
Abstract
【解決手段】低誘電率絶縁膜が表面側に積層されたデバイスを有するウェーハを個々のデバイスに分割し、分割後のデバイスを配線基板に実装した後に、実装されたデバイスの側面側から研削砥石を接触させてデバイスの裏面を所望量研削する。低誘電率絶縁膜には垂直荷重がかからないため、低誘電率絶縁膜の破損を防止することができ、デバイスの品質が低下しない。
【選択図】図9
Description
S:分割予定ライン D:デバイス B:バンプ
T:テープ F:フレーム
10:保持テーブル 11:スピンドル 12:切削ブレード
2:配線基板 3:樹脂
4:研削装置
40a:第一のカセット 40b:第二のカセット
41:搬出入手段 410:アーム部 411:保持部
42:位置合わせ手段
43:洗浄手段 430:スピンナーテーブル
44a:第一の搬送手段 44b:第二の搬送手段
45a、45b、45c、45d:チャックテーブル 46:ターンテーブル
47:第一の研削手段
470:スピンドル 471:スピンドルハウジング 472:モータ
473:ホイールマウント 474:研削ホイール
475:第一の砥石 475a:尖鋭部
48:第二の搬送手段
480:スピンドル 481:スピンドルハウジング 482:モータ
483:ホイールマウント 484:研削ホイール
485:第二の砥石 485a:尖鋭部
49:第一の高さ制御手段
490:ガイドレール 491:昇降板 492:パルスモータ
50:第二の高さ制御手段
500:ガイドレール 501:昇降板 502:パルスモータ
Claims (2)
- 低誘電率絶縁膜が表面側に積層された複数のデバイスが分割予定ラインによって区画されて形成されたウェーハを個々のデバイスに分割すると共に所望の厚さに形成するウェーハの加工方法であって、
ウェーハを個々のデバイスに分割する分割工程と、
分割されたデバイスの電極を配線基板の電極にボンディングすると共に、該配線基板とボンディングされたデバイスとの隙間に樹脂を充填して封止するボンディング工程と、
研削装置のチャックテーブルにおいてデバイスがボンディングされた配線基板を保持し、該配線基板を水平方向に移動させて該デバイスの側面側から所定の高さに固定された研削砥石を接触させて該デバイスの裏面を研削して該デバイスを所望量研削するデバイス研削工程と
から構成されるウェーハの加工方法。 - 前記研削砥石は、少なくとも粗加工用研削砥石と仕上げ加工用研削砥石とから構成される請求項1に記載のウェーハの加工方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007149082A JP2008305833A (ja) | 2007-06-05 | 2007-06-05 | ウェーハの加工方法 |
US12/126,261 US7608483B2 (en) | 2007-06-05 | 2008-05-23 | Method of machining wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007149082A JP2008305833A (ja) | 2007-06-05 | 2007-06-05 | ウェーハの加工方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008305833A true JP2008305833A (ja) | 2008-12-18 |
Family
ID=40096245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007149082A Pending JP2008305833A (ja) | 2007-06-05 | 2007-06-05 | ウェーハの加工方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7608483B2 (ja) |
JP (1) | JP2008305833A (ja) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62251054A (ja) * | 1986-04-23 | 1987-10-31 | Hitachi Micro Comput Eng Ltd | 研削方法および研削装置 |
JPH06270041A (ja) * | 1993-03-24 | 1994-09-27 | Disco Abrasive Syst Ltd | 半導体ウェーハの研削方法及び研削装置 |
JP2001057404A (ja) * | 1999-06-07 | 2001-02-27 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2003017513A (ja) * | 2001-07-04 | 2003-01-17 | Toshiba Corp | 半導体装置の製造方法 |
JP2004063515A (ja) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
WO2004047167A1 (ja) * | 2002-11-21 | 2004-06-03 | Nec Corporation | 半導体装置、配線基板および配線基板製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002134650A (ja) * | 2000-10-23 | 2002-05-10 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP4037197B2 (ja) * | 2002-07-17 | 2008-01-23 | 富士フイルム株式会社 | 半導体撮像装置実装構造体の製造方法 |
CN101002307A (zh) * | 2004-07-16 | 2007-07-18 | 株式会社瑞萨科技 | 制造半导体集成电路器件的方法 |
JP2006303051A (ja) | 2005-04-19 | 2006-11-02 | Disco Abrasive Syst Ltd | ウエーハの研削方法および研削装置 |
JP2007123362A (ja) * | 2005-10-25 | 2007-05-17 | Disco Abrasive Syst Ltd | デバイスの製造方法 |
JP4758222B2 (ja) * | 2005-12-21 | 2011-08-24 | 株式会社ディスコ | ウエーハの加工方法および装置 |
JP5073962B2 (ja) * | 2006-05-12 | 2012-11-14 | 株式会社ディスコ | ウエーハの加工方法 |
JP4913517B2 (ja) * | 2006-09-26 | 2012-04-11 | 株式会社ディスコ | ウエーハの研削加工方法 |
-
2007
- 2007-06-05 JP JP2007149082A patent/JP2008305833A/ja active Pending
-
2008
- 2008-05-23 US US12/126,261 patent/US7608483B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62251054A (ja) * | 1986-04-23 | 1987-10-31 | Hitachi Micro Comput Eng Ltd | 研削方法および研削装置 |
JPH06270041A (ja) * | 1993-03-24 | 1994-09-27 | Disco Abrasive Syst Ltd | 半導体ウェーハの研削方法及び研削装置 |
JP2001057404A (ja) * | 1999-06-07 | 2001-02-27 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2003017513A (ja) * | 2001-07-04 | 2003-01-17 | Toshiba Corp | 半導体装置の製造方法 |
JP2004063515A (ja) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
WO2004047167A1 (ja) * | 2002-11-21 | 2004-06-03 | Nec Corporation | 半導体装置、配線基板および配線基板製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7608483B2 (en) | 2009-10-27 |
US20080305578A1 (en) | 2008-12-11 |
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